Lines Matching refs:OffsetReg
5490 const Variable *OffsetReg, int16_t OffsetRegShAmt,
5505 Str << ", OffsetReg=";
5506 if (OffsetReg)
5507 OffsetReg->dump(Func);
5566 Variable **OffsetReg, int32_t OffsetRegShamt,
5568 // OffsetReg==nullptr && Base is Base=Var1+Var2 ==>
5569 // set Base=Var1, OffsetReg=Var2, Shift=0
5572 if (*OffsetReg != nullptr)
5598 *OffsetReg = Var2;
5605 Variable **OffsetReg, OperandARM32::ShiftKind *Kind,
5607 // OffsetReg is OffsetReg=Var*Const && log2(Const)+Shift<=32 ==>
5608 // OffsetReg=Var, Shift+=log2(Const)
5609 // OffsetReg is OffsetReg=Var<<Const && Const+Shift<=32 ==>
5610 // OffsetReg=Var, Shift+=Const
5611 // OffsetReg is OffsetReg=Var>>Const && Const-Shift>=-32 ==>
5612 // OffsetReg=Var, Shift-=Const
5614 if (*OffsetReg == nullptr)
5616 auto *IndexInst = VMetadata->getSingleDefinition(*OffsetReg);
5619 assert(!VMetadata->isMultiDef(*OffsetReg));
5683 *OffsetReg = Var;
5767 Variable *OffsetReg = nullptr;
5804 dumpAddressOpt(Func, BaseVar, OffsetImm, OffsetReg, OffsetRegShamt,
5814 matchAssign(VMetadata, &OffsetReg, &OffsetImm, &Reason)) {
5818 if (CanHaveIndex && matchCombinedBaseIndex(VMetadata, &BaseVar, &OffsetReg,
5824 if (matchShiftedOffsetReg(VMetadata, &OffsetReg, &ShiftKind,
5832 std::swap(BaseVar, OffsetReg);
5843 // [OffsetReg{, LSL Shamt}{, #OffsetImm}] is not legal in ARM, so we have to
5844 // legalize the addressing mode to [BaseReg, OffsetReg{, LSL Shamt}].
5847 // [OffsetReg{, LSL Shamt}{, #OffsetImm}] ->
5849 // use of [BaseReg, OffsetReg{, LSL Shamt}]
5864 OffsetReg != nullptr) {
5865 if (OffsetReg == nullptr) {
5892 assert(OffsetImm == 0 || OffsetReg == nullptr);
5893 assert(OffsetReg == nullptr || CanHaveIndex);
5897 if (OffsetReg != nullptr) {
5899 Context.insert<InstAssign>(OffsetR, OffsetReg);
