Lines Matching refs:Imm
358 #define TestImplRegImm(Dst, Value0, Imm, Size) \
362 "(" #Dst ", " #Value0 ", " #Imm ", " #Size ")"; \
369 Immediate((Imm)&Mask##Size)); \
381 ASSERT_EQ(((Value0)&Mask##Size) & ((Imm)&Mask##Size) ? ValueIfTrue \
541 #define TestImplRegImm(Inst, Dst, Value0, Imm, Type, Size, Op) \
544 "(" #Inst ", " #Dst ", " #Value0 ", Imm(" #Imm "), " #Type #Size \
550 Immediate((Imm)&Mask##Size)); \
557 Op static_cast<Type##Size##_t>((Imm)&Mask##Size)), \
588 #define TestImplAddrImm(Inst, Value0, Imm, Type, Size, Op) \
591 "(" #Inst ", Addr, " #Value0 ", Imm, " #Imm ", " #Type #Size \
596 __ Inst(IceType_i##Size, dwordAddress(T0), Immediate((Imm)&Mask##Size)); \
604 Op static_cast<Type##Size##_t>((Imm)&Mask##Size)), \
747 #define TestImplRegImm(Inst0, Inst1, Dst0, Dst1, Value0, Imm, Op, Size) \
753 ", Imm(" #Imm "), " #Op ", " #Size ")"; \
759 Immediate(uint64_t(Imm) & Mask##Size)); \
761 Immediate((uint64_t(Imm) >> Size) & Mask##Size)); \
767 (uint64_t(Value0) & ResultMask##Size)Op(uint64_t(Imm) & \
811 #define TestImplAddrImm(Inst0, Inst1, Value0, Imm, Op, Size) \
816 "(" #Inst0 ", " #Inst1 ", Addr, " #Value0 ", Imm(" #Imm "), " #Op \
823 Immediate(uint64_t(Imm) & Mask##Size)); \
825 Immediate((uint64_t(Imm) >> Size) & Mask##Size)); \
833 (uint64_t(Value0) & ResultMask##Size)Op(uint64_t(Imm) & \
1074 #define TestImplRegImm(Dst, Value0, Imm, Size) \
1077 "(" #Dst ", " #Value0 ", Imm(" #Imm "), " #Size ")"; \
1081 static_cast<int##Size##_t>((Imm)&Mask##Size); \
1086 __ imul(IceType_i##Size, GPRRegister::Encoded_Reg_##Dst, Immediate(Imm)); \
1404 #define TestImplRegImm(Inst, Dst, Value0, Imm, Op, Type, Size) \
1407 "(" #Inst ", " #Dst ", " #Value0 ", Imm(" #Imm "), " #Op ", " #Type \
1411 Mask##Size & (static_cast<Type##Size##_t>(Value0) Op(Imm) | \
1412 (!IsRol ? 0 : (Value0) >> (Size - Imm))); \
1417 Immediate((Imm)&Mask##Size)); \
1431 ", Imm(" #Count "), " #Op0 ", " #Op1 ", " #Type ", " #Size ")"; \
