Lines Matching refs:Imm
389 #define TestImplRegImm(Dst, Value0, Imm, Size) \
393 "(" #Dst ", " #Value0 ", " #Imm ", " #Size ")"; \
399 Immediate((Imm)&Mask##Size)); \
409 ASSERT_EQ(((Value0)&Mask##Size) & ((Imm)&Mask##Size) ? ValueIfTrue \
570 #define TestImplRegImm(Inst, Dst, Value0, Imm, Type, Size, Op) \
573 "(" #Inst ", " #Dst ", " #Value0 ", Imm(" #Imm "), " #Type #Size \
578 Immediate((Imm)&Mask##Size)); \
585 Op static_cast<Type##Size##_t>((Imm)&Mask##Size)), \
614 #define TestImplAddrImm(Inst, Value0, Imm, Type, Size, Op) \
617 "(" #Inst ", Addr, " #Value0 ", Imm, " #Imm ", " #Type #Size \
622 __ Inst(IceType_i##Size, dwordAddress(T0), Immediate((Imm)&Mask##Size)); \
630 Op static_cast<Type##Size##_t>((Imm)&Mask##Size)), \
774 #define TestImplRegImm(Inst0, Inst1, Dst0, Dst1, Value0, Imm, Op, Size) \
780 ", Imm(" #Imm "), " #Op ", " #Size ")"; \
786 Immediate(uint64_t(Imm) & Mask##Size)); \
788 Immediate((uint64_t(Imm) >> Size) & Mask##Size)); \
794 (uint64_t(Value0) & ResultMask##Size)Op(uint64_t(Imm) & \
836 #define TestImplAddrImm(Inst0, Inst1, Value0, Imm, Op, Size) \
841 "(" #Inst0 ", " #Inst1 ", Addr, " #Value0 ", Imm(" #Imm "), " #Op \
848 Immediate(uint64_t(Imm) & Mask##Size)); \
850 Immediate((uint64_t(Imm) >> Size) & Mask##Size)); \
858 (uint64_t(Value0) & ResultMask##Size)Op(uint64_t(Imm) & \
1100 #define TestImplRegImm(Dst, Value0, Imm, Size) \
1103 "(" #Dst ", " #Value0 ", Imm(" #Imm "), " #Size ")"; \
1107 static_cast<int##Size##_t>((Imm)&Mask##Size); \
1112 __ imul(IceType_i##Size, Encoded_GPR_##Dst(), Immediate(Imm)); \
1393 #define TestImplRegImm(Inst, Dst, Value0, Imm, Op, Type, Size) \
1396 "(" #Inst ", " #Dst ", " #Value0 ", Imm(" #Imm "), " #Op ", " #Type \
1400 Mask##Size & (static_cast<Type##Size##_t>(Value0) Op(Imm) | \
1401 (!IsRol ? 0 : (Value0) >> (Size - Imm))); \
1406 Immediate((Imm)&Mask##Size)); \
1420 ", Imm(" #Count "), " #Op0 ", " #Op1 ", " #Type ", " #Size ")"; \
