Lines Matching refs:bp
137 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
139 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
140 return (REG_RD(bp, BNX2_PCICFG_REG_WINDOW));
144 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
146 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
147 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
151 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
154 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
155 REG_WR(bp, BNX2_CTX_DATA, val);
159 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
164 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
165 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
168 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
169 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
174 val1 = (bp->phy_addr << 21) | (reg << 16) |
177 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
182 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
186 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
202 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
203 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
206 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
207 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
216 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
221 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
222 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
225 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
226 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
231 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
234 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
239 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
251 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
252 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
255 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
256 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
265 bnx2_disable_int(struct bnx2 *bp)
267 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
269 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
274 bnx2_alloc_mem(struct bnx2 *bp)
276 bp->tx_desc_ring = bnx2_bss.tx_desc_ring;
277 bp->tx_desc_mapping = virt_to_bus(bp->tx_desc_ring);
279 bp->rx_desc_ring = bnx2_bss.rx_desc_ring;
280 memset(bp->rx_desc_ring, 0, sizeof(struct rx_bd) * RX_DESC_CNT);
281 bp->rx_desc_mapping = virt_to_bus(bp->rx_desc_ring);
284 bp->status_blk = &bnx2_bss.status_blk;
285 bp->status_blk_mapping = virt_to_bus(&bnx2_bss.status_blk);
287 bp->stats_blk = &bnx2_bss.stats_blk;
289 bp->stats_blk_mapping = virt_to_bus(&bnx2_bss.stats_blk);
295 bnx2_report_fw_link(struct bnx2 *bp)
299 if (bp->link_up) {
302 switch (bp->line_speed) {
304 if (bp->duplex == DUPLEX_HALF)
310 if (bp->duplex == DUPLEX_HALF)
316 if (bp->duplex == DUPLEX_HALF)
322 if (bp->duplex == DUPLEX_HALF)
331 if (bp->autoneg) {
334 bnx2_read_phy(bp, MII_BMSR, &bmsr);
335 bnx2_read_phy(bp, MII_BMSR, &bmsr);
338 bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)
347 REG_WR_IND(bp, bp->shmem_base + BNX2_LINK_STATUS, fw_link_status);
351 bnx2_report_link(struct bnx2 *bp)
353 if (bp->link_up) {
356 printf("%d Mbps ", bp->line_speed);
358 if (bp->duplex == DUPLEX_FULL)
363 if (bp->flow_ctrl) {
364 if (bp->flow_ctrl & FLOW_CTRL_RX) {
366 if (bp->flow_ctrl & FLOW_CTRL_TX)
380 bnx2_report_fw_link(bp);
384 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
388 bp->flow_ctrl = 0;
389 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
392 if (bp->duplex == DUPLEX_FULL) {
393 bp->flow_ctrl = bp->req_flow_ctrl;
398 if (bp->duplex != DUPLEX_FULL) {
402 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
403 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
406 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
408 bp->flow_ctrl |= FLOW_CTRL_TX;
410 bp->flow_ctrl |= FLOW_CTRL_RX;
414 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
415 bnx2_read_phy(bp, MII_LPA, &remote_adv);
417 if (bp->phy_flags & PHY_SERDES_FLAG) {
438 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
441 bp->flow_ctrl = FLOW_CTRL_RX;
446 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
454 bp->flow_ctrl = FLOW_CTRL_TX;
460 bnx2_5708s_linkup(struct bnx2 *bp)
464 bp->link_up = 1;
465 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
468 bp->line_speed = SPEED_10;
471 bp->line_speed = SPEED_100;
474 bp->line_speed = SPEED_1000;
477 bp->line_speed = SPEED_2500;
481 bp->duplex = DUPLEX_FULL;
483 bp->duplex = DUPLEX_HALF;
489 bnx2_5706s_linkup(struct bnx2 *bp)
493 bp->link_up = 1;
494 bp->line_speed = SPEED_1000;
496 bnx2_read_phy(bp, MII_BMCR, &bmcr);
498 bp->duplex = DUPLEX_FULL;
501 bp->duplex = DUPLEX_HALF;
508 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
509 bnx2_read_phy(bp, MII_LPA, &remote_adv);
515 bp->duplex = DUPLEX_FULL;
518 bp->duplex = DUPLEX_HALF;
526 bnx2_copper_linkup(struct bnx2 *bp)
530 bnx2_read_phy(bp, MII_BMCR, &bmcr);
534 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
535 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
539 bp->line_speed = SPEED_1000;
540 bp->duplex = DUPLEX_FULL;
543 bp->line_speed = SPEED_1000;
544 bp->duplex = DUPLEX_HALF;
547 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
548 bnx2_read_phy(bp, MII_LPA, &remote_adv);
552 bp->line_speed = SPEED_100;
553 bp->duplex = DUPLEX_FULL;
556 bp->line_speed = SPEED_100;
557 bp->duplex = DUPLEX_HALF;
560 bp->line_speed = SPEED_10;
561 bp->duplex = DUPLEX_FULL;
564 bp->line_speed = SPEED_10;
565 bp->duplex = DUPLEX_HALF;
568 bp->line_speed = 0;
569 bp->link_up = 0;
575 bp->line_speed = SPEED_100;
578 bp->line_speed = SPEED_10;
581 bp->duplex = DUPLEX_FULL;
584 bp->duplex = DUPLEX_HALF;
592 bnx2_set_mac_link(struct bnx2 *bp)
596 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
597 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
598 (bp->duplex == DUPLEX_HALF)) {
599 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
603 val = REG_RD(bp, BNX2_EMAC_MODE);
609 if (bp->link_up) {
610 switch (bp->line_speed) {
612 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
633 if (bp->duplex == DUPLEX_HALF)
635 REG_WR(bp, BNX2_EMAC_MODE, val);
638 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
640 if (bp->flow_ctrl & FLOW_CTRL_RX)
641 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
642 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
645 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
648 if (bp->flow_ctrl & FLOW_CTRL_TX)
650 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
653 REG_WR(bp
659 bnx2_set_link(struct bnx2 *bp)
664 if (bp->loopback == MAC_LOOPBACK) {
665 bp->link_up = 1;
669 link_up = bp->link_up;
671 bnx2_read_phy(bp, MII_BMSR, &bmsr);
672 bnx2_read_phy(bp, MII_BMSR, &bmsr);
674 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
675 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
678 val = REG_RD(bp, BNX2_EMAC_STATUS);
686 bp->link_up = 1;
688 if (bp->phy_flags & PHY_SERDES_FLAG) {
689 if (CHIP_NUM(bp) == CHIP_NUM_5706)
690 bnx2_5706s_linkup(bp);
691 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
692 bnx2_5708s_linkup(bp);
695 bnx2_copper_linkup(bp);
697 bnx2_resolve_flow_ctrl(bp);
700 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
701 (bp->autoneg & AUTONEG_SPEED)) {
705 bnx2_read_phy(bp, MII_BMCR, &bmcr);
707 bnx2_write_phy(bp, MII_BMCR, bmcr |
711 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
712 bp->link_up = 0;
715 if (bp->link_up != link_up) {
716 bnx2_report_link(bp);
719 bnx2_set_mac_link(bp);
725 bnx2_reset_phy(struct bnx2 *bp)
730 bnx2_write_phy(bp, MII_BMCR, BMCR_RESET);
736 bnx2_read_phy(bp, MII_BMCR, ®);
749 bnx2_phy_get_pause_adv(struct bnx2 *bp)
753 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
756 if (bp->phy_flags & PHY_SERDES_FLAG) {
763 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
764 if (bp->phy_flags & PHY_SERDES_FLAG) {
771 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
772 if (bp->phy_flags & PHY_SERDES_FLAG) {
783 bnx2_setup_serdes_phy(struct bnx2 *bp)
788 if (!(bp->autoneg & AUTONEG_SPEED)) {
792 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
793 bnx2_read_phy(bp, BCM5708S_UP1, &up1);
796 bnx2_write_phy(bp, BCM5708S_UP1, up1);
801 bnx2_read_phy(bp, MII_ADVERTISE, &adv);
804 bnx2_read_phy(bp, MII_BMCR, &bmcr);
807 if (bp->req_duplex == DUPLEX_FULL) {
817 if (bp->link_up) {
818 bnx2_write_phy(bp, MII_ADVERTISE, adv &
821 bnx2_write_phy(bp, MII_BMCR, bmcr |
824 bp->link_up = 0;
825 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
827 bnx2_write_phy(bp, MII_ADVERTISE, adv);
828 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
833 if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
834 bnx2_read_phy(bp, BCM5708S_UP1, &up1);
836 bnx2_write_phy(bp, BCM5708S_UP1, up1);
839 if (bp->advertising & ADVERTISED_1000baseT_Full)
842 new_adv |= bnx2_phy_get_pause_adv(bp);
844 bnx2_read_phy(bp, MII_ADVERTISE, &adv);
845 bnx2_read_phy(bp, MII_BMCR, &bmcr);
847 bp->serdes_an_pending = 0;
850 if (bp->link_up) {
853 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
859 bnx2_write_phy(bp, MII_ADVERTISE, new_adv);
860 bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART |
863 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
872 bp->current_interval = SERDES_AN_TIMEOUT;
873 bp->serdes_an_pending = 1;
874 mod_timer(&bp->timer, jiffies + bp->current_interval);
896 bnx2_setup_copper_phy(struct bnx2 *bp)
901 bnx2_read_phy(bp, MII_BMCR, &bmcr);
903 if (bp->autoneg & AUTONEG_SPEED) {
908 bnx2_read_phy(bp, MII_ADVERTISE, &adv_reg);
912 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
915 if (bp->advertising & ADVERTISED_10baseT_Half)
917 if (bp->advertising & ADVERTISED_10baseT_Full)
919 if (bp->advertising & ADVERTISED_100baseT_Half)
921 if (bp->advertising & ADVERTISED_100baseT_Full)
923 if (bp->advertising & ADVERTISED_1000baseT_Full)
928 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
934 bnx2_write_phy(bp, MII_ADVERTISE, new_adv_reg);
935 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
936 bnx2_write_phy(bp, MII_BMCR, BMCR_ANRESTART |
939 else if (bp->link_up) {
943 bnx2_resolve_flow_ctrl(bp);
944 bnx2_set_mac_link(bp);
950 if (bp->req_line_speed == SPEED_100) {
953 if (bp->req_duplex == DUPLEX_FULL) {
960 bnx2_read_phy(bp, MII_BMSR, &bmsr);
961 bnx2_read_phy(bp, MII_BMSR, &bmsr);
965 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
968 bnx2_read_phy(bp, MII_BMSR, &bmsr);
969 bnx2_read_phy(bp, MII_BMSR, &bmsr);
974 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
981 bp->line_speed = bp->req_line_speed;
982 bp->duplex = bp->req_duplex;
983 bnx2_resolve_flow_ctrl(bp);
984 bnx2_set_mac_link(bp);
991 bnx2_setup_phy(struct bnx2 *bp)
993 if (bp->loopback == MAC_LOOPBACK)
996 if (bp->phy_flags & PHY_SERDES_FLAG) {
997 return (bnx2_setup_serdes_phy(bp));
1000 return (bnx2_setup_copper_phy(bp));
1005 bnx2_init_5708s_phy(struct bnx2 *bp)
1009 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
1010 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
1011 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1013 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
1015 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
1017 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
1019 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
1021 if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
1022 bnx2_read_phy(bp, BCM5708S_UP1, &val);
1024 bnx2_write_phy(bp, BCM5708S_UP1, val);
1027 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
1028 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
1029 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
1031 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1033 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
1035 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
1036 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1039 val = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG) &
1045 is_backplane = REG_RD_IND(bp, bp->shmem_base +
1048 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1050 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
1051 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1059 bnx2_init_5706s_phy(struct bnx2 *bp)
1063 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
1065 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
1066 REG_WR(bp, BNX2_MISC_UNUSED0, 0x300);
1070 bnx2_write_phy(bp, 0x18, 0x7);
1071 bnx2_read_phy(bp, 0x18, &val);
1072 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1074 bnx2_write_phy(bp, 0x1c, 0x6c00);
1075 bnx2_read_phy(bp, 0x1c, &val);
1076 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
1082 bnx2_init_copper_phy(struct bnx2 *bp)
1086 bp->phy_flags |= PHY_CRC_FIX_FLAG;
1088 if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
1089 bnx2_write_phy(bp, 0x18, 0x0c00);
1090 bnx2_write_phy(bp, 0x17, 0x000a);
1091 bnx2_write_phy(bp, 0x15, 0x310b);
1092 bnx2_write_phy(bp, 0x17, 0x201f);
1093 bnx2_write_phy(bp, 0x15, 0x9506);
1094 bnx2_write_phy(bp, 0x17, 0x401f);
1095 bnx2_write_phy(bp, 0x15, 0x14e2);
1096 bnx2_write_phy(bp, 0x18, 0x0400);
1099 bnx2_write_phy(bp, 0x18, 0x7);
1100 bnx2_read_phy(bp, 0x18, &val);
1101 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1103 bnx2_read_phy(bp, 0x10, &val);
1104 bnx2_write_phy(bp, 0x10, val & ~0x1);
1107 bnx2_write_phy(bp, 0x18, 0x7007);
1108 bnx2_read_phy(bp, 0x18, &val);
1109 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
1114 bnx2_init_phy(struct bnx2 *bp)
1119 bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG;
1120 bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG;
1122 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
1124 bnx2_reset_phy(bp);
1126 bnx2_read_phy(bp, MII_PHYSID1, &val);
1127 bp->phy_id = val << 16;
1128 bnx2_read_phy(bp, MII_PHYSID2, &val);
1129 bp->phy_id |= val & 0xffff;
1131 if (bp->phy_flags & PHY_SERDES_FLAG) {
1132 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1133 rc = bnx2_init_5706s_phy(bp);
1134 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1135 rc = bnx2_init_5708s_phy(bp);
1138 rc = bnx2_init_copper_phy(bp);
1141 bnx2_setup_phy(bp);
1147 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
1152 bp->fw_wr_seq++;
1153 msg_data |= bp->fw_wr_seq;
1155 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
1161 val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_MB);
1177 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
1189 bnx2_init_context(struct bnx2 *bp)
1199 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
1216 REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00);
1217 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1221 CTX_WR(bp, 0x00, offset, 0);
1224 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
1225 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1230 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
1236 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
1242 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1244 REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ);
1246 val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC);
1256 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1267 REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val);
1273 bnx2_set_mac_addr(struct bnx2 *bp)
1276 u8 *mac_addr = bp->nic->node_addr;
1280 REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
1285 REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
1291 struct bnx2 *bp = &bnx2;
1295 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
1299 if (!(bp->flags & ASF_ENABLE_FLAG)) {
1305 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
1310 if (rx_mode != bp->rx_mode) {
1311 bp->rx_mode = rx_mode;
1312 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
1315 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
1316 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
1317 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
1321 load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len, u32 rv2p_proc)
1328 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, *rv2p_code);
1330 REG_WR(bp, BNX2_RV2P_INSTR_LOW, *rv2p_code);
1335 REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
1339 REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
1345 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
1348 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
1353 load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
1359 val = REG_RD_IND(bp, cpu_reg->mode);
1361 REG_WR_IND(bp, cpu_reg->mode, val);
1362 REG_WR_IND(bp
1370 REG_WR_IND(bp, offset, fw->text[j]);
1380 REG_WR_IND(bp, offset, fw->data[j]);
1390 REG_WR_IND(bp, offset, fw->sbss[j]);
1400 REG_WR_IND(bp, offset, fw->bss[j]);
1411 REG_WR_IND(bp, offset, fw->rodata[j]);
1416 REG_WR_IND(bp, cpu_reg->inst, 0);
1417 REG_WR_IND(bp, cpu_reg->pc, fw->start_addr);
1420 val = REG_RD_IND(bp, cpu_reg->mode);
1422 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
1423 REG_WR_IND(bp, cpu_reg->mode, val);
1427 bnx2_init_cpus(struct bnx2 *bp)
1438 load_rv2p_fw(bp, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1), RV2P_PROC1);
1439 load_rv2p_fw(bp, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2), RV2P_PROC2);
1451 cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
1485 load_cpu_fw(bp, &cpu_reg, &fw);
1497 cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
1531 load_cpu_fw(bp, &cpu_reg, &fw);
1543 cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
1577 load_cpu_fw(bp, &cpu_reg, &fw);
1589 cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
1623 load_cpu_fw(bp, &cpu_reg, &fw);
1628 bnx2_set_power_state_0(struct bnx2 *bp)
1633 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
1635 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
1643 val = REG_RD(bp, BNX2_EMAC_MODE);
1646 REG_WR(bp, BNX2_EMAC_MODE, val);
1648 val = REG_RD(bp, BNX2_RPM_CONFIG);
1650 REG_WR(bp, BNX2_RPM_CONFIG, val);
1656 bnx2_enable_nvram_access(struct bnx2 *bp)
1660 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
1662 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
1667 bnx2_disable_nvram_access(struct bnx2 *bp)
1671 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
1673 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
1679 bnx2_init_nvram(struct bnx2 *bp)
1686 val = REG_RD(bp, BNX2_NVM_CFG1);
1697 bp->flash_info = flash;
1715 bp->flash_info = flash;
1718 bnx2_enable_nvram_access(bp);
1721 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
1722 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
1723 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
1724 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
1727 bnx2_disable_nvram_access(bp);
1735 bp->flash_info = NULL;
1740 val = REG_RD_IND(bp, bp->shmem_base + BNX2_SHARED_HW_CFG_CONFIG2);
1743 bp->flash_size = val;
1746 bp->flash_size = bp->flash_info->total_size;
1753 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
1760 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
1765 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
1770 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1);
1774 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_RESET_SIGNATURE,
1779 val = REG_RD(bp, BNX2_MISC_ID);
1786 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
1788 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
1789 (CHIP_ID(bp) == CHIP_ID_5706_A1))
1794 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
1809 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
1816 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 0);
1821 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
1824 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
1827 rc = bnx2_alloc_bad_rbuf(bp);
1836 struct bnx2* bp = &bnx2;
1838 if (bp->regview) {
1839 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_UNLOAD);
1840 iounmap(bp->regview);
1845 bnx2_init_chip(struct bnx2 *bp)
1851 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1864 if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz == 133))
1867 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
1868 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & PCIX_FLAG))
1871 REG_WR(bp, BNX2_DMA_CONFIG, val);
1873 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
1874 val = REG_RD(bp, BNX2_TDMA_CONFIG);
1876 REG_WR(bp, BNX2_TDMA_CONFIG, val);
1879 if (bp->flags & PCIX_FLAG) {
1882 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
1884 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
1888 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
1895 bnx2_init_context(bp);
1897 bnx2_init_nvram(bp);
1898 bnx2_init_cpus(bp);
1900 bnx2_set_mac_addr(bp);
1902 val = REG_RD(bp, BNX2_MQ_CONFIG);
1905 REG_WR(bp, BNX2_MQ_CONFIG, val);
1908 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
1909 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
1912 REG_WR(bp, BNX2_RV2P_CONFIG, val);
1915 val = REG_RD(bp, BNX2_TBDR_CONFIG);
1918 REG_WR(bp, BNX2_TBDR_CONFIG, val);
1920 val = bp->mac_addr[0] +
1921 (bp->mac_addr[1] << 8) +
1922 (bp->mac_addr[2] << 16) +
1923 bp->mac_addr[3] +
1924 (bp->mac_addr[4] << 8) +
1925 (bp->mac_addr[5] << 16);
1926 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
1932 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
1934 bp->last_status_idx = 0;
1935 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
1938 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
1940 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
1941 (u64) bp->status_blk_mapping & 0xffffffff);
1942 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
1944 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
1945 (u64) bp->stats_blk_mapping & 0xffffffff);
1946 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
1947 (u64) bp->stats_blk_mapping >> 32);
1949 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
1950 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
1952 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
1953 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
1955 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
1956 (bpbp->comp_prod_trip);
1958 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
1960 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
1962 REG_WR(bp, BNX2_HC_COM_TICKS,
1963 (bp->com_ticks_int << 16) | bp->com_ticks);
1965 REG_WR(bp, BNX2_HC_CMD_TICKS,
1966 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
1968 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks & 0xffff00);
1969 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
1971 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
1972 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_COLLECT_STATS);
1974 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_RX_TMR_MODE |
1980 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
1982 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
1984 if (REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_FEATURE) &
1986 bp->flags |= ASF_ENABLE_FLAG;
1989 bnx2_set_rx_mode(bp->nic);
1991 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
1994 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 0x5ffffff);
1995 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
1999 bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
2005 bnx2_init_tx_ring(struct bnx2 *bp)
2010 txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
2014 txbd->tx_bd_haddr_lo = bp->tx_desc_mapping;
2016 bp->tx_prod = 0;
2017 bp->tx_cons = 0;
2018 bp->hw_tx_cons = 0;
2019 bp->tx_prod_bseq = 0;
2023 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TYPE, val);
2027 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_CMD_TYPE, val);
2030 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_HI, 0);
2032 val = (u64) bp->tx_desc_mapping & 0xffffffff;
2033 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_LO, val);
2037 bnx2_init_rx_ring(struct bnx2 *bp)
2044 bp->rx_buf_use_size = RX_BUF_USE_SIZE;
2045 bp->rx_buf_size = RX_BUF_SIZE;
2047 ring_prod = prod = bp->rx_prod = 0;
2048 bp->rx_cons = 0;
2049 bp->hw_rx_cons = 0;
2050 bp->rx_prod_bseq = 0;
2054 rxbd = &bp->rx_desc_ring[0];
2056 rxbd->rx_bd_len = bp->rx_buf_use_size;
2060 rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping & 0xffffffff;
2065 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_CTX_TYPE, val);
2068 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_HI, 0);
2070 val = bp->rx_desc_mapping & 0xffffffff;
2071 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val);
2073 for (i = 0; (int) i < bp->rx_ring_size; i++) {
2074 rxbd = &bp->rx_desc_ring[RX_RING_IDX(ring_prod)];
2077 bp->rx_prod_bseq += bp->rx_buf_use_size;
2081 bp->rx_prod = prod;
2083 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, bp->rx_prod);
2085 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
2089 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
2093 rc = bnx2_reset_chip(bp, reset_code);
2098 bnx2_init_chip(bp);
2099 bnx2_init_tx_ring(bp);
2100 bnx2_init_rx_ring(bp);
2105 bnx2_init_nic(struct bnx2 *bp)
2109 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
2112 bnx2_init_phy(bp);
2113 bnx2_set_link(bp);
2121 struct bnx2 *bp = &bnx2;
2125 bp->flags = 0;
2126 bp->phy_flags = 0;
2135 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
2136 if (bp->pm_cap == 0) {
2142 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
2143 if (bp->pcix_cap == 0) {
2149 bp->pdev = pdev;
2150 bp->nic = nic;
2155 bp->regview = ioremap(bnx2reg_base, bnx2reg_len);
2157 if (!bp->regview) {
2167 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
2171 bnx2_set_power_state_0(bp);
2173 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
2176 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
2180 bp->flags |= PCIX_FLAG;
2182 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
2187 bp->bus_speed_mhz = 133;
2191 bp->bus_speed_mhz = 100;
2196 bp->bus_speed_mhz = 66;
2201 bp->bus_speed_mhz = 50;
2207 bp->bus_speed_mhz = 33;
2213 bp->bus_speed_mhz = 66;
2215 bp->bus_speed_mhz = 33;
2219 bp->flags |= PCI_32BIT_FLAG;
2222 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2223 reg = REG_RD(bp, PCI_COMMAND);
2225 REG_WR(bp, PCI_COMMAND, reg);
2227 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
2228 !(bp->flags & PCIX_FLAG)) {
2234 bnx2_init_nvram(bp);
2236 reg = REG_RD_IND(bp, BNX2_SHM_HDR_SIGNATURE);
2240 bp->shmem_base = REG_RD_IND(bp, BNX2_SHM_HDR_ADDR_0);
2242 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
2247 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_SIGNATURE);
2256 bp->fw_ver = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_BC_REV);
2258 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_UPPER);
2259 bp->mac_addr[0] = (u8) (reg >> 8);
2260 bp->mac_addr[1] = (u8) reg;
2262 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_LOWER);
2263 bp->mac_addr[2] = (u8) (reg >> 24);
2264 bp->mac_addr[3] = (u8) (reg >> 16);
2265 bp->mac_addr[4] = (u8) (reg >> 8);
2266 bp->mac_addr[5] = (u8) reg;
2268 bp->tx_ring_size = MAX_TX_DESC_CNT;
2269 bp->rx_ring_size = RX_BUF_CNT;
2270 bp->rx_max_ring_idx = MAX_RX_DESC_CNT;
2272 bp->rx_offset = RX_OFFSET;
2274 bp->tx_quick_cons_trip_int = 20;
2275 bp->tx_quick_cons_trip = 20;
2276 bp->tx_ticks_int = 80;
2277 bp->tx_ticks = 80;
2279 bp->rx_quick_cons_trip_int = 6;
2280 bp->rx_quick_cons_trip = 6;
2281 bp->rx_ticks_int = 18;
2282 bp->rx_ticks = 18;
2284 bp->stats_ticks = 1000000 & 0xffff00;
2286 bp->phy_addr = 1;
2289 bp->flags |= NO_WOL_FLAG;
2292 if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) {
2293 bp->phy_flags |= PHY_SERDES_FLAG;
2294 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
2295 bp->phy_addr = 2;
2296 reg = REG_RD_IND(bp, bp->shmem_base +
2299 bp->phy_flags |= PHY_2_5G_CAPABLE_FLAG;
2303 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2304 bp->tx_quick_cons_trip_int =
2305 bp->tx_quick_cons_trip;
2306 bp->tx_ticks_int = bp->tx_ticks;
2307 bp->rx_quick_cons_trip_int =
2308 bp->rx_quick_cons_trip;
2309 bp->rx_ticks_int = bp->rx_ticks;
2310 bp->comp_prod_trip_int = bp->comp_prod_trip;
2311 bp->com_ticks_int = bp->com_ticks;
2312 bp->cmd_ticks_int = bp->cmd_ticks;
2315 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
2316 bp->req_line_speed = 0;
2317 if (bp->phy_flags & PHY_SERDES_FLAG) {
2318 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
2320 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG);
2323 bp->autoneg = 0;
2324 bp->req_line_speed = bp->line_speed = SPEED_1000;
2325 bp->req_duplex = DUPLEX_FULL;
2329 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
2332 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
2335 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_PULSE_MB,
2337 REG_RD_IND(bp, bp->shmem_base + BNX2_DRV_PULSE_MB);
2364 struct bnx2 *bp = &bnx2;
2369 prod = bp->tx_prod;
2371 hw_cons = bp->status_blk->status_tx_quick_consumer_index0;
2381 bnx2_disable(bp->nic);
2382 bnx2_init_board(bp->pdev, bp->nic);
2398 txbd = &bp->tx_desc_ring[ring_prod];
2408 bp->tx_prod_bseq += (size + ETH_HLEN);
2410 REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, prod);
2411 REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq);
2415 bp->tx_prod = prod;
2419 bnx2_poll_link(struct bnx2 *bp)
2423 new_link_state = bp->status_blk->status_attn_bits &
2426 old_link_state = bp->status_blk->status_attn_bits_ack &
2435 bnx2_read_phy(bp, MII_BMSR, &bmsr);
2436 bnx2_read_phy(bp, MII_BMSR, &bmsr);
2438 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
2439 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
2440 REG_RD(bp, BNX2_EMAC_STATUS);
2443 new_link_state = bp->status_blk->status_attn_bits &
2446 old_link_state = bp->status_blk->status_attn_bits_ack &
2455 emac_status = REG_RD(bp, BNX2_EMAC_STATUS);
2458 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
2468 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD,
2472 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD,
2476 bnx2_set_link(bp);
2482 REG_WR(bp, BNX2_HC_COMMAND,
2483 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
2484 REG_RD(bp, BNX2_HC_COMMAND);
2488 return bp->link_up;
2494 struct bnx2 *bp = &bnx2;
2504 if ((bp->status_blk->status_idx == bp->last_status_idx) &&
2505 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
2508 bp->last_status_idx = bp->status_blk->status_idx;
2509 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2512 bp->last_status_idx);
2517 if ((bp->status_blk->status_rx_quick_consumer_index0 != bp->rx_cons) && !retrieve)
2520 if (bp->status_blk->status_rx_quick_consumer_index0 != bp->rx_cons) {
2522 hw_cons = bp->hw_rx_cons = bp->status_blk->status_rx_quick_consumer_index0;
2526 sw_cons = bp->rx_cons;
2527 sw_prod = bp->rx_prod;
2535 data = bus_to_virt(bp->rx_desc_ring[sw_ring_cons].rx_bd_haddr_lo);
2551 memcpy(nic->packet, data + bp->rx_offset, len);
2556 bp->rx_prod_bseq += bp->rx_buf_use_size;
2558 cons_bd = &bp->rx_desc_ring[sw_ring_cons];
2559 prod_bd = &bp->rx_desc_ring[sw_ring_prod];
2569 bp->rx_cons = sw_cons;
2570 bp->rx_prod = sw_prod;
2572 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, bp
2574 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
2580 bnx2_poll_link(bp);
2583 bp->last_status_idx = bp->status_blk->status_idx;
2586 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2589 bp->last_status_idx);
2591 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
2617 struct bnx2 *bp = &bnx2;
2623 memset(bp, 0, sizeof(*bp));
2639 memcpy(nic->node_addr, bp->mac_addr, ETH_ALEN);
2642 (int) ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
2643 (int) ((CHIP_ID(bp) & 0x0ff0) >> 4),
2644 ((bp->flags & PCIX_FLAG) ? "-X" : ""),
2645 ((bp->flags & PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
2646 bp->bus_speed_mhz);
2648 bnx2_set_power_state_0(bp);
2649 bnx2_disable_int(bp);
2651 bnx2_alloc_mem(bp);
2653 rc = bnx2_init_nic(bp);
2658 bnx2_poll_link(bp);
2659 for(i = 0; !bp->link_up && (i < VALID_LINK_TIMEOUT*100); i++) {
2661 bnx2_poll_link(bp);
2664 if (!bp->link_up){
