Lines Matching refs:outl
127 #define SROM_CLK_WRITE(data, ioaddr) outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr);udelay(5);outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr);udelay(5);outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr);udelay(5);
281 outl(DM910X_RESET, ioaddr + DCR0); /* RESET MAC */
283 outl(db->cr0_data, ioaddr + DCR0);
294 outl(0x180, ioaddr + DCR12); /* Let bit 7 output port */
296 outl(0x80, ioaddr + DCR12); /* Issue RESET signal */
299 outl(0x0, ioaddr + DCR12); /* Clear RESET signal */
313 outl(virt_to_le32desc(&txd[0]), ioaddr + DCR4); /* TX DESC address */
316 outl(virt_to_le32desc(&rxd[0]), ioaddr + DCR3); /* RX DESC address */
330 outl(db->cr7_data, ioaddr + DCR7);
332 outl(db->cr15_data, ioaddr + DCR15);
410 outl(0, BASE + DCR7);
426 outl(0x1, BASE + DCR1);
427 outl(db->cr7_data, BASE + DCR7);
439 outl(DM910X_RESET, BASE + DCR0);
520 outl(virt_to_le32desc(&txd[0]), ioaddr + DCR4); /* TX DESC address */
523 outl(virt_to_le32desc(&rxd[0]), ioaddr + DCR3); /* RX DESC address */
564 outl(cr6_tmp, ioaddr + DCR6);
566 outl(cr6_data, ioaddr + DCR6);
652 outl(0x1, BASE + DCR1); /* Issue Tx polling */
667 outl(CR9_SROM_READ, cr9_ioaddr);
668 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
682 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
685 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
690 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
694 outl(CR9_SROM_READ, cr9_ioaddr);
992 outl(phy_data, ioaddr); /* MII Clock Low */
994 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
996 outl(phy_data, ioaddr); /* MII Clock Low */
1009 outl(0x50000, ioaddr);
1012 outl(0x40000, ioaddr);
