Lines Matching refs:hw
68 switch (adapter->hw.mac_type) {
70 swsm = E1000_READ_REG(&adapter->hw, SWSM);
71 E1000_WRITE_REG(&adapter->hw, SWSM,
79 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
80 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
96 E1000_WRITE_REG ( &adapter->hw, IMS, IMS_ENABLE_MASK );
97 E1000_WRITE_FLUSH ( &adapter->hw );
108 E1000_WRITE_REG ( &adapter->hw, IMC, ~0 );
109 E1000_WRITE_FLUSH ( &adapter->hw );
124 struct e1000_hw *hw = &adapter->hw;
129 hw->vendor_id = pdev->vendor;
130 hw->device_id = pdev->device;
132 pci_read_config_word ( pdev, PCI_COMMAND, &hw->pci_cmd_word );
135 hw->fc = E1000_FC_NONE;
145 hw->max_frame_size = MAXIMUM_ETHERNET_VLAN_SIZE +
147 hw->min_frame_size = MINIMUM_ETHERNET_FRAME_SIZE;
151 if ( e1000_set_mac_type ( hw ) ) {
156 switch ( hw->mac_type ) {
163 hw->phy_init_script = 1;
167 e1000_set_media_type ( hw );
169 hw->autoneg = TRUE;
170 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
171 hw->wait_autoneg_complete = TRUE;
173 hw->tbi_compatibility_en = TRUE;
174 hw->adaptive_ifs = TRUE;
178 if ( hw->media_type == e1000_media_type_copper ) {
179 hw->mdix = AUTO_ALL_MODES;
180 hw->disable_polarity_correction = FALSE;
181 hw->master_slave = E1000_MASTER_SLAVE;
242 struct e1000_hw *hw = &adapter->hw;
248 E1000_WRITE_REG ( hw, TDBAH, 0 );
249 E1000_WRITE_REG ( hw, TDBAL, virt_to_bus ( adapter->tx_base ) );
250 E1000_WRITE_REG ( hw, TDLEN, adapter->tx_ring_size );
252 DBG ( "TDBAL: %#08x\n", E1000_READ_REG ( hw, TDBAL ) );
253 DBG ( "TDLEN: %d\n", E1000_READ_REG ( hw, TDLEN ) );
255 /* Setup the HW Tx Head and Tail descriptor pointers */
256 E1000_WRITE_REG ( hw, TDH, 0 );
257 E1000_WRITE_REG ( hw, TDT, 0 );
263 if (hw->mac_type == e1000_82576) {
264 txdctl = E1000_READ_REG ( hw, TXDCTL );
266 E1000_WRITE_REG ( hw, TXDCTL, txdctl );
274 e1000_config_collision_dist ( hw );
276 E1000_WRITE_REG ( hw, TCTL, tctl );
277 E1000_WRITE_FLUSH ( hw );
306 struct e1000_hw *hw = &adapter->hw;
333 E1000_WRITE_REG ( hw, RDT, rx_curr );
387 struct e1000_hw *hw = &adapter->hw;
393 rctl = E1000_READ_REG ( hw, RCTL );
394 E1000_WRITE_REG ( hw, RCTL, rctl & ~E1000_RCTL_EN );
395 E1000_WRITE_FLUSH ( hw );
400 /* Setup the HW Rx Head and Tail Descriptor Pointers and
403 E1000_WRITE_REG ( hw, RDBAL, virt_to_bus ( adapter->rx_base ) );
404 E1000_WRITE_REG ( hw, RDBAH, 0 );
405 E1000_WRITE_REG ( hw, RDLEN, adapter->rx_ring_size );
407 E1000_WRITE_REG ( hw, RDH, 0 );
408 if (hw->mac_type == e1000_82576)
409 E1000_WRITE_REG ( hw, RDT, 0 );
411 E1000_WRITE_REG ( hw, RDT, NUM_RX_DESC - 1 );
416 if (hw->mac_type == e1000_82576) {
417 rxdctl = E1000_READ_REG ( hw, RXDCTL );
423 E1000_WRITE_REG ( hw, RXDCTL, rxdctl );
424 E1000_WRITE_FLUSH ( hw );
426 rxcsum = E1000_READ_REG(hw, RXCSUM);
428 E1000_WRITE_REG ( hw, RXCSUM, 0 );
436 E1000_WRITE_REG ( hw, MRQC, mrqc );
442 E1000_WRITE_REG ( hw, RCTL, rctl );
443 E1000_WRITE_FLUSH ( hw );
456 if (hw->mac_type == e1000_82576)
457 E1000_WRITE_REG ( hw, RDT, NUM_RX_DESC - 1 );
459 DBG ( "RDBAL: %#08x\n", E1000_READ_REG ( hw, RDBAL ) );
460 DBG ( "RDLEN: %d\n", E1000_READ_REG ( hw, RDLEN ) );
461 DBG ( "RCTL: %#08x\n", E1000_READ_REG ( hw, RCTL ) );
477 switch (adapter->hw.mac_type) {
515 E1000_WRITE_REG ( &adapter->hw, PBA, pba );
531 if (adapter->hw.mac_type < e1000_82576) {
533 adapter->hw.fc_high_water = fc_high_water_mark & 0xFFF8;
534 adapter->hw.fc_low_water = adapter->hw.fc_high_water - 8;
537 adapter->hw.fc_high_water = fc_high_water_mark & 0xFFF0;
538 adapter->hw.fc_low_water = adapter->hw.fc_high_water - 16;
541 if (adapter->hw.mac_type == e1000_80003es2lan ||
542 adapter->hw.mac_type == e1000_82576)
543 adapter->hw.fc_pause_time = 0xFFFF;
545 adapter->hw.fc_pause_time = E1000_FC_PAUSE_TIME;
546 adapter->hw.fc_send_xon = 1;
547 adapter->hw.fc = adapter->hw.original_fc;
550 e1000_reset_hw ( &adapter->hw );
552 if ( adapter->hw.mac_type >= e1000_82544 )
553 E1000_WRITE_REG ( &adapter->hw, WUC, 0 );
555 if ( e1000_init_hw ( &adapter->hw ) )
559 if (adapter->hw.mac_type >= e1000_82544 &&
560 adapter->hw.mac_type <= e1000_82547_rev_2 &&
561 adapter->hw.autoneg == 1 &&
562 adapter->hw.autoneg_advertised == ADVERTISE_1000_FULL) {
563 uint32_t ctrl = E1000_READ_REG(&adapter->hw, CTRL);
568 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
571 e1000_phy_get_info ( &adapter->hw, &adapter->phy_info );
574 (adapter->hw.mac_type == e1000_82571 ||
575 adapter->hw.mac_type == e1000_82572)) {
580 e1000_read_phy_reg(&adapter->hw, IGP02E1000_PHY_POWER_MGMT,
583 e1000_write_phy_reg(&adapter->hw, IGP02E1000_PHY_POWER_MGMT,
600 struct e1000_hw *hw = &adapter->hw;
607 icr = E1000_READ_REG ( hw, ICR );
612 rctl = E1000_READ_REG ( hw, RCTL );
613 E1000_WRITE_REG ( hw, RCTL, rctl & ~E1000_RCTL_EN );
614 E1000_WRITE_FLUSH ( hw );
616 e1000_reset_hw ( hw );
634 struct e1000_hw *hw = &adapter->hw;
676 E1000_WRITE_REG ( hw, TDT, adapter->tx_tail );
690 struct e1000_hw *hw = &adapter->hw;
704 icr = E1000_READ_REG ( hw, ICR );
763 DBG ( "RCTL = %#08x\n", E1000_READ_REG ( &adapter->hw, RCTL ) );
853 adapter->hw.io_base = pdev->ioaddr;
858 adapter->hw.back = adapter;
874 adapter->hw.hw_addr = ioremap ( mmio_start, mmio_len );
875 DBG ( "adapter->hw.hw_addr: %p\n", adapter->hw.hw_addr );
877 if ( ! adapter->hw.hw_addr )
884 DBG ( "adapter->hw.mac_type: %#08x\n", adapter->hw.mac_type );
889 if ( ( adapter->hw.mac_type == e1000_ich8lan ) && ( pdev->ioaddr ) ) {
892 adapter->hw.flash_address = ioremap ( flash_start, flash_len );
893 if ( ! adapter->hw.flash_address )
898 if ( e1000_init_eeprom_params ( &adapter->hw ) ) {
906 err = e1000_reset_hw ( &adapter->hw );
913 if ( e1000_validate_eeprom_checksum( &adapter->hw ) < 0 ) {
919 if ( e1000_read_mac_addr ( &adapter->hw ) )
922 memcpy ( netdev->hw_addr, adapter->hw.mac_addr, ETH_ALEN );
926 struct e1000_hw *hw = &adapter->hw;
928 ((hw->bus_type == e1000_bus_type_pcix) ? "-X" :
929 (hw->bus_type == e1000_bus_type_pci_express ? " Express":"")),
930 ((hw->bus_speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
931 (hw->bus_speed == e1000_bus_speed_133) ? "133MHz" :
932 (hw->bus_speed == e1000_bus_speed_120) ? "120MHz" :
933 (hw->bus_speed == e1000_bus_speed_100) ? "100MHz" :
934 (hw->bus_speed == e1000_bus_speed_66) ? "66MHz" : "33MHz"),
935 ((hw->bus_width == e1000_bus_width_64) ? "64-bit" :
936 (hw->bus_width == e1000_bus_width_pciex_4) ? "Width x4" :
937 (hw->bus_width == e1000_bus_width_pciex_1) ? "Width x1" :
963 if ( ! e1000_check_phy_reset_block ( &adapter->hw ) )
964 e1000_phy_hw_reset ( &adapter->hw );
965 if ( adapter->hw.flash_address )
966 iounmap ( adapter->hw.flash_address );
969 iounmap ( adapter->hw.hw_addr );
990 if ( adapter->hw.flash_address )
991 iounmap ( adapter->hw.flash_address );
992 if ( adapter->hw.hw_addr )
993 iounmap ( adapter->hw.hw_addr );
996 e1000_reset_hw ( &adapter->hw );
1034 DBG ( "RXDCTL: %#08x\n", E1000_READ_REG ( &adapter->hw, RXDCTL ) );
1056 e1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
1058 struct e1000_adapter *adapter = hw->back;
1072 e1000_pci_clear_mwi ( struct e1000_hw *hw )
1074 struct e1000_adapter *adapter = hw->back;
1077 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE );
1081 e1000_pci_set_mwi ( struct e1000_hw *hw )
1083 struct e1000_adapter *adapter = hw->back;
1085 pci_write_config_word ( adapter->pdev, PCI_COMMAND, hw->pci_cmd_word );
1089 e1000_read_pci_cfg ( struct e1000_hw *hw, uint32_t reg, uint16_t *value )
1091 struct e1000_adapter *adapter = hw->back;
1097 e1000_write_pci_cfg ( struct e1000_hw *hw, uint32_t reg, uint16_t *value )
1099 struct e1000_adapter *adapter = hw->back;
1105 e1000_io_write ( struct e1000_hw *hw __unused, unsigned long port, uint32_t value )
