Lines Matching refs:hw
38 static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
39 static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
40 static int32_t e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data);
41 static int32_t e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data);
42 static int32_t e1000_get_software_semaphore(struct e1000_hw *hw);
43 static void e1000_release_software_semaphore(struct e1000_hw *hw);
45 static uint8_t e1000_arc_subsystem_valid(struct e1000_hw *hw);
46 static int32_t e1000_check_downshift(struct e1000_hw *hw);
47 static int32_t e1000_check_polarity(struct e1000_hw *hw, e1000_rev_polarity *polarity);
48 static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
49 static void e1000_clear_vfta(struct e1000_hw *hw);
50 static int32_t e1000_commit_shadow_ram(struct e1000_hw *hw);
51 static int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw, boolean_t link_up);
52 static int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw);
53 static int32_t e1000_detect_gig_phy(struct e1000_hw *hw);
54 static int32_t e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank);
55 static int32_t e1000_get_auto_rd_done(struct e1000_hw *hw);
56 static int32_t e1000_get_cable_length(struct e1000_hw *hw, uint16_t *min_length, uint16_t *max_length);
57 static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
58 static int32_t e1000_get_phy_cfg_done(struct e1000_hw *hw);
59 static int32_t e1000_get_software_flag(struct e1000_hw *hw);
60 static int32_t e1000_ich8_cycle_init(struct e1000_hw *hw);
61 static int32_t e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout);
62 static int32_t e1000_id_led_init(struct e1000_hw *hw);
63 static int32_t e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, uint32_t cnf_base_addr, uint32_t cnf_size);
64 static int32_t e1000_init_lcd_from_nvm(struct e1000_hw *hw);
65 static void e1000_init_rx_addrs(struct e1000_hw *hw);
66 static void e1000_initialize_hardware_bits(struct e1000_hw *hw);
67 static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw);
68 static int32_t e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw);
69 static int32_t e1000_mng_enable_host_if(struct e1000_hw *hw);
70 static int32_t e1000_mng_host_if_write(struct e1000_hw *hw, uint8_t *buffer, uint16_t length, uint16_t offset, uint8_t *sum);
71 static int32_t e1000_mng_write_cmd_header(struct e1000_hw* hw, struct e1000_host_mng_command_header* hdr);
72 static int32_t e1000_mng_write_commit(struct e1000_hw *hw);
73 static int32_t e1000_phy_ife_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
74 static int32_t e1000_phy_igp_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
75 static int32_t e1000_read_eeprom_eerd(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
76 static int32_t e1000_write_eeprom_eewr(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
77 static int32_t e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd);
78 static int32_t e1000_phy_m88_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
79 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
80 static int32_t e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t *data);
81 static int32_t e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte);
82 static int32_t e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte);
83 static int32_t e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data);
84 static int32_t e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t *data);
85 static int32_t e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t data);
86 static int32_t e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
87 static int32_t e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
88 static void e1000_release_software_flag(struct e1000_hw *hw);
89 static int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active);
90 static int32_t e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active);
91 static int32_t e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop);
92 static void e1000_set_pci_express_master_disable(struct e1000_hw *hw);
93 static int32_t e1000_wait_autoneg(struct e1000_hw *hw);
94 static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value);
95 static int32_t e1000_set_phy_type(struct e1000_hw *hw);
96 static void e1000_phy_init_script(struct e1000_hw *hw);
97 static int32_t e1000_setup_copper_link(struct e1000_hw *hw);
98 static int32_t e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
99 static int32_t e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
100 static int32_t e1000_phy_force_speed_duplex(struct e1000_hw *hw);
101 static int32_t e1000_config_mac_to_phy(struct e1000_hw *hw);
102 static void e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
103 static void e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
104 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data,
106 static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw);
107 static int32_t e1000_phy_reset_dsp(struct e1000_hw *hw);
108 static int32_t e1000_write_eeprom_spi(struct e1000_hw *hw, uint16_t offset,
110 static int32_t e1000_write_eeprom_microwire(struct e1000_hw *hw,
113 static int32_t e1000_spi_eeprom_ready(struct e1000_hw *hw);
114 static void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
115 static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
116 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data,
118 static int32_t e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
120 static int32_t e1000_read_phy_reg_ex(struct e1000_hw *hw,uint32_t reg_addr,
122 static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count);
123 static int32_t e1000_acquire_eeprom(struct e1000_hw *hw);
124 static void e1000_release_eeprom(struct e1000_hw *hw);
125 static void e1000_standby_eeprom(struct e1000_hw *hw);
126 static int32_t e1000_set_vco_speed(struct e1000_hw *hw);
127 static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw);
128 static int32_t e1000_set_phy_mode(struct e1000_hw *hw);
129 static int32_t e1000_host_if_read_cookie(struct e1000_hw *hw, uint8_t *buffer);
131 static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw,
133 static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw);
159 * Set the phy type member in the hw struct.
161 * hw - Struct containing variables accessed by shared code
164 e1000_set_phy_type(struct e1000_hw *hw)
168 if (hw->mac_type == e1000_undefined)
171 switch (hw->phy_id) {
176 hw->phy_type = e1000_phy_m88;
179 if (hw->mac_type == e1000_82541 ||
180 hw->mac_type == e1000_82541_rev_2 ||
181 hw->mac_type == e1000_82547 ||
182 hw->mac_type == e1000_82547_rev_2) {
183 hw->phy_type = e1000_phy_igp;
187 hw->phy_type = e1000_phy_igp_3;
192 hw->phy_type = e1000_phy_ife;
195 if (hw->mac_type == e1000_80003es2lan) {
196 hw->phy_type = e1000_phy_gg82563;
202 hw->phy_type = e1000_phy_undefined;
212 * hw - Struct containing variables accessed by shared code
215 e1000_phy_init_script(struct e1000_hw *hw)
222 if (hw->phy_init_script) {
227 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
230 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
234 e1000_write_phy_reg(hw,0x0000,0x0140);
238 switch (hw->mac_type) {
241 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
243 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
245 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
247 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
249 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
251 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
253 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
255 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
257 e1000_write_phy_reg(hw, 0x2010, 0x0008);
262 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
268 e1000_write_phy_reg(hw, 0x0000, 0x3300);
273 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
275 if (hw->mac_type == e1000_82547) {
279 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
282 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
297 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
298 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
306 * Set the mac type member in the hw struct.
308 * hw - Struct containing variables accessed by shared code
311 e1000_set_mac_type(struct e1000_hw *hw)
315 switch (hw->device_id) {
317 switch (hw->revision_id) {
319 hw->mac_type = e1000_82542_rev2_0;
322 hw->mac_type = e1000_82542_rev2_1;
331 hw->mac_type = e1000_82543;
337 hw->mac_type = e1000_82544;
344 hw->mac_type = e1000_82540;
348 hw->mac_type = e1000_82545;
353 hw->mac_type = e1000_82545_rev_3;
358 hw->mac_type = e1000_82546;
366 hw->mac_type = e1000_82546_rev_3;
371 hw->mac_type = e1000_82541;
377 hw->mac_type = e1000_82541_rev_2;
381 hw->mac_type = e1000_82547;
384 hw->mac_type = e1000_82547_rev_2;
394 hw->mac_type = e1000_82571;
400 hw->mac_type = e1000_82572;
405 hw->mac_type = e1000_82573;
411 hw->mac_type = e1000_80003es2lan;
420 hw->mac_type = e1000_ich8lan;
423 hw->mac_type = e1000_82576;
430 switch (hw->mac_type) {
433 hw->swfwhw_semaphore_present = TRUE;
434 hw->asf_firmware_present = TRUE;
437 hw->swfw_sync_present = TRUE;
442 hw->eeprom_semaphore_present = TRUE;
448 hw->asf_firmware_present = TRUE;
457 if (hw->mac_type == e1000_82543)
458 hw->bad_tx_carr_stats_fd = TRUE;
461 if (hw->mac_type >= e1000_82571)
462 hw->has_manc2h = TRUE;
467 if (hw->mac_type == e1000_80003es2lan)
468 hw->rx_needs_kicking = TRUE;
470 if (hw->mac_type > e1000_82544)
471 hw->has_smbus = TRUE;
479 * hw - Struct containing variables accessed by shared code
482 e1000_set_media_type(struct e1000_hw *hw)
488 if (hw->mac_type != e1000_82543) {
490 hw->tbi_compatibility_en = FALSE;
493 switch (hw->device_id) {
501 hw->media_type = e1000_media_type_internal_serdes;
504 switch (hw->mac_type) {
507 hw->media_type = e1000_media_type_fiber;
515 hw->media_type = e1000_media_type_copper;
518 status = E1000_READ_REG(hw, STATUS);
520 hw->media_type = e1000_media_type_fiber;
522 hw->tbi_compatibility_en = FALSE;
524 hw->media_type = e1000_media_type_copper;
534 * hw - Struct containing variables accessed by shared code
537 e1000_reset_hw(struct e1000_hw *hw)
551 if (hw->mac_type == e1000_82542_rev2_0) {
553 e1000_pci_clear_mwi(hw);
556 if (hw->bus_type == e1000_bus_type_pci_express) {
560 if (e1000_disable_pciex_master(hw) != E1000_SUCCESS) {
567 E1000_WRITE_REG(hw, IMC, 0xffffffff);
573 E1000_WRITE_REG(hw, RCTL, 0);
574 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
575 E1000_WRITE_FLUSH(hw);
578 hw->tbi_compatibility_on = FALSE;
585 ctrl = E1000_READ_REG(hw, CTRL);
588 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
589 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
595 if (hw->mac_type == e1000_82573) {
598 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
602 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
603 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
616 if (hw->mac_type == e1000_ich8lan) {
618 E1000_WRITE_REG(hw, PBA, E1000_PBA_8K);
620 E1000_WRITE_REG(hw, PBS, E1000_PBS_16K);
630 switch (hw->mac_type) {
639 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
644 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
647 if (!hw->phy_reset_disable &&
648 e1000_check_phy_reset_block(hw) == E1000_SUCCESS) {
649 /* e1000_ich8lan PHY HW reset requires MAC CORE reset
656 e1000_get_software_flag(hw);
657 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
661 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
669 switch (hw->mac_type) {
676 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
678 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
679 E1000_WRITE_FLUSH(hw);
691 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
693 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
695 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
696 E1000_WRITE_FLUSH(hw);
701 ret_val = e1000_get_auto_rd_done(hw);
707 /* Disable HW ARPs on ASF enabled adapters */
708 if (hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) {
709 manc = E1000_READ_REG(hw, MANC);
711 E1000_WRITE_REG(hw, MANC, manc);
714 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
715 e1000_phy_init_script(hw);
718 led_ctrl = E1000_READ_REG(hw, LEDCTL);
721 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
726 E1000_WRITE_REG(hw, IMC, 0xffffffff);
729 icr = E1000_READ_REG(hw, ICR);
731 if (hw->mac_type == e1000_82571 && hw->laa_is_present == TRUE) {
739 e1000_rar_set(hw, hw->mac_addr, E1000_RAR_ENTRIES - 1);
743 if (hw->mac_type == e1000_82542_rev2_0) {
744 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
745 e1000_pci_set_mwi(hw);
748 if (hw->mac_type == e1000_ich8lan) {
749 uint32_t kab = E1000_READ_REG(hw, KABGTXD);
751 E1000_WRITE_REG(hw, KABGTXD, kab);
761 * hw: Struct containing variables accessed by shared code
767 e1000_initialize_hardware_bits(struct e1000_hw *hw)
769 if ((hw->mac_type >= e1000_82571 && hw->mac_type < e1000_82576) &&
770 (!hw->initialize_hw_bits_disable)) {
778 reg_tarc0 = E1000_READ_REG(hw, TARC0);
782 reg_txdctl = E1000_READ_REG(hw, TXDCTL);
784 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
785 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
787 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
789 switch (hw->mac_type) {
793 reg_tarc1 = E1000_READ_REG(hw, TARC1);
803 reg_tctl = E1000_READ_REG(hw, TCTL);
809 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
812 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
817 reg_ctrl = E1000_READ_REG(hw, CTRL);
820 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
821 E1000_WRITE_REG(hw, CTRL, reg_ctrl);
825 if ((hw->media_type == e1000_media_type_fiber) ||
826 (hw->media_type == e1000_media_type_internal_serdes)) {
831 reg_tctl = E1000_READ_REG(hw, TCTL);
832 reg_tarc1 = E1000_READ_REG(hw, TARC1);
838 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
842 if ((hw->revision_id < 3) ||
843 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
844 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
847 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
849 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
855 reg_tctl = E1000_READ_REG(hw, TCTL);
856 reg_tarc1 = E1000_READ_REG(hw, TARC1);
865 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
871 E1000_WRITE_REG(hw, TARC0, reg_tarc0);
878 * hw - Struct containing variables accessed by shared code
887 e1000_init_hw(struct e1000_hw *hw)
903 if ((hw->mac_type == e1000_ich8lan) &&
904 ((hw->revision_id < 3) ||
905 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
906 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
907 reg_data = E1000_READ_REG(hw, STATUS);
909 E1000_WRITE_REG(hw, STATUS, reg_data);
913 ret_val = e1000_id_led_init(hw);
920 e1000_set_media_type(hw);
923 e1000_initialize_hardware_bits(hw);
927 switch (hw->mac_type) {
941 E1000_WRITE_REG(hw, VET, ETHERNET_IEEE_VLAN_TYPE);
944 if (hw->mac_type < e1000_82545_rev_3)
945 E1000_WRITE_REG(hw, VET, 0);
946 e1000_clear_vfta(hw);
951 if (hw->mac_type == e1000_82542_rev2_0) {
953 e1000_pci_clear_mwi(hw);
954 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
955 E1000_WRITE_FLUSH(hw);
962 e1000_init_rx_addrs(hw);
965 if (hw->mac_type == e1000_82542_rev2_0) {
966 E1000_WRITE_REG(hw, RCTL, 0);
967 E1000_WRITE_FLUSH(hw);
969 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
970 e1000_pci_set_mwi(hw);
976 if (hw->mac_type == e1000_ich8lan)
979 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
982 E1000_WRITE_FLUSH(hw);
990 if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
991 ctrl = E1000_READ_REG(hw, CTRL);
992 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
995 switch (hw->mac_type) {
1001 if (hw->bus_type == e1000_bus_type_pcix) {
1002 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
1003 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI,
1014 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER,
1022 if (hw->mac_type == e1000_ich8lan)
1026 ret_val = e1000_setup_link(hw);
1029 if (hw->mac_type > e1000_82544) {
1030 ctrl = E1000_READ_REG(hw, TXDCTL);
1032 E1000_WRITE_REG(hw, TXDCTL, ctrl);
1035 if (hw->mac_type == e1000_82573) {
1036 e1000_enable_tx_pkt_filtering(hw);
1039 switch (hw->mac_type) {
1044 reg_data = E1000_READ_REG(hw, TCTL);
1046 E1000_WRITE_REG(hw, TCTL, reg_data);
1049 reg_data = E1000_READ_REG(hw, TCTL_EXT);
1052 E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
1055 reg_data = E1000_READ_REG(hw, TIPG);
1058 E1000_WRITE_REG(hw, TIPG, reg_data);
1060 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
1062 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
1067 ctrl = E1000_READ_REG(hw, TXDCTL1);
1069 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
1074 if (hw->mac_type == e1000_82573) {
1075 uint32_t gcr = E1000_READ_REG(hw, GCR);
1077 E1000_WRITE_REG(hw, GCR, gcr);
1085 e1000_clear_hw_cntrs(hw);
1089 if (hw->mac_type == e1000_ich8lan)
1090 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
1092 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
1093 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
1094 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1098 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1107 * hw - Struct containing variables accessed by shared code.
1110 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
1117 if (hw->media_type != e1000_media_type_internal_serdes)
1120 switch (hw->mac_type) {
1128 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data);
1136 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
1147 * hw - Struct containing variables accessed by shared code
1156 e1000_setup_link(struct e1000_hw *hw)
1166 if (e1000_check_phy_reset_block(hw))
1171 * a bit that determines whether the HW defaults to enabling or
1174 * control setting, then the variable hw->fc will
1177 if (hw->fc == E1000_FC_DEFAULT) {
1178 switch (hw->mac_type) {
1181 hw->fc = E1000_FC_FULL;
1184 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
1191 hw->fc = E1000_FC_NONE;
1194 hw->fc = E1000_FC_TX_PAUSE;
1196 hw->fc = E1000_FC_FULL;
1205 if (hw->mac_type == e1000_82542_rev2_0)
1206 hw->fc &= (~E1000_FC_TX_PAUSE);
1208 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
1209 hw->fc &= (~E1000_FC_RX_PAUSE);
1211 hw->original_fc = hw->fc;
1213 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
1222 if (hw->mac_type == e1000_82543) {
1223 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
1231 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1235 ret_val = (hw->media_type == e1000_media_type_copper) ?
1236 e1000_setup_copper_link(hw) :
1237 e1000_setup_fiber_serdes_link(hw);
1247 if (hw->mac_type != e1000_ich8lan) {
1248 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1249 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1250 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1253 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
1261 if (!(hw->fc & E1000_FC_TX_PAUSE)) {
1262 E1000_WRITE_REG(hw, FCRTL, 0);
1263 E1000_WRITE_REG(hw, FCRTH, 0);
1268 if (hw->fc_send_xon) {
1269 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
1270 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1272 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
1273 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1282 * hw - Struct containing variables accessed by shared code
1289 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1305 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572)
1306 E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK);
1314 ctrl = E1000_READ_REG(hw, CTRL);
1315 if (hw->media_type == e1000_media_type_fiber)
1316 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
1318 ret_val = e1000_adjust_serdes_amplitude(hw);
1326 ret_val = e1000_set_vco_speed(hw);
1330 e1000_config_collision_dist(hw);
1347 switch (hw->fc) {
1385 E1000_WRITE_REG(hw, TXCW, txcw);
1386 E1000_WRITE_REG(hw, CTRL, ctrl);
1387 E1000_WRITE_FLUSH(hw);
1389 hw->txcw = txcw;
1398 if (hw->media_type == e1000_media_type_internal_serdes ||
1399 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
1403 status = E1000_READ_REG(hw, STATUS);
1408 hw->autoneg_failed = 1;
1414 ret_val = e1000_check_for_link(hw);
1419 hw->autoneg_failed = 0;
1421 hw->autoneg_failed = 0;
1433 * hw - Struct containing variables accessed by shared code
1436 e1000_copper_link_preconfig(struct e1000_hw *hw)
1444 ctrl = E1000_READ_REG(hw, CTRL);
1449 if (hw->mac_type > e1000_82543) {
1452 E1000_WRITE_REG(hw, CTRL, ctrl);
1455 E1000_WRITE_REG(hw, CTRL, ctrl);
1456 ret_val = e1000_phy_hw_reset(hw);
1462 ret_val = e1000_detect_gig_phy(hw);
1467 DEBUGOUT1("Phy ID = %#08x \n", hw->phy_id);
1470 ret_val = e1000_set_phy_mode(hw);
1474 if ((hw->mac_type == e1000_82545_rev_3) ||
1475 (hw->mac_type == e1000_82546_rev_3)) {
1476 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1478 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1481 if (hw->mac_type <= e1000_82543 ||
1482 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1483 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
1484 hw->phy_reset_disable = FALSE;
1493 * hw - Struct containing variables accessed by shared code
1496 e1000_copper_link_igp_setup(struct e1000_hw *hw)
1504 if (hw->phy_reset_disable)
1507 ret_val = e1000_phy_reset(hw);
1519 if (hw->mac_type != e1000_ich8lan && hw->mac_type != e1000_82576) {
1521 led_ctrl = E1000_READ_REG(hw, LEDCTL);
1524 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
1528 if (hw->phy_type == e1000_phy_igp) {
1530 ret_val = e1000_set_d3_lplu_state(hw, FALSE);
1538 ret_val = e1000_set_d0_lplu_state(hw, FALSE);
1544 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1548 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1549 hw->dsp_config_state = e1000_dsp_config_disabled;
1552 hw->mdix = 1;
1555 hw->dsp_config_state = e1000_dsp_config_enabled;
1558 switch (hw->mdix) {
1571 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1576 if (hw->autoneg) {
1577 e1000_ms_type phy_ms_setting = hw->master_slave;
1579 if (hw->ffe_config_state == e1000_ffe_config_active)
1580 hw->ffe_config_state = e1000_ffe_config_enabled;
1582 if (hw->dsp_config_state == e1000_dsp_config_activated)
1583 hw->dsp_config_state = e1000_dsp_config_enabled;
1588 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1590 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1595 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1600 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1604 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1609 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1614 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1633 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1644 * hw - Struct containing variables accessed by shared code
1647 e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1655 if (!hw->phy_reset_disable) {
1658 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1667 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1679 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data);
1685 switch (hw->mdix) {
1705 if (hw->disable_polarity_correction == 1)
1707 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
1713 ret_val = e1000_phy_reset(hw);
1720 if (hw->mac_type == e1000_80003es2lan) {
1722 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
1728 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data);
1733 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data);
1738 reg_data = E1000_READ_REG(hw, CTRL_EXT);
1740 E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
1742 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1747 /* Do not init these registers when the HW is in IAMT mode, since the
1749 * them if the HW is not in IAMT mode.
1751 if (e1000_check_mng_mode(hw) == FALSE) {
1754 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1759 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1765 hw, GG82563_PHY_KMRN_MODE_CTRL,
1775 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
1780 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
1792 * hw - Struct containing variables accessed by shared code
1795 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1802 if (hw->phy_reset_disable)
1806 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1821 switch (hw->mdix) {
1844 if (hw->disable_polarity_correction == 1)
1846 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1850 if (hw->phy_revision < M88E1011_I_REV_4) {
1854 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1860 if ((hw->phy_revision == E1000_REVISION_2) &&
1861 (hw->phy_id == M88E1111_I_PHY_ID)) {
1865 ret_val = e1000_write_phy_reg(hw,
1875 ret_val = e1000_write_phy_reg(hw,
1883 ret_val = e1000_phy_reset(hw);
1896 * hw - Struct containing variables accessed by shared code
1899 e1000_copper_link_autoneg(struct e1000_hw *hw)
1906 /* Perform some bounds checking on the hw->autoneg_advertised
1909 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1914 if (hw->autoneg_advertised == 0)
1915 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1918 if (hw->phy_type == e1000_phy_ife)
1919 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
1922 ret_val = e1000_phy_setup_autoneg(hw);
1932 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1937 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
1944 if (hw->wait_autoneg_complete) {
1945 ret_val = e1000_wait_autoneg(hw);
1952 hw->get_link_status = TRUE;
1967 * hw - Struct containing variables accessed by shared code
1970 e1000_copper_link_postconfig(struct e1000_hw *hw)
1975 if (hw->mac_type >= e1000_82544) {
1976 e1000_config_collision_dist(hw);
1978 ret_val = e1000_config_mac_to_phy(hw);
1984 ret_val = e1000_config_fc_after_link_up(hw);
1991 if (hw->phy_type == e1000_phy_igp) {
1992 ret_val = e1000_config_dsp_after_link_change(hw, TRUE);
2005 * hw - Struct containing variables accessed by shared code
2008 e1000_setup_copper_link(struct e1000_hw *hw)
2017 switch (hw->mac_type) {
2023 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
2026 ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data);
2030 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
2038 ret_val = e1000_copper_link_preconfig(hw);
2042 switch (hw->mac_type) {
2047 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL,
2056 if (hw->phy_type == e1000_phy_igp ||
2057 hw->phy_type == e1000_phy_igp_3 ||
2058 hw->phy_type == e1000_phy_igp_2) {
2059 ret_val = e1000_copper_link_igp_setup(hw);
2062 } else if (hw->phy_type == e1000_phy_m88) {
2063 ret_val = e1000_copper_link_mgp_setup(hw);
2066 } else if (hw->phy_type == e1000_phy_gg82563) {
2067 ret_val = e1000_copper_link_ggp_setup(hw);
2072 if (hw->autoneg) {
2075 ret_val = e1000_copper_link_autoneg(hw);
2082 ret_val = e1000_phy_force_speed_duplex(hw);
2093 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2096 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2102 ret_val = e1000_copper_link_postconfig(hw);
2119 * hw - Struct containing variables accessed by shared code
2122 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
2131 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
2137 tipg = E1000_READ_REG(hw, TIPG);
2140 E1000_WRITE_REG(hw, TIPG, tipg);
2142 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
2152 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
2158 e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
2167 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
2173 tipg = E1000_READ_REG(hw, TIPG);
2176 E1000_WRITE_REG(hw, TIPG, tipg);
2178 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
2184 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
2192 * hw - Struct containing variables accessed by shared code
2195 e1000_phy_setup_autoneg(struct e1000_hw *hw)
2204 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
2208 if (hw->phy_type != e1000_phy_ife) {
2210 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
2230 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
2233 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
2239 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
2245 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
2251 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
2257 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
2262 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
2265 hw->phy_type == e1000_phy_ife) {
2286 switch (hw->fc) {
2301 *hw's ability to send PAUSE frames.
2323 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
2329 if (hw->phy_type != e1000_phy_ife) {
2330 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
2339 * Force PHY speed and duplex settings to hw->forced_speed_duplex
2341 * hw - Struct containing variables accessed by shared code
2344 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2356 hw->fc = E1000_FC_NONE;
2358 DEBUGOUT1("hw->fc = %d\n", hw->fc);
2361 ctrl = E1000_READ_REG(hw, CTRL);
2371 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
2380 if (hw->forced_speed_duplex == e1000_100_full ||
2381 hw->forced_speed_duplex == e1000_10_full) {
2398 if (hw->forced_speed_duplex == e1000_100_full ||
2399 hw->forced_speed_duplex == e1000_100_half) {
2413 e1000_config_collision_dist(hw);
2416 E1000_WRITE_REG(hw, CTRL, ctrl);
2418 if ((hw->phy_type == e1000_phy_m88) ||
2419 (hw->phy_type == e1000_phy_gg82563)) {
2420 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2428 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2438 } else if (hw->phy_type == e1000_phy_ife) {
2439 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
2446 ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data);
2454 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2461 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2467 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
2480 if (hw->wait_autoneg_complete) {
2490 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2494 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2502 ((hw->phy_type == e1000_phy_m88) ||
2503 (hw->phy_type == e1000_phy_gg82563))) {
2505 ret_val = e1000_phy_reset_dsp(hw);
2518 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2522 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2528 if (hw->phy_type == e1000_phy_m88) {
2533 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
2538 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2545 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2550 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2554 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2555 (!hw->autoneg) && (hw->forced_speed_duplex == e1000_10_full ||
2556 hw->forced_speed_duplex == e1000_10_half)) {
2557 ret_val = e1000_polarity_reversal_workaround(hw);
2561 } else if (hw->phy_type == e1000_phy_gg82563) {
2565 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2570 if ((hw->forced_speed_duplex == e1000_10_full) ||
2571 (hw->forced_speed_duplex == e1000_10_half))
2579 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2589 * hw - Struct containing variables accessed by shared code
2595 e1000_config_collision_dist(struct e1000_hw *hw)
2601 if (hw->mac_type < e1000_82543)
2606 tctl = E1000_READ_REG(hw, TCTL);
2611 E1000_WRITE_REG(hw, TCTL, tctl);
2612 E1000_WRITE_FLUSH(hw);
2618 * hw - Struct containing variables accessed by shared code
2625 e1000_config_mac_to_phy(struct e1000_hw *hw)
2635 if (hw->mac_type >= e1000_82544)
2641 ctrl = E1000_READ_REG(hw, CTRL);
2648 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2657 e1000_config_collision_dist(hw);
2668 E1000_WRITE_REG(hw, CTRL, ctrl);
2675 * hw - Struct containing variables accessed by shared code
2684 e1000_force_mac_fc(struct e1000_hw *hw)
2691 ctrl = E1000_READ_REG(hw, CTRL);
2699 * according to the "hw->fc" parameter.
2711 switch (hw->fc) {
2732 if (hw->mac_type == e1000_82542_rev2_0)
2735 E1000_WRITE_REG(hw, CTRL, ctrl);
2742 * hw - Struct containing variables accessed by shared code
2751 e1000_config_fc_after_link_up(struct e1000_hw *hw)
2766 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
2767 ((hw->media_type == e1000_media_type_internal_serdes) &&
2768 (hw->autoneg_failed)) ||
2769 ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) {
2770 ret_val = e1000_force_mac_fc(hw);
2782 if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
2787 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2790 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2801 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
2805 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2852 if (hw->original_fc == E1000_FC_FULL) {
2853 hw->fc = E1000_FC_FULL;
2856 hw->fc = E1000_FC_RX_PAUSE;
2872 hw->fc = E1000_FC_TX_PAUSE;
2887 hw->fc = E1000_FC_RX_PAUSE;
2910 else if ((hw->original_fc == E1000_FC_NONE ||
2911 hw->original_fc == E1000_FC_TX_PAUSE) ||
2912 hw->fc_strict_ieee) {
2913 hw->fc = E1000_FC_NONE;
2916 hw->fc = E1000_FC_RX_PAUSE;
2924 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
2931 hw->fc = E1000_FC_NONE;
2936 ret_val = e1000_force_mac_fc(hw);
2951 * hw - Struct containing variables accessed by shared code
2956 e1000_check_for_link(struct e1000_hw *hw)
2969 ctrl = E1000_READ_REG(hw, CTRL);
2970 status = E1000_READ_REG(hw, STATUS);
2976 if ((hw->media_type == e1000_media_type_fiber) ||
2977 (hw->media_type == e1000_media_type_internal_serdes)) {
2978 rxcw = E1000_READ_REG(hw, RXCW);
2980 if (hw->media_type == e1000_media_type_fiber) {
2981 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
2983 hw->get_link_status = FALSE;
2993 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
2999 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3002 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3007 hw->get_link_status = FALSE;
3010 e1000_check_downshift(hw);
3020 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
3021 (!hw->autoneg) &&
3022 (hw->forced_speed_duplex == e1000_10_full ||
3023 hw->forced_speed_duplex == e1000_10_half)) {
3024 E1000_WRITE_REG(hw, IMC, 0xffffffff);
3025 ret_val = e1000_polarity_reversal_workaround(hw);
3026 icr = E1000_READ_REG(hw, ICR);
3027 E1000_WRITE_REG(hw, ICS, (icr & ~E1000_ICS_LSC));
3028 E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK);
3033 e1000_config_dsp_after_link_change(hw, FALSE);
3040 if (!hw->autoneg) return -E1000_ERR_CONFIG;
3043 e1000_config_dsp_after_link_change(hw, TRUE);
3053 if (hw->mac_type >= e1000_82544)
3054 e1000_config_collision_dist(hw);
3056 ret_val = e1000_config_mac_to_phy(hw);
3067 ret_val = e1000_config_fc_after_link_up(hw);
3080 if (hw->tbi_compatibility_en) {
3082 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
3091 if (hw->tbi_compatibility_on) {
3093 rctl = E1000_READ_REG(hw, RCTL);
3095 E1000_WRITE_REG(hw, RCTL, rctl);
3096 hw->tbi_compatibility_on = FALSE;
3104 if (!hw->tbi_compatibility_on) {
3105 hw->tbi_compatibility_on = TRUE;
3106 rctl = E1000_READ_REG(hw, RCTL);
3108 E1000_WRITE_REG(hw, RCTL, rctl);
3120 else if ((((hw->media_type == e1000_media_type_fiber) &&
3122 (hw->media_type == e1000_media_type_internal_serdes)) &&
3125 if (hw->autoneg_failed == 0) {
3126 hw->autoneg_failed = 1;
3132 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
3135 ctrl = E1000_READ_REG(hw, CTRL);
3137 E1000_WRITE_REG(hw, CTRL, ctrl);
3140 ret_val = e1000_config_fc_after_link_up(hw);
3151 else if (((hw->media_type == e1000_media_type_fiber) ||
3152 (hw->media_type == e1000_media_type_internal_serdes)) &&
3155 E1000_WRITE_REG(hw, TXCW, hw->txcw);
3156 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
3158 hw->serdes_link_down = FALSE;
3163 else if ((hw->media_type == e1000_media_type_internal_serdes) &&
3164 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
3167 if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
3169 hw->serdes_link_down = FALSE;
3173 hw->serdes_link_down = TRUE;
3177 if ((hw->media_type == e1000_media_type_internal_serdes) &&
3178 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
3179 hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS));
3187 * hw - Struct containing variables accessed by shared code
3192 e1000_get_speed_and_duplex(struct e1000_hw *hw,
3202 if (hw->mac_type >= e1000_82543) {
3203 status = E1000_READ_REG(hw, STATUS);
3232 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
3233 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
3240 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
3249 if ((hw->mac_type == e1000_80003es2lan) &&
3250 (hw->media_type == e1000_media_type_copper)) {
3252 ret_val = e1000_configure_kmrn_for_1000(hw);
3254 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
3259 if ((hw->phy_type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
3260 ret_val = e1000_kumeran_lock_loss_workaround(hw);
3271 * hw - Struct containing variables accessed by shared code
3274 e1000_wait_autoneg(struct e1000_hw *hw)
3288 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3291 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3305 * hw - Struct containing variables accessed by shared code
3309 e1000_raise_mdi_clk(struct e1000_hw *hw,
3315 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
3316 E1000_WRITE_FLUSH(hw);
3323 * hw - Struct containing variables accessed by shared code
3327 e1000_lower_mdi_clk(struct e1000_hw *hw,
3333 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
3334 E1000_WRITE_FLUSH(hw);
3341 * hw - Struct containing variables accessed by shared code
3348 e1000_shift_out_mdi_bits(struct e1000_hw *hw,
3362 ctrl = E1000_READ_REG(hw, CTRL);
3378 E1000_WRITE_REG(hw, CTRL, ctrl);
3379 E1000_WRITE_FLUSH(hw);
3383 e1000_raise_mdi_clk(hw, &ctrl);
3384 e1000_lower_mdi_clk(hw, &ctrl);
3393 * hw - Struct containing variables accessed by shared code
3398 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
3411 ctrl = E1000_READ_REG(hw, CTRL);
3417 E1000_WRITE_REG(hw, CTRL, ctrl);
3418 E1000_WRITE_FLUSH(hw);
3424 e1000_raise_mdi_clk(hw, &ctrl);
3425 e1000_lower_mdi_clk(hw, &ctrl);
3429 e1000_raise_mdi_clk(hw, &ctrl);
3430 ctrl = E1000_READ_REG(hw, CTRL);
3434 e1000_lower_mdi_clk(hw, &ctrl);
3437 e1000_raise_mdi_clk(hw, &ctrl);
3438 e1000_lower_mdi_clk(hw, &ctrl);
3444 e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
3453 if (hw->swfwhw_semaphore_present)
3454 return e1000_get_software_flag(hw);
3456 if (!hw->swfw_sync_present)
3457 return e1000_get_hw_eeprom_semaphore(hw);
3460 if (e1000_get_hw_eeprom_semaphore(hw))
3463 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
3470 e1000_put_hw_eeprom_semaphore(hw);
3481 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
3483 e1000_put_hw_eeprom_semaphore(hw);
3488 e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
3495 if (hw->swfwhw_semaphore_present) {
3496 e1000_release_software_flag(hw);
3500 if (!hw->swfw_sync_present) {
3501 e1000_put_hw_eeprom_semaphore(hw);
3505 /* if (e1000_get_hw_eeprom_semaphore(hw))
3507 while (e1000_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS);
3510 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
3512 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
3514 e1000_put_hw_eeprom_semaphore(hw);
3520 * hw - Struct containing variables accessed by shared code
3524 e1000_read_phy_reg(struct e1000_hw *hw,
3533 if ((hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_82576) &&
3534 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3539 if (e1000_swfw_sync_acquire(hw, swfw))
3542 if ((hw->phy_type == e1000_phy_igp ||
3543 hw->phy_type == e1000_phy_igp_3 ||
3544 hw->phy_type == e1000_phy_igp_2) &&
3546 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3549 e1000_swfw_sync_release(hw, swfw);
3552 } else if (hw->phy_type == e1000_phy_gg82563) {
3554 (hw->mac_type == e1000_80003es2lan)) {
3557 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3563 ret_val = e1000_write_phy_reg_ex(hw,
3569 e1000_swfw_sync_release(hw, swfw);
3575 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
3578 e1000_swfw_sync_release(hw, swfw);
3583 e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
3597 if (hw->mac_type > e1000_82543) {
3606 E1000_WRITE_REG(hw, MDIC, mdic);
3611 mdic = E1000_READ_REG(hw, MDIC);
3628 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3644 e1000_shift_out_mdi_bits(hw, mdic, 14);
3650 *phy_data = e1000_shift_in_mdi_bits(hw);
3658 * hw - Struct containing variables accessed by shared code
3663 e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
3671 if ((hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_82576) &&
3672 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3677 if (e1000_swfw_sync_acquire(hw, swfw))
3680 if ((hw->phy_type == e1000_phy_igp ||
3681 hw->phy_type == e1000_phy_igp_3 ||
3682 hw->phy_type == e1000_phy_igp_2) &&
3684 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3687 e1000_swfw_sync_release(hw, swfw);
3690 } else if (hw->phy_type == e1000_phy_gg82563) {
3692 (hw->mac_type == e1000_80003es2lan)) {
3695 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3701 ret_val = e1000_write_phy_reg_ex(hw,
3707 e1000_swfw_sync_release(hw, swfw);
3713 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
3716 e1000_swfw_sync_release(hw, swfw);
3721 e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
3735 if (hw->mac_type > e1000_82543) {
3745 E1000_WRITE_REG(hw, MDIC, mdic);
3750 mdic = E1000_READ_REG(hw, MDIC);
3763 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3776 e1000_shift_out_mdi_bits(hw, mdic, 32);
3783 e1000_read_kmrn_reg(struct e1000_hw *hw,
3791 if ((hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_82576) &&
3792 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3797 if (e1000_swfw_sync_acquire(hw, swfw))
3804 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
3808 reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
3811 e1000_swfw_sync_release(hw, swfw);
3816 e1000_write_kmrn_reg(struct e1000_hw *hw,
3824 if ((hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_82576) &&
3825 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3830 if (e1000_swfw_sync_acquire(hw, swfw))
3835 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
3838 e1000_swfw_sync_release(hw, swfw);
3845 * hw - Struct containing variables accessed by shared code
3848 e1000_phy_hw_reset(struct e1000_hw *hw)
3859 ret_val = e1000_check_phy_reset_block(hw);
3865 if (hw->mac_type > e1000_82543) {
3866 if ((hw->mac_type == e1000_80003es2lan ||
3867 hw->mac_type == e1000_82576) &&
3868 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3873 if (e1000_swfw_sync_acquire(hw, swfw)) {
3883 ctrl = E1000_READ_REG(hw, CTRL);
3884 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
3885 E1000_WRITE_FLUSH(hw);
3887 if (hw->mac_type < e1000_82571)
3892 E1000_WRITE_REG(hw, CTRL, ctrl);
3893 E1000_WRITE_FLUSH(hw);
3895 if (hw->mac_type >= e1000_82571)
3898 e1000_swfw_sync_release(hw, swfw);
3903 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
3906 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3907 E1000_WRITE_FLUSH(hw);
3910 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3911 E1000_WRITE_FLUSH(hw);
3915 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
3917 led_ctrl = E1000_READ_REG(hw, LEDCTL);
3920 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
3924 ret_val = e1000_get_phy_cfg_done(hw);
3927 e1000_release_software_semaphore(hw);
3929 if ((hw->mac_type == e1000_ich8lan) && (hw->phy_type == e1000_phy_igp_3))
3930 ret_val = e1000_init_lcd_from_nvm(hw);
3938 * hw - Struct containing variables accessed by shared code
3943 e1000_phy_reset(struct e1000_hw *hw)
3952 ret_val = e1000_check_phy_reset_block(hw);
3956 switch (hw->phy_type) {
3961 ret_val = e1000_phy_hw_reset(hw);
3966 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
3971 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
3979 if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
3980 e1000_phy_init_script(hw);
3992 * hw - struct containing variables accessed by shared code
3995 e1000_phy_powerdown_workaround(struct e1000_hw *hw)
4003 if (hw->phy_type != e1000_phy_igp_3)
4008 reg = E1000_READ_REG(hw, PHY_CTRL);
4009 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
4013 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
4016 e1000_write_phy_reg(hw, IGP3_VR_CTRL, phy_data);
4019 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
4024 reg = E1000_READ_REG(hw, CTRL);
4025 E1000_WRITE_REG(hw, CTRL, reg | E1000_CTRL_PHY_RST);
4045 * hw - struct containing variables accessed by shared code
4048 e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw)
4055 if (hw->kmrn_lock_loss_workaround_disabled)
4061 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4062 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4067 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
4071 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
4080 e1000_phy_hw_reset(hw);
4084 reg = E1000_READ_REG(hw, PHY_CTRL);
4085 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
4098 * hw - Struct containing variables accessed by shared code
4101 e1000_detect_gig_phy(struct e1000_hw *hw)
4109 if (hw->phy_id != 0)
4115 if (hw->mac_type == e1000_82571 ||
4116 hw->mac_type == e1000_82572) {
4117 hw->phy_id = IGP01E1000_I_PHY_ID;
4118 hw->phy_type = e1000_phy_igp_2;
4128 if (hw->mac_type == e1000_80003es2lan)
4129 hw->phy_type = e1000_phy_gg82563;
4132 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
4136 hw->phy_id = (uint32_t) (phy_id_high << 16);
4138 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
4142 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
4143 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
4145 switch (hw->mac_type) {
4147 if (hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
4150 if (hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
4157 if (hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
4163 if (hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
4166 if (hw->phy_id == M88E1111_I_PHY_ID) match = TRUE;
4169 if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE;
4172 if (hw->phy_id == IGP03E1000_E_PHY_ID) match = TRUE;
4173 if (hw->phy_id == IFE_E_PHY_ID) match = TRUE;
4174 if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = TRUE;
4175 if (hw->phy_id == IFE_C_E_PHY_ID) match = TRUE;
4181 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
4184 phy_init_status = e1000_set_phy_type(hw);
4187 DEBUGOUT1("PHY ID %#08x detected\n", hw->phy_id);
4190 DEBUGOUT1("Invalid PHY ID %#08x\n", hw->phy_id);
4197 * hw - Struct containing variables accessed by shared code
4200 e1000_phy_reset_dsp(struct e1000_hw *hw)
4206 if (hw->phy_type != e1000_phy_gg82563) {
4207 ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
4210 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
4212 ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
4223 * hw - Struct containing variables accessed by shared code
4227 e1000_phy_igp_get_info(struct e1000_hw *hw,
4237 * and it stored in the hw->speed_downgraded parameter. */
4238 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4247 ret_val = e1000_check_polarity(hw, &polarity);
4253 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
4263 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
4275 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
4300 * hw - Struct containing variables accessed by shared code
4304 e1000_phy_ife_get_info(struct e1000_hw *hw,
4313 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4316 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
4325 ret_val = e1000_check_polarity(hw, &polarity);
4336 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
4350 * hw - Struct containing variables accessed by shared code
4354 e1000_phy_m88_get_info(struct e1000_hw *hw,
4364 * and it stored in the hw->speed_downgraded parameter. */
4365 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4367 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
4382 ret_val = e1000_check_polarity(hw, &polarity);
4387 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
4398 if (hw->phy_type != e1000_phy_gg82563) {
4402 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
4410 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
4429 * hw - Struct containing variables accessed by shared code
4433 e1000_phy_get_info(struct e1000_hw *hw,
4450 if (hw->media_type != e1000_media_type_copper) {
4455 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4459 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4468 if (hw->phy_type == e1000_phy_igp ||
4469 hw->phy_type == e1000_phy_igp_3 ||
4470 hw->phy_type == e1000_phy_igp_2)
4471 return e1000_phy_igp_get_info(hw, phy_info);
4472 else if (hw->phy_type == e1000_phy_ife)
4473 return e1000_phy_ife_get_info(hw, phy_info);
4475 return e1000_phy_m88_get_info(hw, phy_info);
4479 e1000_validate_mdi_setting(struct e1000_hw *hw)
4483 if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
4485 hw->mdix = 1;
4493 * Sets up eeprom variables in the hw struct. Must be called after mac_type
4497 * hw - Struct containing variables accessed by shared code
4500 e1000_init_eeprom_params(struct e1000_hw *hw)
4502 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4503 hw, EECD);
4509 switch (hw->mac_type) {
4598 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
4605 E1000_WRITE_REG(hw, EECD, eecd);
4625 uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG);
4634 if (hw->eeprom_shadow_ram != NULL) {
4636 hw->eeprom_shadow_ram[i].modified = FALSE;
4637 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
4641 hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
4644 hw->flash_bank_size = ((flash_size >> 16) & ICH_GFPREG_BASE_MASK) + 1;
4645 hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
4647 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
4649 hw->flash_bank_size /= 2 * sizeof(uint16_t);
4693 if (hw->mac_type <= e1000_82547_rev_2) {
4696 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
4718 * hw - Struct containing variables accessed by shared code
4722 e1000_raise_ee_clk(struct e1000_hw *hw,
4729 E1000_WRITE_REG(hw, EECD, *eecd);
4730 E1000_WRITE_FLUSH(hw);
4731 udelay(hw->eeprom.delay_usec);
4737 * hw - Struct containing variables accessed by shared code
4741 e1000_lower_ee_clk(struct e1000_hw *hw,
4748 E1000_WRITE_REG(hw, EECD, *eecd);
4749 E1000_WRITE_FLUSH(hw);
4750 udelay(hw->eeprom.delay_usec);
4756 * hw - Struct containing variables accessed by shared code
4761 e1000_shift_out_ee_bits(struct e1000_hw *hw,
4765 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4774 eecd = E1000_READ_REG(hw, EECD);
4791 E1000_WRITE_REG(hw, EECD, eecd);
4792 E1000_WRITE_FLUSH(hw);
4796 e1000_raise_ee_clk(hw, &eecd);
4797 e1000_lower_ee_clk(hw, &eecd);
4805 E1000_WRITE_REG(hw, EECD, eecd);
4811 * hw - Struct containing variables accessed by shared code
4814 e1000_shift_in_ee_bits(struct e1000_hw *hw,
4828 eecd = E1000_READ_REG(hw, EECD);
4835 e1000_raise_ee_clk(hw, &eecd);
4837 eecd = E1000_READ_REG(hw, EECD);
4843 e1000_lower_ee_clk(hw, &eecd);
4852 * hw - Struct containing variables accessed by shared code
4858 e1000_acquire_eeprom(struct e1000_hw *hw)
4860 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4865 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
4867 eecd = E1000_READ_REG(hw, EECD);
4869 if (hw->mac_type != e1000_82573) {
4871 if (hw->mac_type > e1000_82544) {
4873 E1000_WRITE_REG(hw, EECD, eecd);
4874 eecd = E1000_READ_REG(hw, EECD);
4879 eecd = E1000_READ_REG(hw, EECD);
4883 E1000_WRITE_REG(hw, EECD, eecd);
4885 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
4896 E1000_WRITE_REG(hw, EECD, eecd);
4900 E1000_WRITE_REG(hw, EECD, eecd);
4904 E1000_WRITE_REG(hw, EECD, eecd);
4914 * hw - Struct containing variables accessed by shared code
4917 e1000_standby_eeprom(struct e1000_hw *hw)
4919 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4922 eecd = E1000_READ_REG(hw, EECD);
4926 E1000_WRITE_REG(hw, EECD, eecd);
4927 E1000_WRITE_FLUSH(hw);
4932 E1000_WRITE_REG(hw, EECD, eecd);
4933 E1000_WRITE_FLUSH(hw);
4938 E1000_WRITE_REG(hw, EECD, eecd);
4939 E1000_WRITE_FLUSH(hw);
4944 E1000_WRITE_REG(hw, EECD, eecd);
4945 E1000_WRITE_FLUSH(hw);
4950 E1000_WRITE_REG(hw, EECD, eecd);
4951 E1000_WRITE_FLUSH(hw);
4954 E1000_WRITE_REG(hw, EECD, eecd);
4955 E1000_WRITE_FLUSH(hw);
4963 * hw - Struct containing variables accessed by shared code
4966 e1000_release_eeprom(struct e1000_hw *hw)
4972 eecd = E1000_READ_REG(hw, EECD);
4974 if (hw->eeprom.type == e1000_eeprom_spi) {
4978 E1000_WRITE_REG(hw, EECD, eecd);
4980 udelay(hw->eeprom.delay_usec);
4981 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
4987 E1000_WRITE_REG(hw, EECD, eecd);
4991 E1000_WRITE_REG(hw, EECD, eecd);
4992 E1000_WRITE_FLUSH(hw);
4993 udelay(hw->eeprom.delay_usec);
4997 E1000_WRITE_REG(hw, EECD, eecd);
4998 E1000_WRITE_FLUSH(hw);
4999 udelay(hw->eeprom.delay_usec);
5003 if (hw->mac_type > e1000_82544) {
5005 E1000_WRITE_REG(hw, EECD, eecd);
5008 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
5014 * hw - Struct containing variables accessed by shared code
5017 e1000_spi_eeprom_ready(struct e1000_hw *hw)
5031 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
5032 hw->eeprom.opcode_bits);
5033 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
5040 e1000_standby_eeprom(hw);
5057 * hw - Struct containing variables accessed by shared code
5063 e1000_read_eeprom(struct e1000_hw *hw,
5068 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5075 e1000_init_eeprom_params(hw);
5090 if (hw->eeprom.use_eerd == FALSE && e1000_is_onboard_nvm_eeprom(hw)) {
5092 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
5098 return e1000_read_eeprom_eerd(hw, offset, words, data);
5102 return e1000_read_eeprom_ich8(hw, offset, words, data);
5110 if (e1000_spi_eeprom_ready(hw)) {
5111 e1000_release_eeprom(hw);
5115 e1000_standby_eeprom(hw);
5122 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
5123 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
5131 word_in = e1000_shift_in_ee_bits(hw, 16);
5137 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
5139 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
5144 data[i] = e1000_shift_in_ee_bits(hw, 16);
5145 e1000_standby_eeprom(hw);
5150 e1000_release_eeprom(hw);
5158 * hw - Struct containing variables accessed by shared code
5164 e1000_read_eeprom_eerd(struct e1000_hw *hw,
5176 E1000_WRITE_REG(hw, EERD, eerd);
5177 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
5182 data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA);
5192 * hw - Struct containing variables accessed by shared code
5198 e1000_write_eeprom_eewr(struct e1000_hw *hw,
5207 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
5215 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
5220 E1000_WRITE_REG(hw, EEWR, register_value);
5222 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
5229 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
5236 * hw - Struct containing variables accessed by shared code
5239 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
5247 reg = E1000_READ_REG(hw, EERD);
5249 reg = E1000_READ_REG(hw, EEWR);
5264 * hw - Struct containing variables accessed by shared code
5267 e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
5273 assert(hw->mac_type != e1000_82576);
5275 if (hw->mac_type == e1000_ich8lan)
5278 if (hw->mac_type == e1000_82573) {
5279 eecd = E1000_READ_REG(hw, EECD);
5295 * hw - Struct containing variables accessed by shared code
5302 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
5309 if ((hw->mac_type == e1000_82573) &&
5310 (e1000_is_onboard_nvm_eeprom(hw) == FALSE)) {
5313 e1000_read_eeprom(hw, 0x10, 1, &eeprom_data);
5319 e1000_read_eeprom(hw, 0x23, 1, &eeprom_data);
5322 e1000_write_eeprom(hw, 0x23, 1, &eeprom_data);
5323 e1000_update_eeprom_checksum(hw);
5328 if (hw->mac_type == e1000_ich8lan) {
5334 e1000_read_eeprom(hw, 0x19, 1, &eeprom_data);
5337 e1000_write_eeprom(hw, 0x19, 1, &eeprom_data);
5338 e1000_update_eeprom_checksum(hw);
5343 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
5361 * hw - Struct containing variables accessed by shared code
5367 e1000_update_eeprom_checksum(struct e1000_hw *hw)
5376 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
5383 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
5386 } else if (hw->eeprom.type == e1000_eeprom_flash) {
5387 e1000_commit_shadow_ram(hw);
5388 } else if (hw->eeprom.type == e1000_eeprom_ich8) {
5389 e1000_commit_shadow_ram(hw);
5392 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
5394 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
5403 * hw - Struct containing variables accessed by shared code
5412 e1000_write_eeprom(struct e1000_hw *hw,
5417 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5424 e1000_init_eeprom_params(hw);
5437 return e1000_write_eeprom_eewr(hw, offset, words, data);
5440 return e1000_write_eeprom_ich8(hw, offset, words, data);
5443 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
5447 status = e1000_write_eeprom_microwire(hw, offset, words, data);
5449 status = e1000_write_eeprom_spi(hw, offset, words, data);
5454 e1000_release_eeprom(hw);
5462 * hw - Struct containing variables accessed by shared code
5469 e1000_write_eeprom_spi(struct e1000_hw *hw,
5474 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5482 if (e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
5484 e1000_standby_eeprom(hw);
5487 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
5490 e1000_standby_eeprom(hw);
5497 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
5499 e1000_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2),
5508 e1000_shift_out_ee_bits(hw, word_out, 16);
5516 e1000_standby_eeprom(hw);
5528 * hw - Struct containing variables accessed by shared code
5535 e1000_write_eeprom_microwire(struct e1000_hw *hw,
5540 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5553 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
5556 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
5559 e1000_standby_eeprom(hw);
5563 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
5566 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + words_written),
5570 e1000_shift_out_ee_bits(hw, data[words_written], 16);
5575 e1000_standby_eeprom(hw);
5582 eecd = E1000_READ_REG(hw, EECD);
5592 e1000_standby_eeprom(hw);
5603 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
5606 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
5616 * hw - Struct containing variables accessed by shared code
5622 e1000_commit_shadow_ram(struct e1000_hw *hw)
5635 if (hw->mac_type == e1000_82573) {
5637 flop = E1000_READ_REG(hw, FLOP);
5639 eecd = E1000_READ_REG(hw, EECD);
5652 E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET);
5656 E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD);
5659 eecd = E1000_READ_REG(hw, EECD);
5671 if (hw->mac_type == e1000_ich8lan && hw->eeprom_shadow_ram != NULL) {
5675 if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) {
5676 new_bank_offset = hw->flash_bank_size * 2;
5678 e1000_erase_ich8_4k_segment(hw, 1);
5680 old_bank_offset = hw->flash_bank_size * 2;
5682 e1000_erase_ich8_4k_segment(hw, 0);
5692 if (hw->eeprom_shadow_ram[i].modified == TRUE) {
5693 low_byte = (uint8_t)hw->eeprom_shadow_ram[i].eeprom_word;
5695 error = e1000_verify_write_ich8_byte(hw,
5702 (uint8_t)(hw->eeprom_shadow_ram[i].eeprom_word >> 8);
5706 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset,
5709 error = e1000_verify_write_ich8_byte(hw,
5715 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
5734 error = e1000_verify_write_ich8_byte(hw,
5753 e1000_read_ich8_byte(hw,
5757 error = e1000_verify_write_ich8_byte(hw,
5764 error = e1000_verify_write_ich8_byte(hw,
5770 hw->eeprom_shadow_ram[i].modified = FALSE;
5771 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
5783 * hw - Struct containing variables accessed by shared code
5786 e1000_read_mac_addr(struct e1000_hw * hw)
5794 if (hw->mac_type == e1000_82571) {
5799 ret_val = e1000_read_eeprom(hw, EEPROM_ALT_MAC_ADDR_PTR, 1,
5809 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
5814 ret_val = e1000_read_eeprom(hw, mac_addr_offset, 1,
5825 hw->laa_is_present = TRUE;
5830 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
5834 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF);
5835 hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8);
5838 switch (hw->mac_type) {
5847 E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
5848 hw->perm_mac_addr[5] ^= 0x01;
5853 hw->mac_addr[i] = hw->perm_mac_addr[i];
5860 * hw - Struct containing variables accessed by shared code
5867 e1000_init_rx_addrs(struct e1000_hw *hw)
5877 e1000_rar_set(hw, hw->mac_addr, 0);
5884 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE))
5886 if (hw->mac_type == e1000_ich8lan)
5892 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
5893 E1000_WRITE_FLUSH(hw);
5894 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
5895 E1000_WRITE_FLUSH(hw);
5902 * hw - Struct containing variables accessed by shared code
5906 e1000_hash_mc_addr(struct e1000_hw *hw,
5914 switch (hw->mc_filter_type) {
5920 if (hw->mac_type == e1000_ich8lan) {
5929 if (hw->mac_type == e1000_ich8lan) {
5938 if (hw->mac_type == e1000_ich8lan) {
5947 if (hw->mac_type == e1000_ich8lan) {
5958 if (hw->mac_type == e1000_ich8lan)
5967 * hw - Struct containing variables accessed by shared code
5971 e1000_mta_set(struct e1000_hw *hw,
5987 if (hw->mac_type == e1000_ich8lan)
5992 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
6000 if ((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) {
6001 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
6002 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
6003 E1000_WRITE_FLUSH(hw);
6004 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
6005 E1000_WRITE_FLUSH(hw);
6007 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
6008 E1000_WRITE_FLUSH(hw);
6015 * hw - Struct containing variables accessed by shared code
6020 e1000_rar_set(struct e1000_hw *hw,
6026 /* HW expects these in little endian so we reverse the byte order
6038 * If there are any Rx frames queued up or otherwise present in the HW
6039 * before RSS is enabled, and then we enable RSS, the HW Rx unit will
6042 * redirect all Rx traffic to manageability and then reset the HW.
6052 switch (hw->mac_type) {
6056 if (hw->leave_av_bit_off == TRUE)
6071 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
6072 E1000_WRITE_FLUSH(hw);
6073 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
6074 E1000_WRITE_FLUSH(hw);
6080 * hw - Struct containing variables accessed by shared code
6085 e1000_write_vfta(struct e1000_hw *hw,
6091 if (hw->mac_type == e1000_ich8lan)
6094 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
6095 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
6096 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
6097 E1000_WRITE_FLUSH(hw);
6098 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
6099 E1000_WRITE_FLUSH(hw);
6101 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
6102 E1000_WRITE_FLUSH(hw);
6109 * hw - Struct containing variables accessed by shared code
6112 e1000_clear_vfta(struct e1000_hw *hw)
6119 if (hw->mac_type == e1000_ich8lan)
6122 if (hw->mac_type == e1000_82573) {
6123 if (hw->mng_cookie.vlan_id != 0) {
6128 vfta_offset = (hw->mng_cookie.vlan_id >>
6131 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
6140 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
6141 E1000_WRITE_FLUSH(hw);
6146 e1000_id_led_init(struct e1000_hw * hw)
6157 if (hw->mac_type < e1000_82540) {
6162 ledctl = E1000_READ_REG(hw, LEDCTL);
6163 hw->ledctl_default = ledctl;
6164 hw->ledctl_mode1 = hw->ledctl_default;
6165 hw->ledctl_mode2 = hw->ledctl_default;
6167 if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
6172 if ((hw->mac_type == e1000_82573) &&
6177 if (hw->mac_type == e1000_ich8lan)
6189 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
6190 hw->ledctl_mode1 |= ledctl_on << (i << 3);
6195 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
6196 hw->ledctl_mode1 |= ledctl_off << (i << 3);
6206 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
6207 hw->ledctl_mode2 |= ledctl_on << (i << 3);
6212 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
6213 hw->ledctl_mode2 |= ledctl_off << (i << 3);
6226 * hw - Struct containing variables accessed by shared code
6229 e1000_setup_led(struct e1000_hw *hw)
6236 switch (hw->mac_type) {
6248 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
6249 &hw->phy_spd_default);
6252 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
6253 (uint16_t)(hw->phy_spd_default &
6259 if (hw->media_type == e1000_media_type_fiber) {
6260 ledctl = E1000_READ_REG(hw, LEDCTL);
6262 hw->ledctl_default = ledctl;
6269 E1000_WRITE_REG(hw, LEDCTL, ledctl);
6270 } else if (hw->media_type == e1000_media_type_copper)
6271 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
6285 * hw - Struct containing variables accessed by shared code
6288 e1000_blink_led_start(struct e1000_hw *hw)
6295 if (hw->mac_type < e1000_82571) {
6299 if (hw->media_type == e1000_media_type_fiber) {
6305 ledctl_blink = hw->ledctl_mode2;
6307 if (((hw->ledctl_mode2 >> (i * 8)) & 0xFF) ==
6312 E1000_WRITE_REG(hw, LEDCTL, ledctl_blink);
6320 * hw - Struct containing variables accessed by shared code
6323 e1000_cleanup_led(struct e1000_hw *hw)
6329 switch (hw->mac_type) {
6341 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
6342 hw->phy_spd_default);
6347 if (hw->phy_type == e1000_phy_ife) {
6348 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
6352 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default);
6362 * hw - Struct containing variables accessed by shared code
6365 e1000_led_on(struct e1000_hw *hw)
6367 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
6371 switch (hw->mac_type) {
6380 if (hw->media_type == e1000_media_type_fiber) {
6391 if (hw->media_type == e1000_media_type_fiber) {
6395 } else if (hw->phy_type == e1000_phy_ife) {
6396 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6398 } else if (hw
6399 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2);
6405 E1000_WRITE_REG(hw, CTRL, ctrl);
6413 * hw - Struct containing variables accessed by shared code
6416 e1000_led_off(struct e1000_hw *hw)
6418 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
6422 switch (hw->mac_type) {
6431 if (hw->media_type == e1000_media_type_fiber) {
6442 if (hw->media_type == e1000_media_type_fiber) {
6446 } else if (hw->phy_type == e1000_phy_ife) {
6447 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6449 } else if (hw->media_type == e1000_media_type_copper) {
6450 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
6456 E1000_WRITE_REG(hw, CTRL, ctrl);
6464 * hw - Struct containing variables accessed by shared code
6467 e1000_clear_hw_cntrs(struct e1000_hw *hw)
6471 temp = E1000_READ_REG(hw, CRCERRS);
6472 temp = E1000_READ_REG(hw, SYMERRS);
6473 temp = E1000_READ_REG(hw, MPC);
6474 temp = E1000_READ_REG(hw, SCC);
6475 temp = E1000_READ_REG(hw, ECOL);
6476 temp = E1000_READ_REG(hw, MCC);
6477 temp = E1000_READ_REG(hw, LATECOL);
6478 temp = E1000_READ_REG(hw, COLC);
6479 temp = E1000_READ_REG(hw, DC);
6480 temp = E1000_READ_REG(hw, SEC);
6481 temp = E1000_READ_REG(hw, RLEC);
6482 temp = E1000_READ_REG(hw, XONRXC);
6483 temp = E1000_READ_REG(hw, XONTXC);
6484 temp = E1000_READ_REG(hw, XOFFRXC);
6485 temp = E1000_READ_REG(hw, XOFFTXC);
6486 temp = E1000_READ_REG(hw, FCRUC);
6488 if (hw->mac_type != e1000_ich8lan) {
6489 temp = E1000_READ_REG(hw, PRC64);
6490 temp = E1000_READ_REG(hw, PRC127);
6491 temp = E1000_READ_REG(hw, PRC255);
6492 temp = E1000_READ_REG(hw, PRC511);
6493 temp = E1000_READ_REG(hw, PRC1023);
6494 temp = E1000_READ_REG(hw, PRC1522);
6497 temp = E1000_READ_REG(hw, GPRC);
6498 temp = E1000_READ_REG(hw, BPRC);
6499 temp = E1000_READ_REG(hw, MPRC);
6500 temp = E1000_READ_REG(hw, GPTC);
6501 temp = E1000_READ_REG(hw, GORCL);
6502 temp = E1000_READ_REG(hw, GORCH);
6503 temp = E1000_READ_REG(hw, GOTCL);
6504 temp = E1000_READ_REG(hw, GOTCH);
6505 temp = E1000_READ_REG(hw, RNBC);
6506 temp = E1000_READ_REG(hw, RUC);
6507 temp = E1000_READ_REG(hw, RFC);
6508 temp = E1000_READ_REG(hw, ROC);
6509 temp = E1000_READ_REG(hw, RJC);
6510 temp = E1000_READ_REG(hw, TORL);
6511 temp = E1000_READ_REG(hw, TORH);
6512 temp = E1000_READ_REG(hw, TOTL);
6513 temp = E1000_READ_REG(hw, TOTH);
6514 temp = E1000_READ_REG(hw, TPR);
6515 temp = E1000_READ_REG(hw, TPT);
6517 if (hw->mac_type != e1000_ich8lan) {
6518 temp = E1000_READ_REG(hw, PTC64);
6519 temp = E1000_READ_REG(hw, PTC127);
6520 temp = E1000_READ_REG(hw, PTC255);
6521 temp = E1000_READ_REG(hw, PTC511);
6522 temp = E1000_READ_REG(hw, PTC1023);
6523 temp = E1000_READ_REG(hw, PTC1522);
6526 temp = E1000_READ_REG(hw, MPTC);
6527 temp = E1000_READ_REG(hw, BPTC);
6529 if (hw->mac_type < e1000_82543) return;
6531 temp = E1000_READ_REG(hw, ALGNERRC);
6532 temp = E1000_READ_REG(hw, RXERRC);
6533 temp = E1000_READ_REG(hw, TNCRS);
6534 temp = E1000_READ_REG(hw, CEXTERR);
6535 temp = E1000_READ_REG(hw, TSCTC);
6536 temp = E1000_READ_REG(hw, TSCTFC);
6538 if (hw->mac_type <= e1000_82544) return;
6540 temp = E1000_READ_REG(hw, MGTPRC);
6541 temp = E1000_READ_REG(hw, MGTPDC);
6542 temp = E1000_READ_REG(hw, MGTPTC);
6544 if (hw->mac_type <= e1000_82547_rev_2) return;
6546 temp = E1000_READ_REG(hw, IAC);
6547 temp = E1000_READ_REG(hw, ICRXOC);
6549 if (hw->mac_type == e1000_ich8lan) return;
6551 temp = E1000_READ_REG(hw, ICRXPTC);
6552 temp = E1000_READ_REG(hw, ICRXATC);
6553 temp = E1000_READ_REG(hw, ICTXPTC);
6554 temp = E1000_READ_REG(hw, ICTXATC);
6555 temp = E1000_READ_REG(hw, ICTXQEC);
6556 temp = E1000_READ_REG(hw, ICTXQMTC);
6557 temp = E1000_READ_REG(hw, ICRXDMTC);
6563 * hw - Struct containing variables accessed by shared code
6566 * hw->ifs_params_forced to TRUE. However, you must initialize hw->
6571 e1000_reset_adaptive(struct e1000_hw *hw)
6575 if (hw->adaptive_ifs) {
6576 if (!hw->ifs_params_forced) {
6577 hw->current_ifs_val = 0;
6578 hw->ifs_min_val = IFS_MIN;
6579 hw->ifs_max_val = IFS_MAX;
6580 hw->ifs_step_size = IFS_STEP;
6581 hw->ifs_ratio = IFS_RATIO;
6583 hw->in_ifs_mode = FALSE;
6584 E1000_WRITE_REG(hw, AIT, 0);
6594 * hw - Struct containing variables accessed by shared code
6599 e1000_update_adaptive(struct e1000_hw *hw)
6603 if (hw->adaptive_ifs) {
6604 if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
6605 if (hw->tx_packet_delta > MIN_NUM_XMITS) {
6606 hw->in_ifs_mode = TRUE;
6607 if (hw->current_ifs_val < hw->ifs_max_val) {
6608 if (hw->current_ifs_val == 0)
6609 hw->current_ifs_val = hw->ifs_min_val;
6611 hw->current_ifs_val += hw->ifs_step_size;
6612 E1000_WRITE_REG(hw, AIT, hw->current_ifs_val);
6616 if (hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
6617 hw->current_ifs_val = 0;
6618 hw->in_ifs_mode = FALSE;
6619 E1000_WRITE_REG(hw, AIT, 0);
6630 * hw - Struct containing variables accessed by shared code
6635 e1000_tbi_adjust_stats(struct e1000_hw *hw,
6676 if (frame_len == hw->max_frame_size) {
6710 * hw - Struct containing variables accessed by shared code
6713 e1000_get_bus_info(struct e1000_hw *hw)
6719 switch (hw->mac_type) {
6722 hw->bus_type = e1000_bus_type_pci;
6723 hw->bus_speed = e1000_bus_speed_unknown;
6724 hw->bus_width = e1000_bus_width_unknown;
6731 hw->bus_type = e1000_bus_type_pci_express;
6732 hw->bus_speed = e1000_bus_speed_2500;
6733 ret_val = e1000_read_pcie_cap_reg(hw,
6737 hw->bus_width = e1000_bus_width_unknown;
6739 hw->bus_width = (pci_ex_link_status & PCI_EX_LINK_WIDTH_MASK) >>
6743 hw->bus_type = e1000_bus_type_pci_express;
6744 hw->bus_speed = e1000_bus_speed_2500;
6745 hw->bus_width = e1000_bus_width_pciex_1;
6748 status = E1000_READ_REG(hw, STATUS);
6749 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
6752 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
6753 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
6755 } else if (hw->bus_type == e1000_bus_type_pci) {
6756 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
6761 hw->bus_speed = e1000_bus_speed_66;
6764 hw->bus_speed = e1000_bus_speed_100;
6767 hw->bus_speed = e1000_bus_speed_133;
6770 hw->bus_speed = e1000_bus_speed_reserved;
6774 hw->bus_width = (status & E1000_STATUS_BUS64) ?
6784 * hw - Struct containing variables accessed by shared code
6789 e1000_write_reg_io(struct e1000_hw *hw,
6793 unsigned long io_addr = hw->io_base;
6794 unsigned long io_data = hw->io_base + 4;
6796 e1000_io_write(hw, io_addr, offset);
6797 e1000_io_write(hw, io_data, value);
6803 * hw - Struct containing variables accessed by shared code
6816 e1000_get_cable_length(struct e1000_hw *hw,
6830 if (hw->phy_type == e1000_phy_m88) {
6832 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6865 } else if (hw->phy_type == e1000_phy_gg82563) {
6866 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
6893 } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
6904 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
6940 } else if (hw->phy_type == e1000_phy_igp_2 ||
6941 hw->phy_type == e1000_phy_igp_3) {
6951 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
6993 * hw - Struct containing variables accessed by shared code
7007 e1000_check_polarity(struct e1000_hw *hw,
7015 if ((hw->phy_type == e1000_phy_m88) ||
7016 (hw->phy_type == e1000_phy_gg82563)) {
7018 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
7026 } else if (hw->phy_type == e1000_phy_igp ||
7027 hw->phy_type == e1000_phy_igp_3 ||
7028 hw->phy_type == e1000_phy_igp_2) {
7030 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
7041 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
7055 } else if (hw->phy_type == e1000_phy_ife) {
7056 ret_val = e1000_read_phy_reg(hw, IFE_PHY_EXTENDED_STATUS_CONTROL,
7070 * hw - Struct containing variables accessed by shared code
7083 e1000_check_downshift(struct e1000_hw *hw)
7090 if (hw->phy_type == e1000_phy_igp ||
7091 hw->phy_type == e1000_phy_igp_3 ||
7092 hw->phy_type == e1000_phy_igp_2) {
7093 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
7098 hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
7099 } else if ((hw->phy_type == e1000_phy_m88) ||
7100 (hw->phy_type == e1000_phy_gg82563)) {
7101 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
7106 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
7108 } else if (hw->phy_type == e1000_phy_ife) {
7110 hw->speed_downgraded = FALSE;
7121 * hw: Struct containing variables accessed by shared code
7129 e1000_config_dsp_after_link_change(struct e1000_hw *hw,
7143 if (hw->phy_type != e1000_phy_igp)
7147 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
7155 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
7159 if ((hw->dsp_config_state == e1000_dsp_config_enabled) &&
7163 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
7170 ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],
7175 hw->dsp_config_state = e1000_dsp_config_activated;
7178 if ((hw->ffe_config_state == e1000_ffe_config_enabled) &&
7185 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
7192 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
7199 hw->ffe_config_state = e1000_ffe_config_active;
7201 ret_val = e1000_write_phy_reg(hw,
7215 if (hw->dsp_config_state == e1000_dsp_config_activated) {
7218 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
7224 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
7231 ret_val = e1000_write_phy_reg(hw, 0x0000,
7236 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data);
7243 ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data);
7248 ret_val = e1000_write_phy_reg(hw, 0x0000,
7256 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7261 hw->dsp_config_state = e1000_dsp_config_enabled;
7264 if (hw->ffe_config_state == e1000_ffe_config_active) {
7267 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
7273 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
7280 ret_val = e1000_write_phy_reg(hw, 0x0000,
7284 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
7289 ret_val = e1000_write_phy_reg(hw, 0x0000,
7297 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7302 hw->ffe_config_state = e1000_ffe_config_enabled;
7314 * hw - Struct containing variables accessed by shared code
7317 e1000_set_phy_mode(struct e1000_hw *hw)
7324 if ((hw->mac_type == e1000_82545_rev_3) &&
7325 (hw->media_type == e1000_media_type_copper)) {
7326 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data);
7333 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B);
7336 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104);
7340 hw->phy_reset_disable = FALSE;
7353 * hw: Struct containing variables accessed by shared code
7362 e1000_set_d3_lplu_state(struct e1000_hw *hw,
7370 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
7371 && hw->phy_type != e1000_phy_igp_3)
7377 if (hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) {
7378 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
7381 } else if (hw->mac_type == e1000_ich8lan) {
7385 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
7387 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
7393 if (hw->mac_type == e1000_82541_rev_2 ||
7394 hw->mac_type == e1000_82547_rev_2) {
7396 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
7400 if (hw->mac_type == e1000_ich8lan) {
7402 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7405 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
7416 if (hw->smart_speed == e1000_smart_speed_on) {
7417 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7423 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7427 } else if (hw->smart_speed == e1000_smart_speed_off) {
7428 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7434 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7440 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
7441 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
7442 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
7444 if (hw->mac_type == e1000_82541_rev_2 ||
7445 hw->mac_type == e1000_82547_rev_2) {
7447 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
7451 if (hw->mac_type == e1000_ich8lan) {
7453 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7456 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
7464 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
7469 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
7483 * hw: Struct containing variables accessed by shared code
7492 e1000_set_d0_lplu_state(struct e1000_hw *hw,
7500 if (hw->mac_type <= e1000_82547_rev_2)
7503 if (hw->mac_type == e1000_ich8lan) {
7504 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
7506 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
7512 if (hw->mac_type == e1000_ich8lan) {
7514 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7517 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
7526 if (hw->smart_speed == e1000_smart_speed_on) {
7527 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7533 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7537 } else if (hw->smart_speed == e1000_smart_speed_off) {
7538 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7544 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7553 if (hw->mac_type == e1000_ich8lan) {
7555 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7558 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
7564 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
7569 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
7580 * hw - Struct containing variables accessed by shared code
7583 e1000_set_vco_speed(struct e1000_hw *hw)
7591 switch (hw->mac_type) {
7601 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
7605 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
7609 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
7614 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
7620 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
7624 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
7629 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
7633 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
7647 e1000_host_if_read_cookie(struct e1000_hw * hw, uint8_t *buffer)
7658 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i);
7674 e1000_mng_enable_host_if(struct e1000_hw * hw)
7680 hicr = E1000_READ_REG(hw, HICR);
7687 hicr = E1000_READ_REG(hw, HICR);
7708 e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer,
7728 data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset);
7733 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data);
7752 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
7763 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
7776 e1000_mng_write_cmd_header(struct e1000_hw * hw,
7801 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i));
7802 E1000_WRITE_FLUSH(hw);
7816 e1000_mng_write_commit(struct e1000_hw * hw)
7820 hicr = E1000_READ_REG(hw, HICR);
7822 E1000_WRITE_REG(hw, HICR, hicr | E1000_HICR_C);
7834 e1000_check_mng_mode(struct e1000_hw *hw)
7838 fwsm = E1000_READ_REG(hw, FWSM);
7840 if (hw->mac_type == e1000_ich8lan) {
7856 e1000_mng_write_dhcp_info(struct e1000_hw * hw, uint8_t *buffer,
7868 ret_val = e1000_mng_enable_host_if(hw);
7870 ret_val = e1000_mng_host_if_write(hw, buffer, length, sizeof(hdr),
7873 ret_val = e1000_mng_write_cmd_header(hw, &hdr);
7875 ret_val = e1000_mng_write_commit(hw);
7908 e1000_enable_tx_pkt_filtering(struct e1000_hw *hw)
7914 struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie);
7915 uint8_t *buffer = (uint8_t *) &(hw->mng_cookie);
7917 if (e1000_check_mng_mode(hw)) {
7918 ret_val = e1000_mng_enable_host_if(hw);
7920 ret_val = e1000_host_if_read_cookie(hw, buffer);
7937 hw->tx_pkt_filtering = tx_filter;
7944 * hw - Struct containing variables accessed by shared code
7950 e1000_enable_mng_pass_thru(struct e1000_hw *hw)
7955 if (hw->asf_firmware_present) {
7956 manc = E1000_READ_REG(hw, MANC);
7961 if (e1000_arc_subsystem_valid(hw) == TRUE) {
7962 fwsm = E1000_READ_REG(hw, FWSM);
7963 factps = E1000_READ_REG(hw, FACTPS);
7976 e1000_polarity_reversal_workaround(struct e1000_hw *hw)
7986 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
7989 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
7993 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
8003 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8007 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8020 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
8024 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
8028 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
8032 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
8036 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
8046 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8050 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8064 * hw: Struct containing variables accessed by shared code
8070 e1000_set_pci_express_master_disable(struct e1000_hw *hw)
8076 if (hw->bus_type != e1000_bus_type_pci_express)
8079 ctrl = E1000_READ_REG(hw, CTRL);
8081 E1000_WRITE_REG(hw, CTRL, ctrl);
8088 * hw: Struct containing variables accessed by shared code
8096 e1000_disable_pciex_master(struct e1000_hw *hw)
8102 if (hw->bus_type != e1000_bus_type_pci_express)
8105 e1000_set_pci_express_master_disable(hw);
8108 if (!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
8127 * hw: Struct containing variables accessed by shared code
8134 e1000_get_auto_rd_done(struct e1000_hw *hw)
8140 switch (hw->mac_type) {
8151 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD)
8158 DEBUGOUT("Auto read by HW from EEPROM has not completed.\n");
8167 if (hw->mac_type == e1000_82573)
8176 * hw: Struct containing variables accessed by shared code
8183 e1000_get_phy_cfg_done(struct e1000_hw *hw)
8190 switch (hw->mac_type) {
8197 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
8203 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
8224 * hw: Struct containing variables accessed by shared code
8231 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
8238 if (!hw->eeprom_semaphore_present)
8241 if (hw->mac_type == e1000_80003es2lan) {
8243 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
8248 timeout = hw->eeprom.word_size + 1;
8250 swsm = E1000_READ_REG(hw, SWSM);
8252 E1000_WRITE_REG(hw, SWSM, swsm);
8254 swsm = E1000_READ_REG(hw, SWSM);
8264 e1000_put_hw_eeprom_semaphore(hw);
8273 * This function clears HW semaphore bits.
8275 * hw: Struct containing variables accessed by shared code
8281 e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
8287 if (!hw->eeprom_semaphore_present)
8290 swsm = E1000_READ_REG(hw, SWSM);
8291 if (hw->mac_type == e1000_80003es2lan) {
8296 E1000_WRITE_REG(hw, SWSM, swsm);
8303 * hw: Struct containing variables accessed by shared code
8310 e1000_get_software_semaphore(struct e1000_hw *hw)
8312 int32_t timeout = hw->eeprom.word_size + 1;
8317 if (hw->mac_type != e1000_80003es2lan) {
8322 swsm = E1000_READ_REG(hw, SWSM);
8342 * hw: Struct containing variables accessed by shared code
8346 e1000_release_software_semaphore(struct e1000_hw *hw)
8352 if (hw->mac_type != e1000_80003es2lan) {
8356 swsm = E1000_READ_REG(hw, SWSM);
8359 E1000_WRITE_REG(hw, SWSM, swsm);
8367 * hw - Struct containing variables accessed by shared code
8374 e1000_check_phy_reset_block(struct e1000_hw *hw)
8379 if (hw->mac_type == e1000_ich8lan) {
8380 fwsm = E1000_READ_REG(hw, FWSM);
8385 if (hw->mac_type > e1000_82547_rev_2)
8386 manc = E1000_READ_REG(hw, MANC);
8392 e1000_arc_subsystem_valid(struct e1000_hw *hw)
8401 switch (hw->mac_type) {
8407 fwsm = E1000_READ_REG(hw, FWSM);
8423 * hw - Struct containing variables accessed by shared code.
8430 e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop)
8436 if (hw->bus_type == e1000_bus_type_unknown)
8437 e1000_get_bus_info(hw);
8439 if (hw->bus_type != e1000_bus_type_pci_express)
8443 gcr_reg = E1000_READ_REG(hw, GCR);
8446 E1000_WRITE_REG(hw, GCR, gcr_reg);
8448 if (hw->mac_type == e1000_ich8lan) {
8451 E1000_WRITE_REG(hw, GCR, PCI_EX_82566_SNOOP_ALL);
8453 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
8455 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
8465 * SW, FW and HW.
8467 * hw: Struct containing variables accessed by shared code
8471 e1000_get_software_flag(struct e1000_hw *hw)
8478 if (hw->mac_type == e1000_ich8lan) {
8480 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
8482 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
8484 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
8492 DEBUGOUT("FW or HW locks the resource too long.\n");
8504 * SW, FW and HW.
8506 * hw: Struct containing variables accessed by shared code
8510 e1000_release_software_flag(struct e1000_hw *hw)
8516 if (hw->mac_type == e1000_ich8lan) {
8517 extcnf_ctrl= E1000_READ_REG(hw, EXTCNF_CTRL);
8519 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
8529 * hw - Struct containing variables accessed by shared code
8535 e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
8551 flash_bank = (E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL) ? 1 : 0;
8554 bank_offset = flash_bank * (hw->flash_bank_size * 2);
8556 error = e1000_get_software_flag(hw);
8561 if (hw->eeprom_shadow_ram != NULL &&
8562 hw->eeprom_shadow_ram[offset+i].modified == TRUE) {
8563 data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word;
8567 error = e1000_read_ich8_word(hw, act_offset, &word);
8574 e1000_release_software_flag(hw);
8581 * register. Actually, writes are written to the shadow ram cache in the hw
8582 * structure hw->e1000_shadow_ram. e1000_commit_shadow_ram flushes this to
8585 * hw - Struct containing variables accessed by shared code
8591 e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
8597 error = e1000_get_software_flag(hw);
8608 if (hw->eeprom_shadow_ram != NULL) {
8611 hw->eeprom_shadow_ram[offset+i].modified = TRUE;
8612 hw->eeprom_shadow_ram[offset+i].eeprom_word = data[i];
8626 e1000_release_software_flag(hw);
8635 * hw - The pointer to the hw structure
8638 e1000_ich8_cycle_init(struct e1000_hw *hw)
8646 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8648 /* May be check the Flash Des Valid bit in Hw status */
8654 /* Clear FCERR in Hw status by writing 1 */
8655 /* Clear DAEL in Hw status by writing a 1 */
8659 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
8674 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
8680 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8691 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
8702 * hw - The pointer to the hw structure
8705 e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout)
8712 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
8713 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8715 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8719 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8734 * hw - The pointer to the hw structure
8740 e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index,
8757 hw->flash_base_addr;
8762 error = e1000_ich8_cycle_init(hw);
8766 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8770 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8776 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
8778 error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
8784 flash_data = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0);
8796 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8813 * hw - The pointer to the hw structure
8819 e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size,
8836 hw->flash_base_addr;
8841 error = e1000_ich8_cycle_init(hw);
8845 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8849 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8853 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
8860 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
8864 error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
8872 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8889 * hw - pointer to e1000_hw structure
8894 e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t* data)
8899 status = e1000_read_ich8_data(hw, index, 1, &word);
8912 * hw - pointer to e1000_hw structure
8917 e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte)
8924 error = e1000_write_ich8_byte(hw, index, byte);
8929 error = e1000_write_ich8_byte(hw, index, byte);
8945 * hw - pointer to e1000_hw structure
8950 e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t data)
8955 status = e1000_write_ich8_data(hw, index, 1, word);
8963 * hw - pointer to e1000_hw structure
8968 e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data)
8971 status = e1000_read_ich8_data(hw, index, 2, data);
8979 * hw - pointer to e1000_hw structure
8987 e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank)
9000 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
9002 /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */
9003 /* 00: The Hw sector is 256 bytes, hence we need to erase 16
9004 * consecutive sectors. The start index for the nth Hw sector can be
9006 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
9007 * The start index for the nth Hw sector can be calculated
9009 * 10: The HW sector is 8K bytes
9010 * 11: The Hw sector size is 64K bytes */
9012 /* Hw sector size 256 */
9030 error = e1000_ich8_cycle_init(hw);
9036 /* Write a value 11 (block Erase) in Flash Cycle field in Hw flash
9038 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
9040 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
9047 flash_linear_address += hw->flash_base_addr;
9050 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
9052 error = e1000_ich8_flash_cycle(hw, ICH_FLASH_ERASE_TIMEOUT);
9058 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
9077 e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
9089 ret_val = e1000_read_eeprom(hw, (word_addr + i*2), 1, ®_data);
9093 ret_val = e1000_read_eeprom(hw, (word_addr + i*2 + 1), 1, ®_addr);
9097 ret_val = e1000_get_software_flag(hw);
9101 ret_val = e1000_write_phy_reg_ex(hw, (uint32_t)reg_addr, reg_data);
9103 e1000_release_software_flag(hw);
9116 * hw: Struct containing variables accessed by shared code
9119 e1000_init_lcd_from_nvm(struct e1000_hw *hw)
9123 if (hw->phy_type != e1000_phy_igp_3)
9127 reg_data = E1000_READ_REG(hw, FEXTNVM);
9134 reg_data = E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE;
9140 reg_data = E1000_READ_REG(hw, STATUS);
9142 E1000_WRITE_REG(hw, STATUS, reg_data);
9144 /* Make sure HW does not configure LCD from PHY extended configuration
9146 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
9148 reg_data = E1000_READ_REG(hw, EXTCNF_SIZE);
9152 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
9158 ret_val = e1000_init_lcd_from_nvm_config_region(hw, cnf_base_addr,
