Lines Matching defs:ioaddr
56 static u32 ioaddr; /* Globally used for the card's io address */
419 lp->a.reset(ioaddr);
422 lp->a.write_bcr(ioaddr, 20, 2);
425 val = lp->a.read_bcr(ioaddr, 2) & ~2;
428 lp->a.write_bcr(ioaddr, 2, val);
432 val = lp->a.read_bcr(ioaddr, 9) & ~3;
441 read_csr(ioaddr,
442 88) | (lp->a.read_csr(ioaddr,
448 lp->a.write_bcr(ioaddr, 9, val);
452 val = lp->a.read_csr(ioaddr, 124) & ~0x10;
455 lp->a.write_csr(ioaddr, 124, val);
458 val = lp->a.read_bcr(ioaddr, 32) & ~0x38; /* disable Auto Negotiation, set 10Mpbs, HD */
463 lp->a.write_bcr(ioaddr, 32, val);
466 val = lp->a.read_bcr(ioaddr, 32) & ~0x98;
468 lp->a.write_bcr(ioaddr, 32, val);
474 val = lp->a.read_csr(ioaddr, 3);
476 lp->a.write_csr(ioaddr, 3, val);
482 val = lp->a.read_csr(ioaddr, 3);
490 lp->a.write_csr(ioaddr, 3, val);
494 val = lp->a.read_csr(ioaddr, 5);
496 lp->a.write_csr(ioaddr, 5, val);
507 lp->a.write_csr(ioaddr, 1,
509 lp->a.write_csr(ioaddr, 2, (virt_to_bus(&lp->init_block)) >> 16);
510 lp->a.write_csr(ioaddr, 4, 0x0915);
511 lp->a.write_csr(ioaddr, 0, 0x0001);
516 if (lp->a.read_csr(ioaddr, 0) & 0x0100)
522 lp->a.write_csr(ioaddr, 0, 0x0042);
524 dprintf(("pcnet32 open, csr0 %hX.\n", lp->a.read_csr(ioaddr, 0)));
609 lp->a.write_csr(ioaddr, 0, 0x0048);
631 lp->a.write_csr(ioaddr, 0, 0x0004);
637 lp->a.write_bcr(ioaddr, 20, 0);
670 if (pci->ioaddr == 0)
674 ioaddr = pci->ioaddr;
679 nic->ioaddr = pci->ioaddr & ~3;
682 pcnet32_wio_reset(ioaddr);
685 if (pcnet32_wio_read_csr(ioaddr, 0) == 4
686 && pcnet32_wio_check(ioaddr)) {
689 pcnet32_dwio_reset(ioaddr);
690 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4
691 && pcnet32_dwio_check(ioaddr)) {
698 a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16);
751 media = a->read_bcr(ioaddr, 49);
754 a->write_bcr(ioaddr, 49, media);
776 a->write_bcr(ioaddr, 18,
777 (a->read_bcr(ioaddr, 18) | 0x0800));
778 a->write_csr(ioaddr, 80,
779 (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
784 DBG ( "%s at %hX,", chipname, (unsigned int) ioaddr );
788 promaddr[i] = inb(ioaddr + i);
796 DBG ( "%s: IO Addr 0x%hX, MAC Addr %s\n ", chipname, (unsigned int) ioaddr,
807 i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */
823 i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */
833 i = a->read_bcr(ioaddr, 25);
835 i = a->read_bcr(ioaddr, 26);
837 i = a->read_bcr(ioaddr, 27);
889 a->write_bcr(ioaddr, 20, 2);
891 a->write_csr(ioaddr, 1, (virt_to_bus(&lp->init_block)) & 0xffff);
892 a->write_csr(ioaddr, 2, (virt_to_bus(&lp->init_block)) >> 16);
902 // a->write_csr(ioaddr, 0, 0x41);
968 phyaddr = lp->a.read_bcr(ioaddr, 33);
970 lp->a.write_bcr(ioaddr, 33,
972 val_out = lp->a.read_bcr(ioaddr, 34);
973 lp->a.write_bcr(ioaddr, 33, phyaddr);
987 phyaddr = lp->a.read_bcr(ioaddr, 33);
989 lp->a.write_bcr(ioaddr, 33,
991 lp->a.write_bcr(ioaddr, 34, val);
992 lp->a.write_bcr(ioaddr, 33, phyaddr);
