Lines Matching refs:hw
62 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
63 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
64 static void yukon_init(struct skge_hw *hw, int port);
65 static void genesis_mac_init(struct skge_hw *hw, int port);
68 static void skge_phyirq(struct skge_hw *hw);
94 static u32 skge_supported_modes(const struct skge_hw *hw)
98 if (hw->copper) {
107 if (hw->chip_id == CHIP_ID_GENESIS)
113 else if (hw->chip_id == CHIP_ID_YUKON)
123 static inline u32 hwkhz(const struct skge_hw *hw)
125 return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125;
129 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
131 return hwkhz(hw) * usec / 1000;
137 struct skge_hw *hw = skge->hw;
140 if (hw->chip_id == CHIP_ID_GENESIS) {
143 if (hw->phy_type == SK_PHY_BCOM)
144 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
146 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
147 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
149 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
150 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
151 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
155 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
156 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
158 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
159 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
164 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
165 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
166 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
168 if (hw->phy_type == SK_PHY_BCOM)
169 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
171 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
172 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
173 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
180 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
181 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
189 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
195 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
201 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
202 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
221 * pci_read_config_dword(skge->hw->pdev, PCI_DEV_REG2, ®2);
254 * struct pci_dev *pdev = skge->hw->pdev;
280 * struct pci_dev *pdev = skge->hw->pdev;
398 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
410 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
417 static void xm_link_down(struct skge_hw *hw, int port)
419 struct net_device *dev = hw->dev[port];
422 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
428 static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
432 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
433 *val = xm_read16(hw, port, XM_PHY_DATA);
435 if (hw->phy_type == SK_PHY_XMAC)
439 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
446 *val = xm_read16(hw, port, XM_PHY_DATA);
451 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
454 if (__xm_phy_read(hw, port, reg, &v))
456 hw->dev[port]->name);
460 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
464 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
466 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
473 xm_write16(hw, port, XM_PHY_DATA, val);
475 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
482 static void genesis_init(struct skge_hw *hw)
485 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
486 skge_write8(hw, B2_BSC_CTRL, BSC_START);
489 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
492 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
493 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
494 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
495 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
497 skge_write8(hw, B3_MA_RCINI_RX1, 0);
498 skge_write8(hw, B3_MA_RCINI_RX2, 0);
499 skge_write8(hw, B3_MA_RCINI_TX1, 0);
500 skge_write8(hw, B3_MA_RCINI_TX2, 0);
503 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
504 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
505 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
506 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
507 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
510 static void genesis_reset(struct skge_hw *hw, int port)
515 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
518 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
519 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
520 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
521 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
522 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
525 if (hw->phy_type == SK_PHY_BCOM)
526 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
528 xm_outhash(hw, port, XM_HSM, zero);
531 reg = xm_read32(hw, port, XM_MODE);
532 xm_write32(hw, port, XM_MODE, reg | XM_MD_FTF);
533 xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF);
555 static void bcom_check_link(struct skge_hw *hw, int port)
557 struct net_device *dev = hw->dev[port];
562 xm_phy_read(hw, port, PHY_BCOM_STAT);
563 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
566 xm_link_down(hw, port);
576 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
583 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
625 struct skge_hw *hw = skge->hw;
645 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
648 r = xm_read16(hw, port, XM_MMU_CMD);
650 xm_write16(hw, port, XM_MMU_CMD,r);
659 xm_phy_write(hw, port,
669 xm_phy_write(hw, port,
678 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
680 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
683 xm_read16(hw, port, XM_ISRC);
699 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
706 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
710 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
713 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
714 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
717 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
722 struct skge_hw *hw = skge->hw;
734 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
748 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
757 struct skge_hw *hw = skge->hw;
762 xm_phy_read(hw, port, PHY_XMAC_STAT);
763 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
766 xm_link_down(hw, port);
776 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
783 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
832 struct skge_hw *hw = skge->hw;
841 if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
847 u16 msk = xm_read16(hw, port, XM_IMSK);
849 xm_write16(hw, port, XM_IMSK, msk);
850 xm_read16(hw, port, XM_ISRC);
854 static void genesis_mac_init(struct skge_hw *hw, int port)
856 struct net_device *dev = hw->dev[port];
863 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
865 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
874 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
881 if (hw->phy_type != SK_PHY_XMAC) {
883 r = skge_read32(hw, B2_GP_IO);
889 skge_write32(hw, B2_GP_IO, r);
892 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
896 switch(hw->phy_type) {
902 bcom_check_link(hw, port);
906 xm_outaddr(hw, port, XM_SA, dev->ll_addr);
910 xm_outaddr(hw, port, XM_EXM(i), zero);
913 xm_write16(hw, port, XM_STAT_CMD,
916 xm_write16(hw, port, XM_STAT_CMD,
920 xm_write16(hw, port, XM_RX_HI_WM, 1450);
933 xm_write16(hw, port, XM_RX_CMD, r);
936 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
938 xm_write16(hw, port, XM_TX_THR, 512);
954 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
962 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
969 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
972 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
975 skge_write8(hw, B3_MA_TOINI_RX1, 72);
976 skge_write8(hw, B3_MA_TOINI_RX2, 72);
977 skge_write8(hw, B3_MA_TOINI_TX1, 72);
978 skge_write8(hw, B3_MA_TOINI_TX2, 72);
980 skge_write8(hw, B3_MA_RCINI_RX1, 0);
981 skge_write8(hw, B3_MA_RCINI_RX2, 0);
982 skge_write8(hw, B3_MA_RCINI_TX1, 0);
983 skge_write8(hw, B3_MA_RCINI_TX2, 0);
986 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
987 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
988 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
991 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
992 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
993 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
996 skge_write16(hw, B3_PA_CTRL,
1002 struct skge_hw *hw = skge->hw;
1008 cmd = xm_read16(hw, port, XM_MMU_CMD);
1010 xm_write16(hw, port, XM_MMU_CMD, cmd);
1012 genesis_reset(hw, port);
1015 skge_write16(hw, B3_PA_CTRL,
1019 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1021 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1022 if (!(skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST))
1027 if (hw->phy_type != SK_PHY_XMAC) {
1028 u32 reg = skge_read32(hw, B2_GP_IO);
1036 skge_write32(hw, B2_GP_IO, reg);
1037 skge_read32(hw, B2_GP_IO);
1040 xm_write16(hw, port, XM_MMU_CMD,
1041 xm_read16(hw, port, XM_MMU_CMD)
1044 xm_read16(hw, port, XM_MMU_CMD);
1049 struct skge_hw *hw = skge->hw;
1054 cmd = xm_read16(hw, port, XM_MMU_CMD);
1068 xm_write16(hw, port, XM_MMU_CMD, cmd);
1070 mode = xm_read32(hw, port, XM_MODE);
1084 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1087 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1096 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1099 xm_write32(hw, port, XM_MODE, mode);
1102 msk = xm_read16(hw, port, XM_IMSK);
1104 xm_write16(hw, port, XM_IMSK, msk);
1106 xm_read16(hw, port, XM_ISRC);
1109 cmd = xm_read16(hw, port, XM_MMU_CMD);
1110 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
1117 if (hw->phy_type == SK_PHY_BCOM) {
1118 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1119 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1121 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1125 xm_write16(hw, port, XM_MMU_CMD,
1133 struct skge_hw *hw = skge->hw;
1137 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1143 hw->dev[port]->name);
1149 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1150 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1152 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1157 bcom_check_link(hw, port);
1161 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1165 gma_write16(hw, port, GM_SMI_DATA, val);
1166 gma_write16(hw, port, GM_SMI_CTRL,
1167 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1171 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1176 hw->dev[port]->name,
1181 static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1185 gma_write16(hw, port, GM_SMI_CTRL,
1186 GM_SMI_CT_PHY_AD(hw->phy_addr)
1191 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1197 *val = gma_read16(hw, port, GM_SMI_DATA);
1201 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1204 if (__gm_phy_read(hw, port, reg, &v))
1206 hw->dev[port]->name,
1212 static void yukon_init(struct skge_hw *hw, int port)
1214 struct skge_port *skge = netdev_priv(hw->dev[port]);
1218 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1226 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1229 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1234 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1241 if (hw->copper) {
1287 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
1289 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1290 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1294 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
1296 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1299 static void yukon_reset(struct skge_hw *hw, int port)
1301 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1302 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1303 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1304 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1305 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
1307 gma_write16(hw, port, GM_RX_CTRL,
1308 gma_read16(hw, port, GM_RX_CTRL)
1313 static int is_yukon_lite_a0(struct skge_hw *hw)
1318 if (hw->chip_id != CHIP_ID_YUKON)
1321 reg = skge_read32(hw, B2_FAR);
1322 skge_write8(hw, B2_FAR + 3, 0xff);
1323 ret = (skge_read8(hw, B2_FAR + 3) != 0);
1324 skge_write32(hw, B2_FAR, reg);
1328 static void yukon_mac_init(struct skge_hw *hw, int port)
1330 struct skge_port *skge = netdev_priv(hw->dev[port]);
1333 const u8 *addr = hw->dev[port]->ll_addr;
1336 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1337 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1338 reg = skge_read32(hw, B2_GP_IO);
1340 skge_write32(hw, B2_GP_IO, reg);
1344 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1345 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1348 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1349 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1350 reg = skge_read32(hw, B2_GP_IO);
1353 skge_write32(hw, B2_GP_IO, reg);
1359 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
1362 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1363 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1364 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
1368 gma_write16(hw, port, GM_GP_CTRL,
1369 gma_read16(hw, port, GM_GP_CTRL) | reg);
1392 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1405 gma_write16(hw, port, GM_GP_CTRL, reg);
1406 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
1408 yukon_init(hw, port);
1411 reg = gma_read16(hw, port, GM_PHY_ADDR);
1412 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
1415 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
1416 gma_write16(hw, port, GM_PHY_ADDR, reg);
1419 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
1422 gma_write16(hw, port, GM_RX_CTRL,
1426 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
1429 gma_write16(hw, port, GM_TX_PARAM,
1439 gma_write16(hw, port, GM_SERIAL_MODE, reg);
1442 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
1444 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
1447 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
1448 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
1449 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
1454 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
1458 if (is_yukon_lite_a0(hw))
1461 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
1462 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
1468 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
1471 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1472 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
1476 static void yukon_suspend(struct skge_hw *hw, int port)
1480 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
1482 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
1484 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1486 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1489 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1491 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1496 struct skge_hw *hw = skge->hw;
1499 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1500 yukon_reset(hw, port);
1502 gma_write16(hw, port, GM_GP_CTRL,
1503 gma_read16(hw, port, GM_GP_CTRL)
1505 gma_read16(hw, port, GM_GP_CTRL);
1507 yukon_suspend(hw, port);
1510 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1511 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1514 static u16 yukon_speed(const struct skge_hw *hw __unused, u16 aux)
1528 struct skge_hw *hw = skge->hw;
1533 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1535 reg = gma_read16(hw, port, GM_GP_CTRL);
1541 gma_write16(hw, port, GM_GP_CTRL, reg);
1543 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1549 struct skge_hw *hw = skge->hw;
1553 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1555 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1558 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
1561 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
1566 yukon_init(hw, port);
1571 struct skge_hw *hw = skge->hw;
1576 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1577 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1583 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
1589 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1601 skge->speed = yukon_speed(hw, phystat);
1620 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1622 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1628 skge->speed = yukon_speed(hw, phystat);
1646 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
1654 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
1655 skge_write32(hw, RB_ADDR(q, RB_START), start);
1656 skge_write32(hw, RB_ADDR(q, RB_WP), start);
1657 skge_write32(hw, RB_ADDR(q, RB_RP), start);
1658 skge_write32(hw, RB_ADDR(q, RB_END), end);
1662 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
1664 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
1670 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
1673 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
1680 struct skge_hw *hw = skge->hw;
1685 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
1688 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
1689 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
1690 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
1691 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
1712 struct skge_hw *hw = skge->hw;
1750 if (hw->chip_id == CHIP_ID_GENESIS)
1751 genesis_mac_init(hw, port);
1753 yukon_mac_init(hw, port);
1756 chunk = (hw->ram_size - hw->ram_offset) / (hw->ports * 2);
1757 ram_addr = hw->ram_offset + 2 * chunk * port;
1759 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
1763 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
1768 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
1771 hw->intr_mask |= portmask[port];
1772 skge_write32(hw, B0_IMSK, hw->intr_mask);
1784 static void skge_rx_stop(struct skge_hw *hw, int port)
1786 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
1787 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
1789 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
1795 struct skge_hw *hw = skge->hw;
1803 hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)
1808 hw->intr_mask &= ~portmask[port];
1809 skge_write32(hw, B0_IMSK, hw->intr_mask);
1811 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
1812 if (hw->chip_id == CHIP_ID_GENESIS)
1818 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
1819 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1824 skge_write8(hw, SK_REG(port, TXA_CTRL),
1828 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1829 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1832 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
1833 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1836 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
1838 skge_rx_stop(hw, port);
1840 if (hw->chip_id == CHIP_ID_GENESIS) {
1841 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
1842 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
1844 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1845 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1868 struct skge_hw *hw = skge->hw;
1895 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
1926 static inline u16 phy_length(const struct skge_hw *hw, u32 status)
1928 if (hw->chip_id == CHIP_ID_GENESIS)
1934 static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
1936 if (hw->chip_id == CHIP_ID_GENESIS)
1950 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
2036 if ((bad_phy_status(skge->hw, rd->status)) ||
2037 (phy_length(skge->hw, rd->status) != len)) {
2058 struct skge_hw *hw = skge->hw;
2062 status = skge_read32(hw, B0_SP_ISRC);
2066 skge_phyirq(hw);
2073 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
2079 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
2081 skge_read32(hw, B0_IMSK);
2086 static void skge_phyirq(struct skge_hw *hw)
2090 for (port = 0; port < hw->ports; port++) {
2091 struct net_device *dev = hw->dev[port];
2094 if (hw->chip_id != CHIP_ID_GENESIS)
2096 else if (hw->phy_type == SK_PHY_BCOM)
2100 hw->intr_mask |= IS_EXT_REG;
2101 skge_write32(hw, B0_IMSK, hw->intr_mask);
2102 skge_read32(hw, B0_IMSK);
2115 static const char *skge_board_name(const struct skge_hw *hw)
2121 if (skge_chips[i].id == hw->chip_id)
2124 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
2133 static int skge_reset(struct skge_hw *hw)
2140 ctst = skge_read16(hw, B0_CTST);
2143 skge_write8(hw, B0_CTST, CS_RST_SET);
2144 skge_write8(hw, B0_CTST, CS_RST_CLR);
2147 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2148 skge_write8(hw, B2_TST_CTRL2, 0);
2150 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
2151 pci_write_config_word(hw->pdev, PCI_STATUS,
2153 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2154 skge_write8(hw, B0_CTST, CS_MRST_CLR);
2157 skge_write16(hw, B0_CTST,
2160 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
2161 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
2162 pmd_type = skge_read8(hw, B2_PMD_TYP);
2163 hw->copper = (pmd_type == 'T' || pmd_type == '1');
2165 switch (hw->chip_id) {
2167 switch (hw->phy_type) {
2169 hw->phy_addr = PHY_ADDR_XMAC;
2172 hw->phy_addr = PHY_ADDR_BCOM;
2176 hw->phy_type);
2184 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
2185 hw->copper = 1;
2187 hw->phy_addr = PHY_ADDR_MARV;
2192 hw->chip_id);
2196 mac_cfg = skge_read8(hw, B2_MAC_CFG);
2197 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
2198 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
2201 t8 = skge_read8(hw, B2_E_0);
2202 if (hw->chip_id == CHIP_ID_GENESIS) {
2205 hw->ram_size = 0x100000;
2206 hw->ram_offset = 0x80000;
2208 hw->ram_size = t8 * 512;
2211 hw->ram_size = 0x20000;
2213 hw->ram_size = t8 * 4096;
2215 hw->intr_mask = IS_HW_ERR;
2218 if (!(hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC))
2219 hw->intr_mask |= IS_EXT_REG;
2221 if (hw->chip_id == CHIP_ID_GENESIS)
2222 genesis_init(hw);
2225 skge_write8(hw, B0_POWER_CTRL,
2229 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
2230 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
2232 hw->intr_mask &= ~IS_HW_ERR;
2236 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2237 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®);
2239 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
2240 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2243 for (i = 0; i < hw->ports; i++) {
2244 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2245 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2250 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
2251 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2252 skge_write8(hw, B0_LED, LED_STAT_ON);
2255 for (i = 0; i < hw->ports; i++)
2256 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2259 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
2261 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
2262 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
2263 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
2264 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
2265 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
2266 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
2267 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
2268 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
2269 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
2270 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
2271 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
2272 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
2274 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
2279 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
2280 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
2281 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
2283 skge_write32(hw, B0_IMSK, hw->intr_mask);
2285 for (i = 0; i < hw->ports; i++) {
2286 if (hw->chip_id == CHIP_ID_GENESIS)
2287 genesis_reset(hw, i);
2289 yukon_reset(hw, i);
2296 static struct net_device *skge_devinit(struct skge_hw *hw, int port,
2307 dev->dev = &hw->pdev->dev;
2311 skge->hw = hw;
2318 skge->advertising = skge_supported_modes(hw);
2320 hw->dev[port] = dev;
2325 memcpy(dev->hw_addr, (void *) (hw->regs + B2_MAC_1 + port*8), ETH_ALEN);
2343 struct skge_hw *hw;
2349 hw = zalloc(sizeof(*hw));
2350 if (!hw) {
2355 hw->pdev = pdev;
2357 hw->regs = (u32)ioremap(pci_bar_start(pdev, PCI_BASE_ADDRESS_0),
2359 if (!hw->regs) {
2364 err = skge_reset(hw);
2370 skge_board_name(hw), hw->chip_rev);
2372 dev = skge_devinit(hw, 0, using_dac);
2386 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
2392 hw->dev[1] = NULL;
2397 pci_set_drvdata(pdev, hw);
2405 skge_write16(hw, B0_LED, LED_STAT_OFF);
2407 iounmap((void*)hw->regs);
2409 free(hw);
2417 struct skge_hw *hw = pci_get_drvdata(pdev);
2420 if (!hw)
2423 if ((dev1 = hw->dev[1]))
2425 dev0 = hw->dev[0];
2428 hw->intr_mask = 0;
2429 skge_write32(hw, B0_IMSK, 0);
2430 skge_read32(hw, B0_IMSK);
2432 skge_write16(hw, B0_LED, LED_STAT_OFF);
2433 skge_write8(hw, B0_CTST, CS_RST_SET);
2442 iounmap((void*)hw->regs);
2443 free(hw);
2457 struct skge_hw *hw = skge->hw;
2460 hw->intr_mask |= portmask[skge->port];
2462 hw->intr_mask &= ~portmask[skge->port];
2463 skge_write32(hw, B0_IMSK, hw->intr_mask);
