Lines Matching refs:rd
502 // ldr rd, [pc, #offset]
505 // ldr rd, [pp, #offset]
508 // ldr rd, [pp, rn]
541 // A mask for the Rd register for push, pop, ldr, str instructions.
792 // ldr<cond> <Rd>, [pc +/- offset_12].
799 // ldr<cond> <Rd>, [pp +/- offset_12].
806 // ldr<cond> <Rd>, [pp, +/- <Rm>].
1221 void Assembler::move_32_bit_immediate(Register rd,
1230 Register target = rd.code() == pc.code() ? ip : rd;
1247 if (target.code() != rd.code()) {
1248 mov(rd, target, LeaveCC, cond);
1256 Register target = rd.code() == pc.code() ? ip : rd;
1269 ldr(rd, MemOperand(pp, target), cond);
1272 ldr(rd, MemOperand(FLAG_enable_embedded_constant_pool ? pp : pc, 0),
1281 Register rd,
1293 // However, if the original instruction is a 'mov rd, x' (not setting the
1294 // condition code), then replace it with a 'ldr rd, [pc]'.
1298 move_32_bit_immediate(rd, x, cond);
1301 addrmod1(instr, rn, rd, Operand(ip));
1311 DCHECK(!rn.is(pc) && !rd.is(pc) && !x.rm_.is(pc) && !x.rs_.is(pc));
1314 emit(instr | rn.code()*B16 | rd.code()*B12);
1322 void Assembler::addrmod2(Instr instr, Register rd, const MemOperand& x) {
1334 // rn (and rd in a load) should never be ip, or will be trashed.
1335 DCHECK(!x.rn_.is(ip) && ((instr & L) == L || !rd.is(ip)));
1337 addrmod2(instr, rd, MemOperand(x.rn_, ip, x.am_));
1350 emit(instr | am | x.rn_.code()*B16 | rd.code()*B12);
1354 void Assembler::addrmod3(Instr instr, Register rd, const MemOperand& x) {
1367 // rn (and rd in a load) should never be ip, or will be trashed.
1368 DCHECK(!x.rn_.is(ip) && ((instr & L) == L || !rd.is(ip)));
1370 addrmod3(instr, rd, MemOperand(x.rn_, ip, x.am_));
1377 // rn (and rd in a load) should never be ip, or will be trashed.
1378 DCHECK(!x.rn_.is(ip) && ((instr & L) == L || !rd.is(ip)));
1381 addrmod3(instr, rd, MemOperand(x.rn_, ip, x.am_));
1389 emit(instr | am | x.rn_.code()*B16 | rd.code()*B12);
1881 // Rd(15-12) | imm5(11-7) | 0(6) | 01(5-4) | Rm(3-0)
1900 // Rd(15-12) | imm5(11-7) | 1(6) | 01(5-4) | Rm(3-0)
1917 // Rd(15-12) | rotate(11-10) | 00(9-8)| 0111(7-4) | Rm(3-0)
1930 // Rd(15-12) | rotate(11-10) | 00(9-8)| 0111(7-4) | Rm(3-0)
1943 // Rd(15-12) | rotate(11-10) | 00(9-8)| 0111(7-4) | Rm(3-0)
1956 // Rd(15-12) | rotate(11-10) | 00(9-8)| 0111(7-4) | Rm(3-0)
1969 // Rd(15-12) | rotate(11-10) | 00(9-8)| 0111(7-4) | Rm(3-0)
1982 // Rd(15-12) | rotate(11-10) | 00(9-8)| 0111(7-4) | Rm(3-0)
1995 // Rd(15-12) | rotate(11-10) | 00(9-8)| 0111(7-4) | Rm(3-0)
2007 // Rd(15-12) | rotate(11-10) | 00(9-8)| 0111(7-4) | Rm(3-0)
2020 // Rd(15-12) | rotate(11-10) | 00(9-8)| 0111(7-4) | Rm(3-0)
2032 // cond(31-28) | 011011111111(27-16) | Rd(15-12) | 11110011(11-4) | Rm(3-0)
2142 // cond(31-28) | 00011000(27-20) | Rn(19-16) | Rd(15-12) | 11111001(11-4) |
2158 // cond(31-28) | 00011100(27-20) | Rn(19-16) | Rd(15-12) | 11111001(11-4) |
2174 // cond(31-28) | 00011110(27-20) | Rn(19-16) | Rd(15-12) | 11111001(11-4) |
2331 Register rd,
2338 rd.code()*B12 | coproc*B8 | (opcode_2 & 7)*B5 | B4 | crm.code());
2341 void Assembler::mcr2(Coprocessor coproc, int opcode_1, Register rd,
2343 mcr(coproc, opcode_1, rd, crn, crm, opcode_2, kSpecialCondition);
2349 Register rd,
2356 rd.code()*B12 | coproc*B8 | (opcode_2 & 7)*B5 | B4 | crm.code());
2359 void Assembler::mrc2(Coprocessor coproc, int opcode_1, Register rd,
2361 mrc(coproc, opcode_1, rd, crn, crm, opcode_2, kSpecialCondition);
5097 // Instruction to patch must be 'vldr rd, [pc, #offset]' with offset == 0.
5135 // ldr rd, [pc, #0]
5187 // Instructions to patch must be 'movw rd, [#0]' and 'movt rd, [#0].
5196 // Instructions to patch must be 'mov rd, [#0]' and 'orr rd, rd, [#0].
5216 // Instruction to patch must be 'vldr rd, [pp, #0]'.
5222 // Instruction to patch must be 'ldr rd, [pp, #0]'.
