Lines Matching defs:Rt
280 Print("call rt redirected");
321 } else if (format[1] == 't') { // 'rt: Rt register
766 Format(instr, "ldrex'cond 'rt, ['rn]");
769 Format(instr, "ldrexb'cond 'rt, ['rn]");
772 Format(instr, "ldrexh'cond 'rt, ['rn]");
780 // The instruction is documented as strex rd, rt, [rn], but the
781 // "rt" register is using the rm bits.
1395 // vmov: Sn = Rt
1396 // vmov: Rt = Sn
1422 // Qd = vdup.size(Qd, Rt)
1423 // vmov.size: Dd[i] = Rt
1424 // vmov.sign.size: Rt = Dn[i]
1543 Format(instr, "vmov'cond.32 'Dd[0], 'rt");
1545 Format(instr, "vmov'cond.32 'Dd[1], 'rt");
1549 int rt = instr->RtValue();
1554 "vmov.8 d%d[%d], r%d", vd, i, rt);
1559 "vmov.16 d%d[%d], r%d", vd, i, rt);
1571 int Rt = instr->RtValue();
1573 "vdup.%i q%d, r%d", size, Vd, Rt);
1580 Format(instr, "vmov'cond.32 'rt, 'Dd[0]");
1582 Format(instr, "vmov'cond.32 'rt, 'Dd[1]");
1586 int rt = instr->RtValue();
1592 "vmov.%s8 r%d, d%d[%d]", sign, rt, vn, i);
1598 sign, rt, vn, i);
1610 Format(instr, "vmsr'cond FPSCR, 'rt");
1616 Format(instr, "vmrs'cond 'rt, FPSCR");
1662 Format(instr, "vmov'cond 'rt, 'Sn");
1664 Format(instr, "vmov'cond 'Sn, 'rt");
1758 // Dm = vmov(Rt, Rt2)
1759 // <Rt, Rt2> = vmov(Dm)
1807 Format(instr, "vmov'cond 'rt, 'rn, 'Dm");
1809 Format(instr, "vmov'cond 'Dm, 'rt, 'rn");
