Lines Matching defs:Rm
2101 int rm = instr->RmValue();
2104 int32_t rm_val = get_register(rm);
2110 // Format(instr, "mul'cond's 'rn, 'rm, 'rs");
2122 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the
2125 // Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd");
2130 // Format(instr, "mls'cond's 'rn, 'rm, 'rs, 'rd");
2146 // Format(instr, "'um'al'cond's 'rd, 'rn, 'rs, 'rm");
2203 // "rt" register is using the rm bits.
2210 // Format(instr, "strex'cond 'rd, 'rm, ['rn]");
2217 // Format(instr, "strexb'cond 'rd, 'rm, ['rn]");
2224 // Format(instr, "strexh'cond 'rd, 'rm, ['rn]");
2246 int rm = instr->RmValue();
2247 int32_t rm_val = get_register(rm);
2250 // Format(instr, "'memop'cond'sign'h 'rd, ['rn], -'rm");
2258 // Format(instr, "'memop'cond'sign'h 'rd, ['rn], +'rm");
2266 // Format(instr, "'memop'cond'sign'h 'rd, ['rn, -'rm]'w");
2275 // Format(instr, "'memop'cond'sign'h 'rd, ['rn, +'rm]'w");
2376 int rm = instr->RmValue();
2377 DCHECK_NE(pc, rm); // UNPREDICTABLE
2380 SetSpecialRegister(sreg_and_mask, get_register(rm));
2389 int rm = instr->RmValue();
2392 set_pc(get_register(rm));
2396 set_pc(get_register(rm));
2410 int rm = instr->RmValue();
2414 uint32_t bits = get_register(rm);
3023 int rm = instr->RmValue();
3024 int32_t rm_val = get_register(rm);
3029 // Format(instr, "smmul'cond 'rn, 'rm, 'rs");
3033 // Format(instr, "smmla'cond 'rn, 'rm, 'rs, 'rd");
3044 // (s/u)div (in V8 notation matching ARM ISA format) rn = rm/rs
3045 // Format(instr, "'(s/u)div'cond'b 'rn, 'rm, 'rs);
3046 int rm = instr->RmValue();
3047 int32_t rm_val = get_register(rm);
3715 DCHECK((mode == RN) || (mode == RM) || (mode == RZ));
3734 case RM:
3794 case RM:
3836 DCHECK((mode == RM) || (mode == RZ) || (mode == RN));
5281 int Rm = instr->VmValue();
5310 if (Rm != 15) {
5311 if (Rm == 13) {
5314 set_register(Rn, get_register(Rn) + get_register(Rm));
5322 int Rm = instr->VmValue();
5351 if (Rm != 15) {
5352 if (Rm == 13) {
5355 set_register(Rn, get_register(Rn) + get_register(Rm));
