Lines Matching refs:rd
342 Register rd;
343 rd.reg_code = (instr & kRdFieldMask) >> kRdShift;
344 return rd;
603 uint32_t rd = GetRd(instr);
613 rd == static_cast<uint32_t>(ToNumber(zero_reg)) &&
1000 Register rd,
1003 DCHECK(rd.is_valid() && rs.is_valid() && rt.is_valid() && is_uint5(sa));
1005 | (rd.code() << kRdShift) | (sa << kSaShift) | func;
1561 void Assembler::jalr(Register rs, Register rd) {
1562 DCHECK(rs.code() != rd.code());
1564 GenInstrRegister(SPECIAL, rs, zero_reg, rd, 0, JALR);
1585 void Assembler::addu(Register rd, Register rs, Register rt) {
1586 GenInstrRegister(SPECIAL, rs, rt, rd, 0, ADDU);
1590 void Assembler::addiu(Register rd, Register rs, int32_t j) {
1591 GenInstrImmediate(ADDIU, rs, rd, j);
1595 void Assembler::subu(Register rd, Register rs, Register rt) {
1596 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SUBU);
1600 void Assembler::mul(Register rd, Register rs, Register rt) {
1602 GenInstrRegister(SPECIAL, rs, rt, rd, MUL_OP, MUL_MUH);
1604 GenInstrRegister(SPECIAL2, rs, rt, rd, 0, MUL);
1609 void Assembler::muh(Register rd, Register rs, Register rt) {
1611 GenInstrRegister(SPECIAL, rs, rt, rd, MUH_OP, MUL_MUH);
1615 void Assembler::mulu(Register rd, Register rs, Register rt) {
1617 GenInstrRegister(SPECIAL, rs, rt, rd, MUL_OP, MUL_MUH_U);
1621 void Assembler::muhu(Register rd, Register rs, Register rt) {
1623 GenInstrRegister(SPECIAL, rs, rt, rd, MUH_OP, MUL_MUH_U);
1627 void Assembler::dmul(Register rd, Register rs, Register rt) {
1629 GenInstrRegister(SPECIAL, rs, rt, rd, MUL_OP, D_MUL_MUH);
1633 void Assembler::dmuh(Register rd, Register rs, Register rt) {
1635 GenInstrRegister(SPECIAL, rs, rt, rd, MUH_OP, D_MUL_MUH);
1639 void Assembler::dmulu(Register rd, Register rs, Register rt) {
1641 GenInstrRegister(SPECIAL, rs, rt, rd, MUL_OP, D_MUL_MUH_U);
1645 void Assembler::dmuhu(Register rd, Register rs, Register rt) {
1647 GenInstrRegister(SPECIAL, rs, rt, rd, MUH_OP, D_MUL_MUH_U);
1663 void Assembler::daddiu(Register rd
1664 GenInstrImmediate(DADDIU, rs, rd, j);
1673 void Assembler::div(Register rd, Register rs, Register rt) {
1675 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, DIV_MOD);
1679 void Assembler::mod(Register rd, Register rs, Register rt) {
1681 GenInstrRegister(SPECIAL, rs, rt, rd, MOD_OP, DIV_MOD);
1690 void Assembler::divu(Register rd, Register rs, Register rt) {
1692 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, DIV_MOD_U);
1696 void Assembler::modu(Register rd, Register rs, Register rt) {
1698 GenInstrRegister(SPECIAL, rs, rt, rd, MOD_OP, DIV_MOD_U);
1702 void Assembler::daddu(Register rd, Register rs, Register rt) {
1703 GenInstrRegister(SPECIAL, rs, rt, rd, 0, DADDU);
1707 void Assembler::dsubu(Register rd, Register rs, Register rt) {
1708 GenInstrRegister(SPECIAL, rs, rt, rd, 0, DSUBU);
1727 void Assembler::ddiv(Register rd, Register rs, Register rt) {
1729 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, D_DIV_MOD);
1733 void Assembler::dmod(Register rd, Register rs, Register rt) {
1735 GenInstrRegister(SPECIAL, rs, rt, rd, MOD_OP, D_DIV_MOD);
1744 void Assembler::ddivu(Register rd, Register rs, Register rt) {
1746 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, D_DIV_MOD_U);
1750 void Assembler::dmodu(Register rd, Register rs, Register rt) {
1752 GenInstrRegister(SPECIAL, rs, rt, rd, MOD_OP, D_DIV_MOD_U);
1758 void Assembler::and_(Register rd, Register rs, Register rt) {
1759 GenInstrRegister(SPECIAL, rs, rt, rd, 0, AND);
1769 void Assembler::or_(Register rd, Register rs, Register rt) {
1770 GenInstrRegister(SPECIAL, rs, rt, rd, 0, OR);
1780 void Assembler::xor_(Register rd, Register rs, Register rt) {
1781 GenInstrRegister(SPECIAL, rs, rt, rd, 0, XOR);
1791 void Assembler::nor(Register rd, Register rs, Register rt) {
1792 GenInstrRegister(SPECIAL, rs, rt, rd, 0, NOR);
1797 void Assembler::sll(Register rd,
1805 DCHECK(coming_from_nop || !(rd.is(zero_reg) && rt.is(zero_reg)));
1806 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, SLL);
1810 void Assembler::sllv(Register rd, Register rt, Register rs) {
1811 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLLV);
1815 void Assembler::srl(Register rd, Register rt, uint16_t sa) {
1816 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, SRL);
1820 void Assembler::srlv(Register rd, Register rt, Register rs) {
1821 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SRLV);
1825 void Assembler::sra(Register rd, Register rt, uint16_t sa) {
1826 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, SRA);
1830 void Assembler::srav(Register rd, Register rt, Register rs) {
1831 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SRAV);
1835 void Assembler::rotr(Register rd, Register rt, uint16_t sa) {
1837 DCHECK(rd.is_valid() && rt.is_valid() && is_uint5(sa));
1840 | (rd.code() << kRdShift) | (sa << kSaShift) | SRL;
1845 void Assembler::rotrv(Register rd, Register rt, Register rs) {
1847 DCHECK(rd.is_valid() && rt.is_valid() && rs.is_valid());
1850 | (rd.code() << kRdShift) | (1 << kSaShift) | SRLV;
1855 void Assembler::dsll(Register rd, Register rt, uint16_t sa) {
1856 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, DSLL);
1860 void Assembler::dsllv(Register rd, Register rt, Register rs) {
1861 GenInstrRegister(SPECIAL, rs, rt, rd, 0, DSLLV);
1865 void Assembler::dsrl(Register rd, Register rt, uint16_t sa) {
1866 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, DSRL);
1870 void Assembler::dsrlv(Register rd, Register rt, Register rs) {
1871 GenInstrRegister(SPECIAL, rs, rt, rd, 0, DSRLV);
1875 void Assembler::drotr(Register rd, Register rt, uint16_t sa) {
1876 DCHECK(rd.is_valid() && rt.is_valid() && is_uint5(sa));
1878 | (rd.code() << kRdShift) | (sa << kSaShift) | DSRL;
1882 void Assembler::drotr32(Register rd, Register rt, uint16_t sa) {
1883 DCHECK(rd.is_valid() && rt.is_valid() && is_uint5(sa));
1885 (rd.code() << kRdShift) | (sa << kSaShift) | DSRL32;
1889 void Assembler::drotrv(Register rd, Register rt, Register rs) {
1890 DCHECK(rd.is_valid() && rt.is_valid() && rs.is_valid() );
1892 | (rd.code() << kRdShift) | (1 << kSaShift) | DSRLV;
1897 void Assembler::dsra(Register rd, Register rt, uint16_t sa) {
1898 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, DSRA);
1902 void Assembler::dsrav(Register rd, Register rt, Register rs) {
1903 GenInstrRegister(SPECIAL, rs, rt, rd, 0, DSRAV);
1907 void Assembler::dsll32(Register rd, Register rt, uint16_t sa) {
1908 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, DSLL32);
1912 void Assembler::dsrl32(Register rd, Register rt, uint16_t sa) {
1913 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, DSRL32);
1917 void Assembler::dsra32(Register rd, Register rt, uint16_t sa) {
1918 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, DSRA32);
1922 void Assembler::lsa(Register rd, Register rt, Register rs, uint8_t sa) {
1923 DCHECK(rd.is_valid() && rt.is_valid() && rs.is_valid());
1927 rd.code() << kRdShift | sa << kSaShift | LSA;
1932 void Assembler::dlsa(Register rd, Register rt, Register rs, uint8_t sa) {
1933 DCHECK(rd.is_valid() && rt.is_valid() && rs.is_valid());
1937 rd.code() << kRdShift | sa << kSaShift | DLSA;
2000 void Assembler::lb(Register rd, const MemOperand& rs) {
2002 GenInstrImmediate(LB, rs.rm(), rd, rs.offset_);
2005 GenInstrImmediate(LB, at, rd, off16);
2010 void Assembler::lbu(Register rd, const MemOperand& rs) {
2012 GenInstrImmediate(LBU, rs.rm(), rd, rs.offset_);
2015 GenInstrImmediate(LBU, at, rd, off16);
2020 void Assembler::lh(Register rd, const MemOperand& rs) {
2022 GenInstrImmediate(LH, rs.rm(), rd, rs.offset_);
2025 GenInstrImmediate(LH, at, rd, off16);
2030 void Assembler::lhu(Register rd, const MemOperand& rs) {
2032 GenInstrImmediate(LHU, rs.rm(), rd, rs.offset_);
2035 GenInstrImmediate(LHU, at, rd, off16);
2040 void Assembler::lw(Register rd, const MemOperand& rs) {
2042 GenInstrImmediate(LW, rs.rm(), rd, rs.offset_);
2045 GenInstrImmediate(LW, at, rd, off16);
2050 void Assembler::lwu(Register rd, const MemOperand& rs) {
2052 GenInstrImmediate(LWU, rs.rm(), rd, rs.offset_);
2055 GenInstrImmediate(LWU, at, rd, off16);
2060 void Assembler::lwl(Register rd, const MemOperand& rs) {
2063 GenInstrImmediate(LWL, rs.rm(), rd, rs.offset_);
2067 void Assembler::lwr(Register rd, const MemOperand& rs) {
2070 GenInstrImmediate(LWR, rs.rm(), rd, rs.offset_);
2074 void Assembler::sb(Register rd, const MemOperand& rs) {
2076 GenInstrImmediate(SB, rs.rm(), rd, rs.offset_);
2079 GenInstrImmediate(SB, at, rd, off16);
2084 void Assembler::sh(Register rd, const MemOperand& rs) {
2086 GenInstrImmediate(SH, rs.rm(), rd, rs.offset_);
2089 GenInstrImmediate(SH, at, rd, off16);
2094 void Assembler::sw(Register rd, const MemOperand& rs) {
2096 GenInstrImmediate(SW, rs.rm(), rd, rs.offset_);
2099 GenInstrImmediate(SW, at, rd, off16);
2104 void Assembler::swl(Register rd, const MemOperand& rs) {
2107 GenInstrImmediate(SWL, rs.rm(), rd, rs.offset_);
2111 void Assembler::swr(Register rd, const MemOperand& rs) {
2114 GenInstrImmediate(SWR, rs.rm(), rd, rs.offset_);
2118 void Assembler::lui(Register rd, int32_t j) {
2120 GenInstrImmediate(LUI, zero_reg, rd, j);
2151 void Assembler::ldl(Register rd, const MemOperand& rs) {
2154 GenInstrImmediate(LDL, rs.rm(), rd, rs.offset_);
2158 void Assembler::ldr(Register rd, const MemOperand& rs) {
2161 GenInstrImmediate(LDR, rs.rm(), rd, rs.offset_);
2165 void Assembler::sdl(Register rd, const MemOperand& rs) {
2168 GenInstrImmediate(SDL, rs.rm(), rd, rs.offset_);
2172 void Assembler::sdr(Register rd, const MemOperand& rs) {
2175 GenInstrImmediate(SDR, rs.rm(), rd, rs.offset_);
2179 void Assembler::ld(Register rd, const MemOperand& rs) {
2181 GenInstrImmediate(LD, rs.rm(), rd, rs.offset_);
2184 GenInstrImmediate(LD, at, rd, off16);
2189 void Assembler::sd(Register rd, const MemOperand& rs) {
2191 GenInstrImmediate(SD, rs.rm(), rd, rs.offset_);
2194 GenInstrImmediate(SD, at, rd, off16);
2342 void Assembler::mfhi(Register rd) {
2343 GenInstrRegister(SPECIAL, zero_reg, zero_reg, rd, 0, MFHI);
2347 void Assembler::mflo(Register rd) {
2348 GenInstrRegister(SPECIAL, zero_reg, zero_reg, rd, 0, MFLO);
2353 void Assembler::slt(Register rd, Register rs, Register rt) {
2354 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLT);
2358 void Assembler::sltu(Register rd, Register rs, Register rt) {
2359 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLTU);
2374 void Assembler::movz(Register rd, Register rs, Register rt) {
2375 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVZ);
2379 void Assembler::movn(Register rd, Register rs, Register rt) {
2380 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVN);
2384 void Assembler::movt(Register rd, Register rs, uint16_t cc) {
2387 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVCI);
2391 void Assembler::movf(Register rd, Register rs, uint16_t cc) {
2394 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVCI);
2455 void Assembler::seleqz(Register rd, Register rs, Register rt) {
2457 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SELEQZ_S);
2462 void Assembler::selnez(Register rd, Register rs, Register rt) {
2464 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SELNEZ_S);
2469 void Assembler::clz(Register rd, Register rs) {
2471 // Clz instr requires same GPR number in 'rd' and 'rt' fields.
2472 GenInstrRegister(SPECIAL2, rs, rd, rd, 0, CLZ);
2474 GenInstrRegister(SPECIAL, rs, zero_reg, rd, 1, CLZ_R6);
2479 void Assembler::dclz(Register rd, Register rs) {
2481 // dclz instr requires same GPR number in 'rd' and 'rt' fields.
2482 GenInstrRegister(SPECIAL2, rs, rd, rd, 0, DCLZ);
2484 GenInstrRegister(SPECIAL, rs, zero_reg, rd, 1, DCLZ_R6);
2537 void Assembler::bitswap(Register rd, Register rt) {
2539 GenInstrRegister(SPECIAL3, zero_reg, rt, rd, 0, BSHFL);
2543 void Assembler::dbitswap(Register rd, Register rt) {
2545 GenInstrRegister(SPECIAL3, zero_reg, rt, rd, 0, DBSHFL);
2557 void Assembler::align(Register rd, Register rs, Register rt, uint8_t bp) {
2561 GenInstrRegister(SPECIAL3, rs, rt, rd, sa, BSHFL);
2565 void Assembler::dalign(Register rd, Register rs, Register rt, uint8_t bp) {
2569 GenInstrRegister(SPECIAL3, rs, rt, rd, sa, DBSHFL);
2572 void Assembler::wsbh(Register rd, Register rt) {
2574 GenInstrRegister(SPECIAL3, zero_reg, rt, rd, WSBH, BSHFL);
2577 void Assembler::dsbh(Register rd, Register rt) {
2579 GenInstrRegister(SPECIAL3, zero_reg, rt, rd, DSBH, DBSHFL);
2582 void Assembler::dshd(Register rd, Register rt) {
2584 GenInstrRegister(SPECIAL3, zero_reg, rt, rd, DSHD, DBSHFL);
2587 void Assembler::seh(Register rd, Register rt) {
2589 GenInstrRegister(SPECIAL3, zero_reg, rt, rd, SEH, BSHFL);
2592 void Assembler::seb(Register rd, Register rt) {
2594 GenInstrRegister(SPECIAL3, zero_reg, rt, rd, SEB, BSHFL);
3490 // 0: lui(rd, (j.imm64_ >> 32) & kImm16Mask);
3491 // 1: ori(rd, rd, (j.imm64_ >> 16) & kImm16Mask);
3492 // 2: dsll(rd, rd, 16);
3493 // 3: ori(rd, rd, j.imm32_ & kImm16Mask);
