Lines Matching refs:m4
1226 // RRF3 format: <insn> R1,R2,R3,M4
1228 // | OpCode | R3 | M4 | R1 | R2 |
1232 void Assembler::name(Register r3, Conition m4, Register r1, Register r2) { \
1233 rrf3_form(op << 16 | r3.code() * B12 | m4 * B8 | r1.code() * B4 | \
1239 // RRF-e format: <insn> R1,M3,R2,M4
1241 // | OpCode | M3 | M4 | R1 | R2 |
1244 void Assembler::rrfe_form(Opcode op, Condition m3, Condition m4, Register r1,
1246 uint32_t code = op << 16 | m3 * B12 | m4 * B8 | r1.code() * B4 | r2.code();
1897 void Assembler::clgdbr(Condition m3, Condition m4, Register r1,
1899 DCHECK_EQ(m4, Condition(0));
1900 rrfe_form(CLGDBR, m3, m4, r1, Register::from_code(r2.code()));
1904 void Assembler::clgebr(Condition m3, Condition m4, Register r1,
1906 DCHECK_EQ(m4, Condition(0));
1907 rrfe_form(CLGEBR, m3, m4, r1, Register::from_code(r2.code()));
1911 void Assembler::clfdbr(Condition m3, Condition m4, Register r1,
1914 DCHECK_EQ(m4, Condition(0));
1920 void Assembler::clfebr(Condition m3, Condition m4, Register r1,
1922 DCHECK_EQ(m4, Condition(0));
1927 void Assembler::celgbr(Condition m3, Condition m4, DoubleRegister r1,
1930 DCHECK_EQ(m4, Condition(0));
1936 void Assembler::celfbr(Condition m3, Condition m4, DoubleRegister r1,
1938 DCHECK_EQ(m4, Condition(0));
1943 void Assembler::cdlgbr(Condition m3, Condition m4, DoubleRegister r1,
1946 DCHECK_EQ(m4, Condition(0));
1952 void Assembler::cdlfbr(Condition m3, Condition m4, DoubleRegister r1,
1954 DCHECK_EQ(m4, Condition(0));