Lines Matching refs:fN
992 /* Generate code to set APSR.GE[flagNo]. Each fn call sets 1 bit.
15367 UInt fN = (INSN(19,16) << 1) | b7;
15377 IRExpr* res = unop(Iop_ReinterpF32asI32, getFReg(fN));
15382 DIP("fmrs%s r%u, s%u\n", nCC(conq), rD, fN);
15384 putFReg(fN, unop(Iop_ReinterpI32asF32,
15387 DIP("fmsr%s s%u, r%u\n", nCC(conq), fN, rD);
15437 UInt fN = (INSN(19,16) << 1) | bN; /* argL */
15448 triop(Iop_MulF32, rm, getFReg(fN), getFReg(fM))),
15450 DIP("fmacs%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM);
15456 triop(Iop_MulF32, rm, getFReg(fN),
15459 DIP("fnmacs%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM);
15464 triop(Iop_MulF32, rm, getFReg(fN), getFReg(fM))),
15466 DIP("fmscs%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM);
15473 getFReg(fN),
15476 DIP("fnmscs%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM);
15479 putFReg(fD, triop(Iop_MulF32, rm, getFReg(fN), getFReg(fM)),
15481 DIP("fmuls%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM);
15485 triop(Iop_MulF32, rm, getFReg(fN),
15488 DIP("fnmuls%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM);
15491 putFReg(fD, triop(Iop_AddF32, rm, getFReg(fN), getFReg(fM)),
15493 DIP("fadds%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM);
15496 putFReg(fD, triop(Iop_SubF32, rm, getFReg(fN), getFReg(fM)),
15498 DIP("fsubs%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM);
15501 putFReg(fD, triop(Iop_DivF32, rm, getFReg(fN), getFReg(fM)),
15503 DIP("fdivs%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM);
15511 getFReg(fN),
15514 DIP("vfnmss%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM);
15522 unop(Iop_NegF32, getFReg(fN)),
15525 DIP("vfnmas%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM);
15532 triop(Iop_MulF32, rm, getFReg(fN),
15535 DIP("vfmas%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM);
15543 unop(Iop_NegF32, getFReg(fN)),
15546 DIP("vfmss%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM);
15901 assert that we aren't accepting, in this fn, insns that actually
23589 /*--- Top-level fn ---*/
