Lines Matching refs:vHi
1629 HReg vHi, vLo, vec;
1630 iselDVecExpr(&vHi, &vLo, env, e->Iex.Unop.arg);
1638 case Iop_V256to64_2: vec = vHi; off = -16; break;
1639 case Iop_V256to64_3: vec = vHi; off = -8; break;
3293 HReg vHi, vLo;
3294 iselDVecExpr(&vHi, &vLo, env, e->Iex.Unop.arg);
3295 return (e->Iex.Unop.op == Iop_V256toV128_1) ? vHi : vLo;
3753 HReg vHi = newVRegV(env);
3759 addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, vHi, am16));
3760 *rHi = vHi;
3766 HReg vHi = newVRegV(env);
3772 addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, vHi, am16));
3773 *rHi = vHi;
3782 HReg vHi = generate_zeroes_V128(env);
3784 addInstr(env, mk_vMOVsd_RR(vHi, vLo));
3785 *rHi = vHi;
4232 HReg vHi = newVRegV(env);
4245 addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, vHi, m16_rsp));
4250 *rHi = vHi;
4409 HReg vHi, vLo;
4410 iselDVecExpr(&vHi, &vLo, env, stmt->Ist.Store.data);
4412 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 16, vHi, am16));
4465 HReg vHi, vLo;
4466 iselDVecExpr(&vHi, &vLo, env, stmt->Ist.Put.data);
4471 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 16, vHi, am16));
