Lines Matching refs:nArgRegs
1218 ARMInstr* ARMInstr_Call ( ARMCondCode cond, Addr32 target, Int nArgRegs,
1224 i->ARMin.Call.nArgRegs = nArgRegs;
1719 vex_printf("0x%x [nArgRegs=%d, ",
1720 i->ARMin.Call.target, i->ARMin.Call.nArgRegs);
2179 which might be read. This depends on nArgRegs. */
2180 switch (i->ARMin.Call.nArgRegs) {
2190 loaded into a register. Fortunately, for the nArgRegs=
2193 nArgRegs=4 case, we'll have to choose another register
2197 if (i->ARMin.Call.nArgRegs == 4)
2201 address temporary, depending on nArgRegs: 0==r0,
3486 switch (i->ARMin.Call.nArgRegs) {
