Lines Matching defs:arg1
1472 HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
1505 HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
1554 HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
1572 HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
1594 HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
1609 HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
1629 HReg srcL = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
1644 HReg srcL = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
1657 HReg r1 = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
1669 HReg r_Hi = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
1701 fr_srcL = iselDblExpr(env, e->Iex.Binop.arg1, IEndianess);
1706 fr_srcL = iselDfp64Expr(env, e->Iex.Binop.arg1, IEndianess);
1711 iselDfp128Expr(&fr_srcL, &fr_srcL_lo, env, e->Iex.Binop.arg1,
1776 set_FPU_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
1808 set_FPU_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
1833 set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
1854 set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
2648 iselWordExpr_R(env, e->Iex.Binop.arg1,
2655 HReg r_base = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
2672 iselWordExpr_R(env, e->Iex.Binop.arg1,
2679 HReg r_base = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
2997 HReg r1 = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
3046 HReg r1 = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
3069 HReg arg = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
3160 HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
3175 *rHi = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
3241 iselInt64Expr(rHi, rMedHi, env, e->Iex.Binop.arg1, IEndianess);
3393 HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1,
3417 iselInt64Expr(&xHi, &xLo, env, e->Iex.Binop.arg1, IEndianess);
3431 iselInt64Expr(&xHi, &xLo, env, e->Iex.Binop.arg1, IEndianess);
3444 *rHi = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
3461 set_FPU_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
3488 set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
3510 set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
3994 set_FPU_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
4020 set_FPU_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
4165 set_FPU_rounding_mode( env, e->Iex.Qop.details->arg1, IEndianess );
4190 set_FPU_rounding_mode( env, triop->arg1, IEndianess );
4205 set_FPU_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
4221 if (FPU_rounding_mode_isOdd(e->Iex.Binop.arg1)) {
4225 set_FPU_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
4251 set_FPU_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
4265 set_FPU_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
4293 set_FPU_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
4483 set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
4610 HReg r_src_hi = iselDblExpr(env, e->Iex.Binop.arg1, IEndianess);
4640 PPCRI* rm = iselWordExpr_RI(env, e->Iex.Binop.arg1, IEndianess);
4652 PPCRI* rm = iselWordExpr_RI(env, e->Iex.Binop.arg1, IEndianess);
4661 if (FPU_rounding_mode_isOdd(e->Iex.Binop.arg1)) {
4666 set_FPU_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
4671 if (FPU_rounding_mode_isOdd(e->Iex.Binop.arg1)) {
4676 set_FPU_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
4697 if (FPU_rounding_mode_isOdd(triop->arg1)) {
4701 set_FPU_rounding_mode( env, triop->arg1, IEndianess );
4705 if (FPU_rounding_mode_isOdd(triop->arg1)) {
4709 set_FPU_rounding_mode( env, triop->arg1, IEndianess );
4713 if (FPU_rounding_mode_isOdd(triop->arg1)) {
4717 set_FPU_rounding_mode( env, triop->arg1, IEndianess );
4721 if (FPU_rounding_mode_isOdd(triop->arg1)) {
4725 set_FPU_rounding_mode( env, triop->arg1, IEndianess );
4729 if (FPU_rounding_mode_isOdd(triop->arg1)) {
4733 set_FPU_rounding_mode( env, triop->arg1, IEndianess );
4757 if (FPU_rounding_mode_isOdd(qop->arg1)) {
4761 set_FPU_rounding_mode( env, qop->arg1, IEndianess );
4765 if (FPU_rounding_mode_isOdd(qop->arg1)) {
4769 set_FPU_rounding_mode( env, qop->arg1, IEndianess );
4773 if (FPU_rounding_mode_isOdd(qop->arg1)) {
4777 set_FPU_rounding_mode( env, qop->arg1, IEndianess );
4781 if (FPU_rounding_mode_isOdd(qop->arg1)) {
4785 set_FPU_rounding_mode( env, qop->arg1, IEndianess );
4888 HReg fr_srcL = iselDblExpr(env, e->Iex.Binop.arg1, IEndianess);
4916 set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
4924 PPCRI* r_rmc = iselWordExpr_RI(env, e->Iex.Binop.arg1, IEndianess);
4937 set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
4945 set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
4976 HReg fr_src = iselDfp64Expr(env, e->Iex.Binop.arg1, IEndianess);
5000 HReg tmp = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
5009 iselInt64Expr(&tmpHi, &tmpLo, env, e->Iex.Binop.arg1,
5047 set_FPU_DFP_rounding_mode( env, triop->arg1, IEndianess );
5061 PPCRI* rmc = iselWordExpr_RI(env, triop->arg1, IEndianess);
5070 PPCRI* rmc = iselWordExpr_RI(env, triop->arg1, IEndianess);
5164 r_srcHi = iselDfp64Expr( env, e->Iex.Binop.arg1, IEndianess );
5174 set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
5193 iselDfp128Expr(&r_srcHi, &r_srcLo, env, e->Iex.Binop.arg1,
5209 PPCRI* r_rmc = iselWordExpr_RI(env, e->Iex.Binop.arg1, IEndianess);
5234 HReg tmp = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
5291 set_FPU_DFP_rounding_mode( env, triop->arg1, IEndianess );
5307 PPCRI* rmc = iselWordExpr_RI(env, triop->arg1, IEndianess);
5323 PPCRI* rmc = iselWordExpr_RI(env, triop->arg1, IEndianess);
5742 iselInt64Expr(&r3, &r2, env, e->Iex.Binop.arg1, IEndianess);
5752 HReg rHi = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
5788 HReg argL = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
5796 HReg argL = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
5821 HReg arg1 = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
5824 addInstr(env, PPCInstr_AvBinary(op, dst, arg1, arg2));
5853 HReg arg1 = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
5856 addInstr(env, PPCInstr_AvBin8x16(op, dst, arg1, arg2));
5888 HReg arg1 = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
5891 addInstr(env, PPCInstr_AvBin16x8(op, dst, arg1, arg2));
5926 HReg arg1 = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
5929 addInstr(env, PPCInstr_AvBin32x4(op, dst, arg1, arg2));
5953 HReg arg1 = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
5956 addInstr(env, PPCInstr_AvBin64x2(op, dst, arg1, arg2));
5963 HReg r_src = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
5974 HReg r_src = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
5985 HReg r_src = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
5996 HReg r_src = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
6007 HReg r_src = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
6016 HReg v_src = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
6027 HReg arg1 = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
6030 addInstr(env, PPCInstr_AvCipherV128Binary(op, dst, arg1, arg2));
6037 HReg arg1 = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
6040 addInstr(env, PPCInstr_AvHashV128Binary(op, dst, arg1, s_field));
6048 HReg arg = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
6060 HReg argL = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
6069 HReg arg1 = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
6072 addInstr(env, PPCInstr_AvBCDV128Binary(op, dst, arg1, arg2));
6098 set_FPU_rounding_mode(env, triop->arg1, IEndianess);
