Lines Matching defs:LL
94 static cache_t2 I1, D1, LL;
234 * Model: single inclusive, 2-level cache hierarchy (L1/LL)
319 if ( cachesim_ref( &LL, a, size) == Hit ) return LL_Hit;
327 if ( cachesim_ref( &LL, a, size) == Hit ) return LL_Hit;
337 * More complex model: L1 Write-through, LL Write-back
427 switch( cachesim_ref_wb( &LL, Read, a, size) ) {
439 switch( cachesim_ref_wb( &LL, Read, a, size) ) {
452 * the write to the LL to make the LL line dirty.
455 cachesim_ref_wb( &LL, Write, a, size);
458 switch( cachesim_ref_wb( &LL, Write, a, size) ) {
497 UInt block = ( a >> LL.line_size_bits);
509 cachesim_ref(&LL, a + 5 * LL.line_size,1);
519 cachesim_ref(&LL, a - 5 * LL.line_size,1);
535 if ( cachesim_ref( &LL, a, size) == Hit ) return LL_Hit;
544 if ( cachesim_ref( &LL, a, size) == Hit ) return LL_Hit;
556 switch( cachesim_ref_wb( &LL, Read, a, size) ) {
569 switch( cachesim_ref_wb( &LL, Read, a, size) ) {
583 * the write to the LL to make the LL line dirty.
586 cachesim_ref_wb( &LL, Write, a, size);
589 switch( cachesim_ref_wb( &LL, Write, a, size) ) {
751 Int miss1=0, miss2=0; /* 0: L1 hit, 1:L1 miss, 2:LL miss */ \
854 line_loaded* loaded = &(LL.loaded[idx]);
855 line_use* use = &(LL.use[idx]);
856 int i = ((32 - countBits(use->mask)) * LL.line_size)>>5;
858 CLG_DEBUG(2, " LL.miss [%d]: at %#lx accessing memline %#lx\n",
885 UInt setNo = (memline >> LL.line_size_bits) & (LL.sets_min_1);
886 UWord* set = &(LL.tags[setNo * LL.assoc]);
887 UWord tag = memline & LL.tag_mask;
892 CLG_DEBUG(6,"LL.Acc(Memline %#lx): Set %u\n", memline, setNo);
894 if (tag == (set[0] & LL.tag_mask)) {
895 idx = (setNo * LL.assoc) + (set[0] & ~LL.tag_mask);
896 l1_loaded->dep_use = &(LL.use[idx]);
899 idx, LL.loaded[idx].memline, LL.loaded[idx].iaddr,
900 LL.use[idx].mask, LL.use[idx].count);
903 for (i = 1; i < LL.assoc; i++) {
904 if (tag == (set[i] & LL.tag_mask)) {
910 idx = (setNo * LL.assoc) + (tmp_tag & ~LL.tag_mask);
911 l1_loaded->dep_use = &(LL.use[idx]);
914 i, idx, LL.loaded[idx].memline, LL.loaded[idx].iaddr,
915 LL.use[idx].mask, LL.use[idx].count);
921 tmp_tag = set[LL.assoc - 1] & ~LL.tag_mask;
922 for (j = LL.assoc - 1; j > 0; j--) {
926 idx = (setNo * LL.assoc) + tmp_tag;
927 l1_loaded->dep_use = &(LL.use[idx]);
958 /* FIXME (?): L1/LL line sizes must be equal ! */ \
1006 if (LL.use)
1007 for (i = 0; i < LL.sets * LL.assoc; i++)
1008 if (LL.loaded[i].use_base)
1053 case LL_Hit: return "LL Hit ";
1054 case MemAccess: return "LL Miss";
1055 case WriteBackMemAccess: return "LL Miss (dirty)";
1324 LL.name = "LL";
1350 cachesim_initcache(LLc, &LL);
1431 cachesim_clearcache(&LL);
1441 VG_(fprintf)(fp, "desc: LL cache: %s\n", LL.desc_line);
1561 /* LL overall results */
1571 VG_(message)(Vg_UserMsg, "LL refs: %'*llu (%'*llu rd + %'*llu wr)\n",
1582 VG_(message)(Vg_UserMsg, "LL misses: %'*llu (%'*llu rd + %'*llu wr)\n",
1585 VG_(message)(Vg_UserMsg, "LL miss rate: %*.1f%% (%*.1f%% + %*.1f%% )\n",
