Lines Matching full:accesses
75 runtime, as it masks accesses to main memory. Furthermore, the L1 caches
107 <p>Note that D1 total accesses is given by
110 accesses is given by <code class="computeroutput">ILmr</code> +
167 <p>Cache accesses for instruction fetches are summarised
172 <p>Cache accesses for data follow. The information is similar
180 number of memory accesses, not the number of L1 misses. I.e. it is
