Cross Reference: /external/vixl/src/aarch32/assembler-aarch32.cc

Lines Matching refs:rd
1776 // ADR{<c>}{<q>} <Rd>, <label> ; T1
1806 // ADR{<c>}{<q>} <Rd>, <label> ; T3
1862 // ADR{<c>}{<q>} <Rd>, <label> ; A1
1910                     Register rd,
1919       // ADC{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T1
1921           ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
1922         EmitT32_32(0xf1400000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
1931       // ADC{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
1934                 (rd.GetCode() << 12) | (rn.GetCode() << 16) |
1945         if (InITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() &&
1947           EmitT32_16(0x4140 | rd.GetCode() | (rm.GetCode() << 3));
1956       // ADC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
1958           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
1960         EmitT32_32(0xeb400000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
1967       // ADC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
1971                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
1982       // ADC{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
1984           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
1987                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
1993   Delegate(kAdc, &Assembler::adc, cond, size, rd, rn, operand);
1998                      Register rd,
2007       // ADCS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T1
2009           ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
2010         EmitT32_32(0xf1500000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
2019       // ADCS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
2022                 (rd.GetCode() << 12) | (rn.GetCode() << 16) |
2033         if (OutsideITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() &&
2035           EmitT32_16(0x4140 | rd.GetCode() | (rm.GetCode() << 3));
2044       // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
2046           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
2048         EmitT32_32(0xeb500000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
2055       // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
2059                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
2070       // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
2072           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
2075                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
2081   Delegate(kAdcs, &Assembler::adcs, cond, size, rd, rn, operand);
2086                     Register rd,
2095       // ADD{<c>}{<q>} <Rd>, PC, #<imm8> ; T1
2096       if (!size.IsWide() && rd.IsLow() && rn.Is(pc) && (imm <= 1020) &&
2099         EmitT32_16(0xa000 | (rd.GetCode() << 8) | imm_);
2103       // ADD<c>{<q>} <Rd>, <Rn>, #<imm3> ; T1
2104       if (InITBlock() && !size.IsWide() && rd.IsLow() && rn.IsLow() &&
2106         EmitT32_16(0x1c00 | rd.GetCode() | (rn.GetCode() << 3) | (imm << 6));
2111       if (InITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() &&
2113         EmitT32_16(0x3000 | (rd.GetCode() << 8) | imm);
2117       // ADD{<c>}{<q>} <Rd>, SP, #<imm8> ; T1
2118       if (!size.IsWide() && rd.IsLow() && rn.Is(sp) && (imm <= 1020) &&
2121         EmitT32_16(0xa800 | (rd.GetCode() << 8) | imm_);
2126       if (!size.IsWide() && rd.Is(sp) && rn.Is(sp) && (imm <= 508) &&
2133       // ADD{<c>}{<q>} <Rd>, PC, #<imm12> ; T3
2135           (!rd.IsPC() || AllowUnpredictable())) {
2136         EmitT32_32(0xf20f0000U | (rd.GetCode() << 8) | (imm & 0xff) |
2141       // ADD{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T3
2143           ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
2144         EmitT32_32(0xf1000000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
2151       // ADD{<c>}{<q>} {<Rd>}, <Rn>, #<imm12> ; T4
2153           (!rd.IsPC() || AllowUnpredictable())) {
2154         EmitT32_32(0xf2000000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
2159       // ADD{<c>}{<q>} {<Rd>}, SP, #<const> ; T3
2161           (!rd.IsPC() || AllowUnpredictable())) {
2162         EmitT32_32(0xf10d0000U | (rd.GetCode() << 8) |
2169       // ADD{<c>}{<q>} {<Rd>}, SP, #<imm12> ; T4
2171           (!rd.IsPC() || AllowUnpredictable())) {
2172         EmitT32_32(0xf20d0000U | (rd.GetCode() << 8) | (imm & 0xff) |
2179       // ADD{<c>}{<q>} <Rd>, PC, #<const> ; A1
2182                 (rd.GetCode() << 12) | immediate_a32.GetEncodingValue());
2185       // ADD{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
2189                 (rd.GetCode() << 12) | (rn.GetCode() << 16) |
2193       // ADD{<c>}{<q>} {<Rd>}, SP, #<const> ; A1
2196                 (rd.GetCode() << 12) | immediate_a32.GetEncodingValue());
2205         // ADD<c>{<q>} <Rd>, <Rn>, <Rm> ; T1
2206         if (InITBlock() && !size.IsWide() && rd.IsLow() && rn.IsLow() &&
2208           EmitT32_16(0x1800 | rd.GetCode() | (rn.GetCode() << 3) |
2214         if (!size.IsWide() && rd.Is(rn) && !rm.Is(sp) &&
2215             (((!rd.IsPC() || OutsideITBlockAndAlOrLast(cond)) &&
2216               (!rd.IsPC() || !rm.IsPC())) ||
2218           EmitT32_16(0x4400 | (rd.GetCode() & 0x7) |
2219                      ((rd.GetCode() & 0x8) << 4) | (rm.GetCode() << 3));
2224         if (!size.IsWide() && rd.Is(rm) && rn.Is(sp) &&
2225             ((!rd.IsPC() || OutsideITBlockAndAlOrLast(cond)) ||
2227           EmitT32_16(0x4468 | (rd.GetCode() & 0x7) |
2228                      ((rd.GetCode() & 0x8) << 4));
2233         if (!size.IsWide() && rd.Is(sp) && rn.Is(sp) && !rm.Is(sp)) {
2243       // ADD{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T3
2245           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
2247         EmitT32_32(0xeb000000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
2253       // ADD{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T3
2255           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
2257         EmitT32_32(0xeb0d0000U | (rd.GetCode() << 8) | rm.GetCode() |
2264       // ADD{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
2268                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
2272       // ADD{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; A1
2276                 (rd.GetCode() << 12) | rm.GetCode() |
2287       // ADD{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
2289           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
2292                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
2298   Delegate(kAdd, &Assembler::add, cond, size, rd, rn, operand);
2301 void Assembler::add(Condition cond, Register rd, const Operand& operand) {
2308       if (InITBlock() && rd.IsLow() && (imm <= 255)) {
2309         EmitT32_16(0x3000 | (rd.GetCode() << 8) | imm);
2320           (((!rd.IsPC() || OutsideITBlockAndAlOrLast(cond)) &&
2321             (!rd.IsPC() || !rm.IsPC())) ||
2323         EmitT32_16(0x4400 | (rd.GetCode() & 0x7) | ((rd.GetCode() & 0x8) << 4) |
2330   Delegate(kAdd, &Assembler::add, cond, rd, operand);
2335                      Register rd,
2344       // ADDS{<q>} <Rd>, <Rn>, #<imm3> ; T1
2345       if (OutsideITBlock() && !size.IsWide() && rd.IsLow() && rn.IsLow() &&
2347         EmitT32_16(0x1c00 | rd.GetCode() | (rn.GetCode() << 3) | (imm << 6));
2352       if (OutsideITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() &&
2354         EmitT32_16(0x3000 | (rd.GetCode() << 8) | imm);
2358       // ADDS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T3
2360           !rd.Is(pc) && (!rn.IsPC() || AllowUnpredictable())) {
2361         EmitT32_32(0xf1100000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
2368       // ADDS{<c>}{<q>} {<Rd>}, SP, #<const> ; T3
2370           !rd.Is(pc)) {
2371         EmitT32_32(0xf11d0000U | (rd.GetCode() << 8) |
2380       // ADDS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
2383                 (rd.GetCode() << 12) | (rn.GetCode() << 16) |
2387       // ADDS{<c>}{<q>} {<Rd>}, SP, #<const> ; A1
2390                 (rd.GetCode() << 12) | immediate_a32.GetEncodingValue());
2399         // ADDS{<q>} {<Rd>}, <Rn>, <Rm> ; T1
2400         if (OutsideITBlock() && !size.IsWide() && rd.IsLow() && rn.IsLow() &&
2402           EmitT32_16(0x1800 | rd.GetCode() | (rn.GetCode() << 3) |
2412       // ADDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T3
2414           !rd.Is(pc) && ((!rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
2416         EmitT32_32(0xeb100000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
2422       // ADDS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T3
2424           !rd.Is(pc) && (!rm.IsPC() || AllowUnpredictable())) {
2426         EmitT32_32(0xeb1d0000U | (rd.GetCode() << 8) | rm.GetCode() |
2433       // ADDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
2437                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
2441       // ADDS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; A1
2445                 (rd.GetCode() << 12) | rm.GetCode() |
2456       // ADDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
2458           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
2461                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
2467   Delegate(kAdds, &Assembler::adds, cond, size, rd, rn, operand);
2470 void Assembler::adds(Register rd, const Operand& operand) {
2477       if (OutsideITBlock() && rd.IsLow() && (imm <= 255)) {
2478         EmitT32_16(0x3000 | (rd.GetCode() << 8) | imm);
2484   Delegate(kAdds, &Assembler::adds, rd, operand);
2488                      Register rd,
2496       // ADDW{<c>}{<q>} <Rd>, PC, #<imm12> ; T3
2497       if (rn.Is(pc) && (imm <= 4095) && (!rd.IsPC() || AllowUnpredictable())) {
2498         EmitT32_32(0xf20f0000U | (rd.GetCode() << 8) | (imm & 0xff) |
2503       // ADDW{<c>}{<q>} {<Rd
2505           (!rd.IsPC() || AllowUnpredictable())) {
2506         EmitT32_32(0xf2000000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
2511       // ADDW{<c>}{<q>} {<Rd>}, SP, #<imm12> ; T4
2512       if (rn.Is(sp) && (imm <= 4095) && (!rd.IsPC() || AllowUnpredictable())) {
2513         EmitT32_32(0xf20d0000U | (rd.GetCode() << 8) | (imm & 0xff) |
2520   Delegate(kAddw, &Assembler::addw, cond, rd, rn, operand);
2525                     Register rd,
2536     // ADR{<c>}{<q>} <Rd>, <label> ; T1
2537     if (!size.IsWide() && rd.IsLow() &&
2556           Link(0xa000 | (rd.GetCode() << 8), location, immop, &kT16DataInfo));
2560     // ADR{<c>}{<q>} <Rd>, <label> ; T2
2562         (neg_offset <= 4095) && (!rd.IsPC() || AllowUnpredictable())) {
2563       EmitT32_32(0xf2af0000U | (rd.GetCode() << 8) | (neg_offset & 0xff) |
2568     // ADR{<c>}{<q>} <Rd>, <label> ; T3
2571         (!rd.IsPC() || AllowUnpredictable())) {
2593       EmitT32_32(Link(0xf20f0000U | (rd.GetCode() << 8),
2603     // ADR{<c>}{<q>} <Rd>, <label> ; A1
2629           Link(0x028f0000U | (cond.GetCondition() << 28) | (rd.GetCode() << 12),
2635     // ADR{<c>}{<q>} <Rd>, <label> ; A2
2638       EmitA32(0x024f0000U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
2643   Delegate(kAdr, &Assembler::adr, cond, size, rd, location);
2648                          Register rd,
2654     // ADR{<c>}{<q>} <Rd>, <label> ; T1
2655     if (!size.IsWide() && rd.IsLow() && size.IsNarrow()) {
2662     // ADR{<c>}{<q>} <Rd>, <label> ; T3
2668     // ADR{<c>}{<q>} <Rd>, <label> ; A1
2682                      Register rd,
2691       // AND{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T1
2693           ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
2694         EmitT32_32(0xf0000000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
2703       // AND{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
2706                 (rd.GetCode() << 12) | (rn.GetCode() << 16) |
2717         if (InITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() &&
2719           EmitT32_16(0x4000 | rd.GetCode() | (rm.GetCode() << 3));
2728       // AND{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
2730           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
2732         EmitT32_32(0xea000000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
2739       // AND{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
2743                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
2754       // AND{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
2756           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
2759                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
2765   Delegate(kAnd, &Assembler::and_, cond, size, rd, rn, operand);
2770                      Register rd,
2779       // ANDS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T1
2780       if (!size.IsNarrow() && immediate_t32.IsValid() && !rd.Is(pc) &&
2782         EmitT32_32(0xf0100000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
2791       // ANDS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
2794                 (rd.GetCode() << 12) | (rn.GetCode() << 16) |
2805         if (OutsideITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() &&
2807           EmitT32_16(0x4000 | rd.GetCode() | (rm.GetCode() << 3));
2816       // ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
2817       if (!size.IsNarrow() && shift.IsValidAmount(amount) && !rd.Is(pc) &&
2820         EmitT32_32(0xea100000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
2827       // ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
2831                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
2842       // ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
2844           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
2847                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
2853   Delegate(kAnds, &Assembler::ands, cond, size, rd, rn, operand);
2858                     Register rd,
2866       // ASR<c>{<q>} {<Rd>}, <Rm>, #<imm> ; T2
2867       if (InITBlock() && !size.IsWide() && rd.IsLow() && rm.IsLow() &&
2870         EmitT32_16(0x1000 | rd.GetCode() | (rm.GetCode() << 3) |
2875       // ASR{<c>}{<q>} {<Rd>}, <Rm>, #<imm> ; T3
2877           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
2879         EmitT32_32(0xea4f0020U | (rd.GetCode() << 8) | rm.GetCode() |
2885       // ASR{<c>}{<q>} {<Rd>}, <Rm>, #<imm> ; A1
2889                 (rd.GetCode() << 12) | rm.GetCode() | (amount_ << 7));
2898       if (InITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&
2900         EmitT32_16(0x4100 | rd.GetCode() | (rs.GetCode() << 3));
2904       // ASR{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; T2
2906           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
2907         EmitT32_32(0xfa40f000U | (rd.GetCode() << 8) | (rm.GetCode() << 16) |
2913       // ASR{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; A1
2915           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
2917                 (rd.GetCode() << 12) | rm.GetCode() | (rs.GetCode() << 8));
2922   Delegate(kAsr, &Assembler::asr, cond, size, rd, rm, operand);
2927                      Register rd,
2935       // ASRS{<q>} {<Rd>}, <Rm>, #<imm> ; T2
2936       if (OutsideITBlock() && !size.IsWide() && rd
2939         EmitT32_16(0x1000 | rd.GetCode() | (rm.GetCode() << 3) |
2944       // ASRS{<c>}{<q>} {<Rd>}, <Rm>, #<imm> ; T3
2946           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
2948         EmitT32_32(0xea5f0020U | (rd.GetCode() << 8) | rm.GetCode() |
2954       // ASRS{<c>}{<q>} {<Rd>}, <Rm>, #<imm> ; A1
2958                 (rd.GetCode() << 12) | rm.GetCode() | (amount_ << 7));
2967       if (OutsideITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&
2969         EmitT32_16(0x4100 | rd.GetCode() | (rs.GetCode() << 3));
2973       // ASRS{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; T2
2975           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
2976         EmitT32_32(0xfa50f000U | (rd.GetCode() << 8) | (rm.GetCode() << 16) |
2982       // ASRS{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; A1
2984           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
2986                 (rd.GetCode() << 12) | rm.GetCode() | (rs.GetCode() << 8));
2991   Delegate(kAsrs, &Assembler::asrs, cond, size, rd, rm, operand);
3179 void Assembler::bfc(Condition cond, Register rd, uint32_t lsb, uint32_t width) {
3183     // BFC{<c>}{<q>} <Rd>, #<lsb>, #<width> ; T1
3184     if ((lsb <= 31) && (((width >= 1) && (width <= 32 - lsb) && !rd.IsPC()) ||
3187       EmitT32_32(0xf36f0000U | (rd.GetCode() << 8) | ((lsb & 0x3) << 6) |
3193     // BFC{<c>}{<q>} <Rd>, #<lsb>, #<width> ; A1
3195         (((width >= 1) && (width <= 32 - lsb) && !rd.IsPC()) ||
3198       EmitA32(0x07c0001fU | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
3203   Delegate(kBfc, &Assembler::bfc, cond, rd, lsb, width);
3207     Condition cond, Register rd, Register rn, uint32_t lsb, uint32_t width) {
3211     // BFI{<c>}{<q>} <Rd>, <Rn>, #<lsb>, #<width> ; T1
3213         (((width >= 1) && (width <= 32 - lsb) && !rd.IsPC()) ||
3216       EmitT32_32(0xf3600000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
3222     // BFI{<c>}{<q>} <Rd>, <Rn>, #<lsb>, #<width> ; A1
3224         (((width >= 1) && (width <= 32 - lsb) && !rd.IsPC()) ||
3227       EmitA32(0x07c00010U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
3232   Delegate(kBfi, &Assembler::bfi, cond, rd, rn, lsb, width);
3237                     Register rd,
3246       // BIC{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T1
3248           ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
3249         EmitT32_32(0xf0200000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
3258       // BIC{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
3261                 (rd.GetCode() << 12) | (rn.GetCode() << 16) |
3272         if (InITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() &&
3274           EmitT32_16(0x4380 | rd.GetCode() | (rm.GetCode() << 3));
3283       // BIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
3285           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
3287         EmitT32_32(0xea200000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
3294       // BIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
3298                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
3309       // BIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
3311           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
3314                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
3320   Delegate(kBic, &Assembler::bic, cond, size, rd, rn, operand);
3325                      Register rd,
3334       // BICS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T1
3336           ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
3337         EmitT32_32(0xf0300000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
3346       // BICS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
3349                 (rd.GetCode() << 12) | (rn.GetCode() << 16) |
3360         if (OutsideITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() &&
3362           EmitT32_16(0x4380 | rd.GetCode() | (rm.GetCode() << 3));
3371       // BICS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
3373           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
3375         EmitT32_32(0xea300000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
3382       // BICS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
3386                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
3397       // BICS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
3399           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
3402                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
3408   Delegate(kBics, &Assembler::bics, cond, size, rd, rn, operand);
3787 void Assembler::clz(Condition cond, Register rd, Register rm) {
3791     // CLZ{<c>}{<q>} <Rd>, <Rm> ; T1
3792     if (((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
3793       EmitT32_32(0xfab0f080U | (rd.GetCode() << 8) | rm.GetCode() |
3799     // CLZ{<c>}{<q>} <Rd>, <Rm> ; A1
3801         ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
3802       EmitA32(0x016f0f10U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
3807   Delegate(kClz, &Assembler::clz, cond, rd, rm);
3992 void Assembler::crc32b(Condition cond, Register rd, Register rn, Register rm) {
3996     // CRC32B{<q>} <Rd>, <Rn>, <Rm> ; T1
3997     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && OutsideITBlock()) ||
3999       EmitT32_32(0xfac0f080U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
4005     // CRC32B{<q>} <Rd>, <Rn>, <Rm> ; A1
4007         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
4008       EmitA32(0x01000040U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
4013   Delegate(kCrc32b, &Assembler::crc32b, cond, rd, rn, rm);
4016 void Assembler::crc32cb(Condition cond, Register rd, Register rn, Register rm) {
4020     // CRC32CB{<q>} <Rd>, <Rn>, <Rm> ; T1
4021     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && OutsideITBlock()) ||
4023       EmitT32_32(0xfad0f080U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
4029     // CRC32CB{<q>} <Rd>, <Rn>, <Rm> ; A1
4031         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
4032       EmitA32(0x01000240U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
4037   Delegate(kCrc32cb, &Assembler::crc32cb, cond, rd, rn, rm);
4040 void Assembler::crc32ch(Condition cond, Register rd, Register rn, Register rm) {
4044     // CRC32CH{<q>} <Rd>, <Rn>, <Rm> ; T1
4045     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && OutsideITBlock()) ||
4047       EmitT32_32(0xfad0f090U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
4053     // CRC32CH{<q>} <Rd>, <Rn>, <Rm> ; A1
4055         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
4056       EmitA32(0x01200240U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
4061   Delegate(kCrc32ch, &Assembler::crc32ch, cond, rd, rn, rm);
4064 void Assembler::crc32cw(Condition cond, Register rd, Register rn, Register rm) {
4068     // CRC32CW{<q>} <Rd>, <Rn>, <Rm> ; T1
4069     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && OutsideITBlock()) ||
4071       EmitT32_32(0xfad0f0a0U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
4077     // CRC32CW{<q>} <Rd>, <Rn>, <Rm> ; A1
4079         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
4080       EmitA32(0x01400240U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
4085   Delegate(kCrc32cw, &Assembler::crc32cw, cond, rd, rn, rm);
4088 void Assembler::crc32h(Condition cond, Register rd, Register rn, Register rm) {
4092     // CRC32H{<q>} <Rd>, <Rn>, <Rm> ; T1
4093     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && OutsideITBlock()) ||
4095       EmitT32_32(0xfac0f090U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
4101     // CRC32H{<q>} <Rd>, <Rn>, <Rm> ; A1
4103         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
4104       EmitA32(0x01200040U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
4109   Delegate(kCrc32h, &Assembler::crc32h, cond, rd, rn, rm);
4112 void Assembler::crc32w(Condition cond, Register rd, Register rn, Register rm) {
4116     // CRC32W{<q>} <Rd>, <Rn>, <Rm> ; T1
4117     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && OutsideITBlock()) ||
4119       EmitT32_32(0xfac0f0a0U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
4125     // CRC32W{<q>} <Rd>, <Rn>, <Rm> ; A1
4127         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
4128       EmitA32(0x01400040U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
4133   Delegate(kCrc32w, &Assembler::crc32w, cond, rd, rn, rm);
4174                     Register rd,
4183       // EOR{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T1
4185           ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
4186         EmitT32_32(0xf0800000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
4195       // EOR{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
4198                 (rd.GetCode() << 12) | (rn.GetCode() << 16) |
4209         if (InITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() &&
4211           EmitT32_16(0x4040 | rd.GetCode() | (rm.GetCode() << 3));
4220       // EOR{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
4222           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
4224         EmitT32_32(0xea800000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
4231       // EOR{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
4235                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
4246       // EOR{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
4248           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
4251                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
4257   Delegate(kEor, &Assembler::eor, cond, size, rd, rn, operand);
4262                      Register rd,
4271       // EORS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T1
4272       if (!size.IsNarrow() && immediate_t32.IsValid() && !rd.Is(pc) &&
4274         EmitT32_32(0xf0900000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
4283       // EORS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
4286                 (rd.GetCode() << 12) | (rn.GetCode() << 16) |
4297         if (OutsideITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() &&
4299           EmitT32_16(0x4040 | rd.GetCode() | (rm.GetCode() << 3));
4308       // EORS{<c>}{<q>} {<Rd
4309       if (!size.IsNarrow() && shift.IsValidAmount(amount) && !rd.Is(pc) &&
4312         EmitT32_32(0xea900000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
4319       // EORS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
4323                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
4334       // EORS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
4336           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
4339                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
4345   Delegate(kEors, &Assembler::eors, cond, size, rd, rn, operand);
6695                     Register rd,
6703       // LSL<c>{<q>} {<Rd>}, <Rm>, #<imm> ; T2
6704       if (InITBlock() && !size.IsWide() && rd.IsLow() && rm.IsLow() &&
6706         EmitT32_16(0x0000 | rd.GetCode() | (rm.GetCode() << 3) | (imm << 6));
6710       // LSL{<c>}{<q>} {<Rd>}, <Rm>, #<imm> ; T3
6712           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
6713         EmitT32_32(0xea4f0000U | (rd.GetCode() << 8) | rm.GetCode() |
6719       // LSL{<c>}{<q>} {<Rd>}, <Rm>, #<imm> ; A1
6722                 (rd.GetCode() << 12) | rm.GetCode() | (imm << 7));
6731       if (InITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&
6733         EmitT32_16(0x4080 | rd.GetCode() | (rs.GetCode() << 3));
6737       // LSL{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; T2
6739           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
6740         EmitT32_32(0xfa00f000U | (rd.GetCode() << 8) | (rm.GetCode() << 16) |
6746       // LSL{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; A1
6748           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
6750                 (rd.GetCode() << 12) | rm.GetCode() | (rs.GetCode() << 8));
6755   Delegate(kLsl, &Assembler::lsl, cond, size, rd, rm, operand);
6760                      Register rd,
6768       // LSLS{<q>} {<Rd>}, <Rm>, #<imm> ; T2
6769       if (OutsideITBlock() && !size.IsWide() && rd.IsLow() && rm.IsLow() &&
6771         EmitT32_16(0x0000 | rd.GetCode() | (rm.GetCode() << 3) | (imm << 6));
6775       // LSLS{<c>}{<q>} {<Rd>}, <Rm>, #<imm> ; T3
6777           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
6778         EmitT32_32(0xea5f0000U | (rd.GetCode() << 8) | rm.GetCode() |
6784       // LSLS{<c>}{<q>} {<Rd
6787                 (rd.GetCode() << 12) | rm.GetCode() | (imm << 7));
6796       if (OutsideITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&
6798         EmitT32_16(0x4080 | rd.GetCode() | (rs.GetCode() << 3));
6802       // LSLS{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; T2
6804           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
6805         EmitT32_32(0xfa10f000U | (rd.GetCode() << 8) | (rm.GetCode() << 16) |
6811       // LSLS{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; A1
6813           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
6815                 (rd.GetCode() << 12) | rm.GetCode() | (rs.GetCode() << 8));
6820   Delegate(kLsls, &Assembler::lsls, cond, size, rd, rm, operand);
6825                     Register rd,
6833       // LSR<c>{<q>} {<Rd>}, <Rm>, #<imm> ; T2
6834       if (InITBlock() && !size.IsWide() && rd.IsLow() && rm.IsLow() &&
6837         EmitT32_16(0x0800 | rd.GetCode() | (rm.GetCode() << 3) |
6842       // LSR{<c>}{<q>} {<Rd>}, <Rm>, #<imm> ; T3
6844           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
6846         EmitT32_32(0xea4f0010U | (rd.GetCode() << 8) | rm.GetCode() |
6852       // LSR{<c>}{<q>} {<Rd>}, <Rm>, #<imm> ; A1
6856                 (rd.GetCode() << 12) | rm.GetCode() | (amount_ << 7));
6865       if (InITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&
6867         EmitT32_16(0x40c0 | rd.GetCode() | (rs.GetCode() << 3));
6871       // LSR{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; T2
6873           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
6874         EmitT32_32(0xfa20f000U | (rd.GetCode() << 8) | (rm.GetCode() << 16) |
6880       // LSR{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; A1
6882           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
6884                 (rd.GetCode() << 12) | rm.GetCode() | (rs.GetCode() << 8));
6889   Delegate(kLsr, &Assembler::lsr, cond, size, rd, rm, operand);
6894                      Register rd,
6902       // LSRS{<q>} {<Rd>}, <Rm>, #<imm> ; T2
6903       if (OutsideITBlock() && !size.IsWide() && rd.IsLow() && rm.IsLow() &&
6906         EmitT32_16(0x0800 | rd.GetCode() | (rm.GetCode() << 3) |
6911       // LSRS{<c>}{<q>} {<Rd>}, <Rm>, #<imm> ; T3
6913           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
6915         EmitT32_32(0xea5f0010U | (rd.GetCode() << 8) | rm.GetCode() |
6921       // LSRS{<c>}{<q>} {<Rd>}, <Rm>, #<imm> ; A1
6925                 (rd.GetCode() << 12) | rm.GetCode() | (amount_ << 7));
6934       if (OutsideITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&
6936         EmitT32_16(0x40c0 | rd.GetCode() | (rs.GetCode() << 3));
6940       // LSRS{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; T2
6942           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
6943         EmitT32_32(0xfa30f000U | (rd.GetCode() << 8) | (rm.GetCode() << 16) |
6949       // LSRS{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; A1
6951           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
6953                 (rd.GetCode() << 12) | rm.GetCode() | (rs.GetCode() << 8));
6958   Delegate(kLsrs, &Assembler::lsrs, cond, size, rd, rm, operand);
6962     Condition cond, Register rd, Register rn, Register rm, Register ra) {
6966     // MLA{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; T1
6968         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
6969       EmitT32_32(0xfb000000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
6975     // MLA{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; A1
6977         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||
6979       EmitA32(0x00200090U | (cond.GetCondition() << 28) | (rd.GetCode() << 16) |
6984   Delegate(kMla, &Assembler::mla, cond, rd, rn, rm, ra);
6988     Condition cond, Register rd, Register rn, Register rm, Register ra) {
6992     // MLAS{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; A1
6994         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||
6996       EmitA32(0x00300090U | (cond.GetCondition() << 28) | (rd.GetCode() << 16) |
7001   Delegate(kMlas, &Assembler::mlas, cond, rd, rn, rm, ra);
7005     Condition cond, Register rd, Register rn, Register rm, Register ra) {
7009     // MLS{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; T1
7010     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||
7012       EmitT32_32(0xfb000010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
7018     // MLS{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; A1
7020         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||
7022       EmitA32(0x00600090U | (cond.GetCondition() << 28) | (rd.GetCode() << 16) |
7027   Delegate(kMls, &Assembler::mls, cond, rd, rn, rm, ra);
7032                     Register rd,
7040         // MOV{<c>}{<q>} <Rd>, <Rm> ; T1
7042             ((!rd.IsPC() || OutsideITBlockAndAlOrLast(cond)) ||
7044           EmitT32_16(0x4600 | (rd.GetCode() & 0x7) |
7045                      ((rd.GetCode() & 0x8) << 4) | (rm.GetCode() << 3));
7054       // MOV<c>{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T2
7055       if (InITBlock() && !size.IsWide() && rd.IsLow() &&
7060         EmitT32_16(0x0000 | rd.GetCode() | (rm.GetCode() << 3) |
7065       // MOV{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T3
7067           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
7069         EmitT32_32(0xea4f0000U | (rd.GetCode() << 8) | rm.GetCode() |
7076       // MOV{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; A1
7080                 (rd.GetCode() << 12) | rm.GetCode() |
7092       if (InITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&
7094         EmitT32_16(0x4100 | rd.GetCode() | (rs.GetCode() << 3));
7099       if (InITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&
7101         EmitT32_16(0x4080 | rd.GetCode() | (rs.GetCode() << 3));
7106       if (InITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&
7108         EmitT32_16(0x40c0 | rd.GetCode() | (rs.GetCode() << 3));
7113       if (InITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&
7115         EmitT32_16(0x41c0 | rd.GetCode() | (rs.GetCode() << 3));
7119       // MOV{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs> ; T2
7121           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
7122         EmitT32_32(0xfa00f000U | (rd.GetCode() << 8) | (rm.GetCode() << 16) |
7128       // MOV{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs> ; A1
7130           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
7132                 (rd.GetCode() << 12) | rm.GetCode() | (shift.GetType() << 5) |
7142       // MOV<c>{<q>} <Rd>, #<imm8> ; T1
7143       if (InITBlock() && !size.IsWide() && rd.IsLow() && (imm <= 255)) {
7144         EmitT32_16(0x2000 | (rd.GetCode() << 8) | imm);
7148       // MOV{<c>}{<q>} <Rd>, #<const> ; T2
7150           (!rd.IsPC() || AllowUnpredictable())) {
7151         EmitT32_32(0xf04f0000U | (rd.GetCode() << 8) |
7158       // MOV{<c>}{<q>} <Rd>, #<imm16> ; T3
7160           (!rd.IsPC() || AllowUnpredictable())) {
7161         EmitT32_32(0xf2400000U | (rd.GetCode() << 8) | (imm & 0xff) |
7169       // MOV{<c>}{<q>} <Rd>, #<const> ; A1
7172                 (rd.GetCode() << 12) | immediate_a32.GetEncodingValue());
7175       // MOV{<c>}{<q>} <Rd>, #<imm16> ; A2
7177           (!rd.IsPC() || AllowUnpredictable())) {
7179                 (rd.GetCode() << 12) | (imm & 0xfff) | ((imm & 0xf000) << 4));
7184   Delegate(kMov, &Assembler::mov, cond, size, rd, operand);
7189                      Register rd,
7198       // MOVS{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T2
7199       if (OutsideITBlock() && !size.IsWide() && rd.IsLow() &&
7203         EmitT32_16(0x0000 | rd.GetCode() | (rm.GetCode() << 3) |
7208       // MOVS{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T3
7210           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
7212         EmitT32_32(0xea5f0000U | (rd.GetCode() << 8) | rm.GetCode() |
7219       // MOVS{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; A1
7221           (!rd.IsPC() || AllowUnpredictable())) {
7224                 (rd.GetCode() << 12) | rm.GetCode() |
7236       if (OutsideITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&
7238         EmitT32_16(0x4100 | rd.GetCode() | (rs.GetCode() << 3));
7243       if (OutsideITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&
7245         EmitT32_16(0x4080 | rd.GetCode() | (rs.GetCode() << 3));
7250       if (OutsideITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&
7252         EmitT32_16(0x40c0 | rd.GetCode() | (rs.GetCode() << 3));
7257       if (OutsideITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&
7259         EmitT32_16(0x41c0 | rd.GetCode() | (rs.GetCode() << 3));
7263       // MOVS{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs> ; T2
7265           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
7266         EmitT32_32(0xfa10f000U | (rd.GetCode() << 8) | (rm.GetCode() << 16) |
7272       // MOVS{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs> ; A1
7274           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
7276                 (rd.GetCode() << 12) | rm.GetCode() | (shift.GetType() << 5) |
7286       // MOVS{<q>} <Rd>, #<imm8> ; T1
7287       if (OutsideITBlock() && !size.IsWide() && rd.IsLow() && (imm <= 255)) {
7288         EmitT32_16(0x2000 | (rd.GetCode() << 8) | imm);
7292       // MOVS{<c>}{<q>} <Rd>, #<const> ; T2
7294           (!rd.IsPC() || AllowUnpredictable())) {
7295         EmitT32_32(0xf05f0000U | (rd.GetCode() << 8) |
7304       // MOVS{<c>}{<q>} <Rd>, #<const> ; A1
7307                 (rd.GetCode() << 12) | immediate_a32.GetEncodingValue());
7312   Delegate(kMovs, &Assembler::movs, cond, size, rd, operand);
7315 void Assembler::movt(Condition cond, Register rd, const Operand& operand) {
7321       // MOVT{<c>}{<q>} <Rd>, #<imm16> ; T1
7322       if ((imm <= 65535) && (!rd.IsPC() || AllowUnpredictable())) {
7323         EmitT32_32(0xf2c00000U | (rd.GetCode() << 8) | (imm & 0xff) |
7330       // MOVT{<c>}{<q>} <Rd>, #<imm16> ; A1
7332           (!rd.IsPC() || AllowUnpredictable())) {
7334                 (rd.GetCode() << 12) | (imm & 0xfff) | ((imm & 0xf000) << 4));
7339   Delegate(kMovt, &Assembler::movt, cond, rd, operand);
7342 void Assembler::movw(Condition cond, Register rd, const Operand& operand) {
7348       // MOVW{<c>}{<q>} <Rd>, #<imm16> ; T3
7349       if ((imm <= 65535) && (!rd.IsPC() || AllowUnpredictable())) {
7350         EmitT32_32(0xf2400000U | (rd.GetCode() << 8) | (imm & 0xff) |
7357       // MOVW{<c>}{<q>} <Rd>, #<imm16> ; A2
7359           (!rd.IsPC() || AllowUnpredictable())) {
7361                 (rd.GetCode() << 12) | (imm & 0xfff) | ((imm & 0xf000) << 4));
7366   Delegate(kMovw, &Assembler::movw, cond, rd, operand);
7369 void Assembler::mrs(Condition cond, Register rd, SpecialRegister spec_reg) {
7373     // MRS{<c>}{<q>} <Rd>, <spec_reg> ; T1
7374     if ((!rd.IsPC() || AllowUnpredictable())) {
7375       EmitT32_32(0xf3ef8000U | (rd.GetCode() << 8) | (spec_reg.GetReg() << 20));
7380     // MRS{<c>}{<q>} <Rd>, <spec_reg> ; A1
7381     if (cond.IsNotNever() && (!rd.IsPC() || AllowUnpredictable())) {
7382       EmitA32(0x010f0000U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
7387   Delegate(kMrs, &Assembler::mrs, cond, rd, spec_reg);
7433     Condition cond, EncodingSize size, Register rd, Register rn, Register rm) {
7438     if (InITBlock() && !size.IsWide() && rd.Is(rm) && rn.IsLow() &&
7440       EmitT32_16(0x4340 | rd.GetCode() | (rn.GetCode() << 3));
7444     // MUL{<c>}{<q>} <Rd>, <Rn>, {<Rm>} ; T2
7446         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
7447       EmitT32_32(0xfb00f000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
7453     // MUL{<c>}{<q>} <Rd>, <Rn>, {<Rm>} ; A1
7455         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
7456       EmitA32(0x00000090U | (cond.GetCondition() << 28) | (rd.GetCode() << 16) |
7461   Delegate(kMul, &Assembler::mul, cond, size, rd, rn, rm);
7464 void Assembler::muls(Condition cond, Register rd, Register rn, Register rm) {
7469     if (OutsideITBlock() && rd.Is(rm) && rn.IsLow() && rm.IsLow()) {
7470       EmitT32_16(0x4340 | rd.GetCode() | (rn.GetCode() << 3));
7475     // MULS{<c>}{<q>} <Rd>, <Rn>, {<Rm>} ; A1
7477         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
7478       EmitA32(0x00100090U | (cond.GetCondition() << 28) | (rd.GetCode() << 16) |
7483   Delegate(kMuls, &Assembler::muls, cond, rd, rn, rm);
7488                     Register rd,
7496       // MVN{<c>}{<q>} <Rd>, #<const> ; T1
7498           (!rd.IsPC() || AllowUnpredictable())) {
7499         EmitT32_32(0xf06f0000U | (rd.GetCode() << 8) |
7508       // MVN{<c>}{<q>} <Rd>, #<const> ; A1
7511                 (rd.GetCode() << 12) | immediate_a32.GetEncodingValue());
7520         // MVN<c>{<q>} <Rd>, <Rm> ; T1
7521         if (InITBlock() && !size.IsWide() && rd.IsLow() && rm.IsLow()) {
7522           EmitT32_16(0x43c0 | rd.GetCode() | (rm.GetCode() << 3));
7531       // MVN{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T2
7533           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
7535         EmitT32_32(0xea6f0000U | (rd.GetCode() << 8) | rm.GetCode() |
7542       // MVN{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; A1
7546                 (rd.GetCode() << 12) | rm.GetCode() |
7557       // MVN{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs> ; A1
7559           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
7561                 (rd.GetCode() << 12) | rm.GetCode() | (shift.GetType() << 5) |
7567   Delegate(kMvn, &Assembler::mvn, cond, size, rd, operand);
7572                      Register rd,
7580       // MVNS{<c>}{<q>} <Rd>, #<const> ; T1
7582           (!rd.IsPC() || AllowUnpredictable())) {
7583         EmitT32_32(0xf07f0000U | (rd.GetCode() << 8) |
7592       // MVNS{<c>}{<q>} <Rd>, #<const> ; A1
7595                 (rd.GetCode() << 12) | immediate_a32.GetEncodingValue());
7604         // MVNS{<q>} <Rd>, <Rm> ; T1
7605         if (OutsideITBlock() && !size.IsWide() && rd.IsLow() && rm.IsLow()) {
7606           EmitT32_16(0x43c0 | rd.GetCode() | (rm.GetCode() << 3));
7615       // MVNS{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T2
7617           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
7619         EmitT32_32(0xea7f0000U | (rd.GetCode() << 8) | rm.GetCode() |
7626       // MVNS{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; A1
7630                 (rd.GetCode() << 12) | rm.GetCode() |
7641       // MVNS{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs> ; A1
7643           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
7645                 (rd.GetCode() << 12) | rm.GetCode() | (shift.GetType() << 5) |
7651   Delegate(kMvns, &Assembler::mvns, cond, size, rd, operand);
7681                     Register rd,
7690       // ORN{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T1
7692           (!rd.IsPC() || AllowUnpredictable())) {
7693         EmitT32_32(0xf0600000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
7707       // ORN{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T1
7709           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
7711         EmitT32_32(0xea600000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
7719   Delegate(kOrn, &Assembler::orn, cond, rd, rn, operand);
7723                      Register rd,
7732       // ORNS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T1
7734           (!rd.IsPC() || AllowUnpredictable())) {
7735         EmitT32_32(0xf0700000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
7749       // ORNS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T1
7751           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
7753         EmitT32_32(0xea700000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
7761   Delegate(kOrns, &Assembler::orns, cond, rd, rn, operand);
7766                     Register rd,
7775       // ORR{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T1
7777           (!rd.IsPC() || AllowUnpredictable())) {
7778         EmitT32_32(0xf0400000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
7787       // ORR{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
7790                 (rd.GetCode() << 12) | (rn.GetCode() << 16) |
7801         if (InITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() &&
7803           EmitT32_16(0x4300 | rd.GetCode() | (rm.GetCode() << 3));
7812       // ORR{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
7814           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
7816         EmitT32_32(0xea400000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
7823       // ORR{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
7827                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
7838       // ORR{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
7840           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
7843                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
7849   Delegate(kOrr, &Assembler::orr, cond, size, rd, rn, operand);
7854                      Register rd,
7863       // ORRS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T1
7865           (!rd.IsPC() || AllowUnpredictable())) {
7866         EmitT32_32(0xf0500000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
7875       // ORRS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
7878                 (rd.GetCode() << 12) | (rn.GetCode() << 16) |
7889         if (OutsideITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() &&
7891           EmitT32_16(0x4300 | rd.GetCode() | (rm.GetCode() << 3));
7900       // ORRS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
7902           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
7904         EmitT32_32(0xea500000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
7911       // ORRS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
7915                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
7926       // ORRS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
7928           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
7931                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
7937   Delegate(kOrrs, &Assembler::orrs, cond, size, rd, rn, operand);
7941                       Register rd,
7951       // PKHBT{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, LSL #<imm> } ; T1
7953           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
7954         EmitT32_32(0xeac00000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
7961       // PKHBT{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, LSL #<imm> } ; A1
7963           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
7965                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
7971   Delegate(kPkhbt, &Assembler::pkhbt, cond, rd, rn, operand);
7975                       Register rd,
7985       // PKHTB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ASR #<imm> } ; T1
7987           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
7989         EmitT32_32(0xeac00020U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
7996       // PKHTB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ASR #<imm> } ; A1
7999           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8002                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
8008   Delegate(kPkhtb, &Assembler::pkhtb, cond, rd, rn, operand);
8560 void Assembler::qadd(Condition cond, Register rd, Register rm, Register rn) {
8564     // QADD{<c>}{<q>} {<Rd>}, <Rm>, <Rn> ; T1
8565     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8566       EmitT32_32(0xfa80f080U | (rd.GetCode() << 8) | rm.GetCode() |
8572     // QADD{<c>}{<q>} {<Rd>}, <Rm>, <Rn> ; A1
8574         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8575       EmitA32(0x01000050U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
8580   Delegate(kQadd, &Assembler::qadd, cond, rd, rm, rn);
8583 void Assembler::qadd16(Condition cond, Register rd, Register rn, Register rm) {
8587     // QADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
8588     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8589       EmitT32_32(0xfa90f010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
8595     // QADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
8597         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8598       EmitA32(0x06200f10U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
8603   Delegate(kQadd16, &Assembler::qadd16, cond, rd, rn, rm);
8606 void Assembler::qadd8(Condition cond, Register rd, Register rn, Register rm) {
8610     // QADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
8611     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8612       EmitT32_32(0xfa80f010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
8618     // QADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
8620         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8621       EmitA32(0x06200f90U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
8626   Delegate(kQadd8, &Assembler::qadd8, cond, rd, rn, rm);
8629 void Assembler::qasx(Condition cond, Register rd, Register rn, Register rm) {
8633     // QASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
8634     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8635       EmitT32_32(0xfaa0f010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
8641     // QASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
8643         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8644       EmitA32(0x06200f30U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
8649   Delegate(kQasx, &Assembler::qasx, cond, rd, rn, rm);
8652 void Assembler::qdadd(Condition cond, Register rd, Register rm, Register rn) {
8656     // QDADD{<c>}{<q>} {<Rd>}, <Rm>, <Rn> ; T1
8657     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8658       EmitT32_32(0xfa80f090U | (rd.GetCode() << 8) | rm.GetCode() |
8664     // QDADD{<c>}{<q>} {<Rd>}, <Rm>, <Rn> ; A1
8666         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8667       EmitA32(0x01400050U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
8672   Delegate(kQdadd, &Assembler::qdadd, cond, rd, rm, rn);
8675 void Assembler::qdsub(Condition cond, Register rd, Register rm, Register rn) {
8679     // QDSUB{<c>}{<q>} {<Rd>}, <Rm>, <Rn> ; T1
8680     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8681       EmitT32_32(0xfa80f0b0U | (rd.GetCode() << 8) | rm.GetCode() |
8687     // QDSUB{<c>}{<q>} {<Rd>}, <Rm>, <Rn> ; A1
8689         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8690       EmitA32(0x01600050U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
8695   Delegate(kQdsub, &Assembler::qdsub, cond, rd, rm, rn);
8698 void Assembler::qsax(Condition cond, Register rd, Register rn, Register rm) {
8702     // QSAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
8703     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8704       EmitT32_32(0xfae0f010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
8710     // QSAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
8712         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8713       EmitA32(0x06200f50U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
8718   Delegate(kQsax, &Assembler::qsax, cond, rd, rn, rm);
8721 void Assembler::qsub(Condition cond, Register rd, Register rm, Register rn) {
8725     // QSUB{<c>}{<q>} {<Rd>}, <Rm>, <Rn> ; T1
8726     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8727       EmitT32_32(0xfa80f0a0U | (rd.GetCode() << 8) | rm.GetCode() |
8733     // QSUB{<c>}{<q>} {<Rd>}, <Rm>, <Rn> ; A1
8735         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8736       EmitA32(0x01200050U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
8741   Delegate(kQsub, &Assembler::qsub, cond, rd, rm, rn);
8744 void Assembler::qsub16(Condition cond, Register rd, Register rn, Register rm) {
8748     // QSUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
8749     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8750       EmitT32_32(0xfad0f010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
8756     // QSUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
8758         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8759       EmitA32(0x06200f70U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
8764   Delegate(kQsub16, &Assembler::qsub16, cond, rd, rn, rm);
8767 void Assembler::qsub8(Condition cond, Register rd, Register rn, Register rm) {
8771     // QSUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
8772     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8773       EmitT32_32(0xfac0f010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
8779     // QSUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
8781         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8782       EmitA32(0x06200ff0U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
8787   Delegate(kQsub8, &Assembler::qsub8, cond, rd, rn, rm);
8790 void Assembler::rbit(Condition cond, Register rd, Register rm) {
8794     // RBIT{<c>}{<q>} <Rd>, <Rm> ; T1
8795     if (((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8796       EmitT32_32(0xfa90f0a0U | (rd.GetCode() << 8) | rm.GetCode() |
8802     // RBIT{<c>}{<q>} <Rd>, <Rm> ; A1
8804         ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8805       EmitA32(0x06ff0f30U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
8810   Delegate(kRbit, &Assembler::rbit, cond, rd, rm);
8815                     Register rd,
8820     // REV{<c>}{<q>} <Rd>, <Rm> ; T1
8821     if (!size.IsWide() && rd.IsLow() && rm.IsLow()) {
8822       EmitT32_16(0xba00 | rd.GetCode() | (rm.GetCode() << 3));
8826     // REV{<c>}{<q>} <Rd>, <Rm> ; T2
8828         ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8829       EmitT32_32(0xfa90f080U | (rd.GetCode() << 8) | rm.GetCode() |
8835     // REV{<c>}{<q>} <Rd>, <Rm> ; A1
8837         ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8838       EmitA32(0x06bf0f30U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
8843   Delegate(kRev, &Assembler::rev, cond, size, rd, rm);
8848                       Register rd,
8853     // REV16{<c>}{<q>} <Rd>, <Rm> ; T1
8854     if (!size.IsWide() && rd.IsLow() && rm.IsLow()) {
8855       EmitT32_16(0xba40 | rd.GetCode() | (rm.GetCode() << 3));
8859     // REV16{<c>}{<q>} <Rd>, <Rm> ; T2
8861         ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8862       EmitT32_32(0xfa90f090U | (rd.GetCode() << 8) | rm.GetCode() |
8868     // REV16{<c>}{<q>} <Rd>, <Rm> ; A1
8870         ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8871       EmitA32(0x06bf0fb0U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
8876   Delegate(kRev16, &Assembler::rev16, cond, size, rd, rm);
8881                       Register rd,
8886     // REVSH{<c>}{<q>} <Rd>, <Rm> ; T1
8887     if (!size.IsWide() && rd.IsLow() && rm.IsLow()) {
8888       EmitT32_16(0xbac0 | rd.GetCode() | (rm.GetCode() << 3));
8892     // REVSH{<c>}{<q>} <Rd>, <Rm> ; T2
8894         ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8895       EmitT32_32(0xfa90f0b0U | (rd.GetCode() << 8) | rm.GetCode() |
8901     // REVSH{<c>}{<q>} <Rd>, <Rm> ; A1
8903         ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8904       EmitA32(0x06ff0fb0U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
8909   Delegate(kRevsh, &Assembler::revsh, cond, size, rd, rm);
8914                     Register rd,
8922       // ROR{<c>}{<q>} {<Rd>}, <Rm>, #<imm> ; T3
8924           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8925         EmitT32_32(0xea4f0030U | (rd.GetCode() << 8) | rm.GetCode() |
8931       // ROR{<c>}{<q>} {<Rd>}, <Rm>, #<imm> ; A1
8934                 (rd.GetCode() << 12) | rm.GetCode() | (imm << 7));
8943       if (InITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&
8945         EmitT32_16(0x41c0 | rd.GetCode() | (rs.GetCode() << 3));
8949       // ROR{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; T2
8951           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
8952         EmitT32_32(0xfa60f000U | (rd.GetCode() << 8) | (rm.GetCode() << 16) |
8958       // ROR{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; A1
8960           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
8962                 (rd.GetCode() << 12) | rm.GetCode() | (rs.GetCode() << 8));
8967   Delegate(kRor, &Assembler::ror, cond, size, rd, rm, operand);
8972                      Register rd,
8980       // RORS{<c>}{<q>} {<Rd>}, <Rm>, #<imm> ; T3
8982           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8983         EmitT32_32(0xea5f0030U | (rd.GetCode() << 8) | rm.GetCode() |
8989       // RORS{<c>}{<q>} {<Rd>}, <Rm>, #<imm> ; A1
8992                 (rd.GetCode() << 12) | rm.GetCode() | (imm << 7));
9001       if (OutsideITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&
9003         EmitT32_16(0x41c0 | rd.GetCode() | (rs.GetCode() << 3));
9007       // RORS{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; T2
9009           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
9010         EmitT32_32(0xfa70f000U | (rd.GetCode() << 8) | (rm.GetCode() << 16) |
9016       // RORS{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; A1
9018           ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
9020                 (rd.GetCode() << 12) | rm.GetCode() | (rs.GetCode() << 8));
9025   Delegate(kRors, &Assembler::rors, cond, size, rd, rm, operand);
9028 void Assembler::rrx(Condition cond, Register rd, Register rm) {
9032     // RRX{<c>}{<q>} {<Rd>}, <Rm> ; T3
9033     if (((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9034       EmitT32_32(0xea4f0030U | (rd.GetCode() << 8) | rm.GetCode());
9039     // RRX{<c>}{<q>} {<Rd>}, <Rm> ; A1
9041       EmitA32(0x01a00060U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
9046   Delegate(kRrx, &Assembler::rrx, cond, rd, rm);
9049 void Assembler::rrxs(Condition cond, Register rd, Register rm) {
9053     // RRXS{<c>}{<q>} {<Rd>}, <Rm> ; T3
9054     if (((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9055       EmitT32_32(0xea5f0030U | (rd.GetCode() << 8) | rm.GetCode());
9060     // RRXS{<c>}{<q>} {<Rd>}, <Rm> ; A1
9062       EmitA32(0x01b00060U | (cond.GetCondition() << 28) | (rd
9067   Delegate(kRrxs, &Assembler::rrxs, cond, rd, rm);
9072                     Register rd,
9081       // RSB<c>{<q>} {<Rd>}, <Rn>, #0 ; T1
9082       if (InITBlock() && !size.IsWide() && rd.IsLow() && rn.IsLow() &&
9084         EmitT32_16(0x4240 | rd.GetCode() | (rn.GetCode() << 3));
9088       // RSB{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T2
9090           ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
9091         EmitT32_32(0xf1c00000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9100       // RSB{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
9103                 (rd.GetCode() << 12) | (rn.GetCode() << 16) |
9114       // RSB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T1
9116           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9118         EmitT32_32(0xebc00000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9125       // RSB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
9129                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
9140       // RSB{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
9142           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
9145                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
9151   Delegate(kRsb, &Assembler::rsb, cond, size, rd, rn, operand);
9156                      Register rd,
9165       // RSBS{<q>} {<Rd>}, <Rn>, #0 ; T1
9166       if (OutsideITBlock() && !size.IsWide() && rd.IsLow() && rn.IsLow() &&
9168         EmitT32_16(0x4240 | rd.GetCode() | (rn.GetCode() << 3));
9172       // RSBS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T2
9174           ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
9175         EmitT32_32(0xf1d00000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9184       // RSBS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
9187                 (rd.GetCode() << 12) | (rn.GetCode() << 16) |
9198       // RSBS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T1
9200           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9202         EmitT32_32(0xebd00000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9209       // RSBS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
9213                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
9224       // RSBS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
9226           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
9229                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
9235   Delegate(kRsbs, &Assembler::rsbs, cond, size, rd, rn, operand);
9239                     Register rd,
9248       // RSC{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
9251                 (rd.GetCode() << 12) | (rn.GetCode() << 16) |
9262       // RSC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
9266                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
9277       // RSC{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
9279           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
9282                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
9288   Delegate(kRsc, &Assembler::rsc, cond, rd, rn, operand);
9292                      Register rd,
9301       // RSCS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
9304                 (rd.GetCode() << 12) | (rn.GetCode() << 16) |
9315       // RSCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
9319                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
9330       // RSCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
9332           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
9335                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
9341   Delegate(kRscs, &Assembler::rscs, cond, rd, rn, operand);
9344 void Assembler::sadd16(Condition cond, Register rd, Register rn, Register rm) {
9348     // SADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
9349     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9350       EmitT32_32(0xfa90f000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9356     // SADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
9358         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9359       EmitA32(0x06100f10U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
9364   Delegate(kSadd16, &Assembler::sadd16, cond, rd, rn, rm);
9367 void Assembler::sadd8(Condition cond, Register rd, Register rn, Register rm) {
9371     // SADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
9372     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9373       EmitT32_32(0xfa80f000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9379     // SADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
9381         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9382       EmitA32(0x06100f90U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
9387   Delegate(kSadd8, &Assembler::sadd8, cond, rd, rn, rm);
9390 void Assembler::sasx(Condition cond, Register rd, Register rn, Register rm) {
9394     // SASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
9395     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9396       EmitT32_32(0xfaa0f000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9402     // SASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
9404         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9405       EmitA32(0x06100f30U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
9410   Delegate(kSasx, &Assembler::sasx, cond, rd, rn, rm);
9415                     Register rd,
9424       // SBC{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T1
9426           ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
9427         EmitT32_32(0xf1600000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9436       // SBC{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
9439                 (rd.GetCode() << 12) | (rn.GetCode() << 16) |
9450         if (InITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() &&
9452           EmitT32_16(0x4180 | rd.GetCode() | (rm.GetCode() << 3));
9461       // SBC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
9463           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9465         EmitT32_32(0xeb600000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9472       // SBC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
9476                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
9487       // SBC{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
9489           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
9492                 (rd
9498   Delegate(kSbc, &Assembler::sbc, cond, size, rd, rn, operand);
9503                      Register rd,
9512       // SBCS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T1
9514           ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
9515         EmitT32_32(0xf1700000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9524       // SBCS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
9527                 (rd.GetCode() << 12) | (rn.GetCode() << 16) |
9538         if (OutsideITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() &&
9540           EmitT32_16(0x4180 | rd.GetCode() | (rm.GetCode() << 3));
9549       // SBCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
9551           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9553         EmitT32_32(0xeb700000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9560       // SBCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
9564                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
9575       // SBCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
9577           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
9580                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
9586   Delegate(kSbcs, &Assembler::sbcs, cond, size, rd, rn, operand);
9590     Condition cond, Register rd, Register rn, uint32_t lsb, uint32_t width) {
9594     // SBFX{<c>}{<q>} <Rd>, <Rn>, #<lsb>, #<width> ; T1
9596         (((width >= 1) && (width <= 32 - lsb) && !rd.IsPC() && !rn.IsPC()) ||
9599       EmitT32_32(0xf3400000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9605     // SBFX{<c>}{<q>} <Rd>, <Rn>, #<lsb>, #<width> ; A1
9607         (((width >= 1) && (width <= 32 - lsb) && !rd.IsPC() && !rn.IsPC()) ||
9610       EmitA32(0x07a00050U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
9615   Delegate(kSbfx, &Assembler::sbfx, cond, rd, rn, lsb, width);
9618 void Assembler::sdiv(Condition cond, Register rd, Register rn, Register rm) {
9622     // SDIV{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
9623     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9624       EmitT32_32(0xfb90f0f0U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9630     // SDIV{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
9632         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9633       EmitA32(0x0710f010U | (cond.GetCondition() << 28) | (rd.GetCode() << 16) |
9638   Delegate(kSdiv, &Assembler::sdiv, cond, rd, rn, rm);
9641 void Assembler::sel(Condition cond, Register rd, Register rn, Register rm) {
9645     // SEL{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
9646     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9647       EmitT32_32(0xfaa0f080U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9653     // SEL{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
9655         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9656       EmitA32(0x06800fb0U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
9661   Delegate(kSel, &Assembler::sel, cond, rd, rn, rm);
9664 void Assembler::shadd16(Condition cond, Register rd, Register rn, Register rm) {
9668     // SHADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
9669     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9670       EmitT32_32(0xfa90f020U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9676     // SHADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
9678         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9679       EmitA32(0x06300f10U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
9684   Delegate(kShadd16, &Assembler::shadd16, cond, rd, rn, rm);
9687 void Assembler::shadd8(Condition cond, Register rd, Register rn, Register rm) {
9691     // SHADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
9692     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9693       EmitT32_32(0xfa80f020U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9699     // SHADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
9701         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9702       EmitA32(0x06300f90U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
9707   Delegate(kShadd8, &Assembler::shadd8, cond, rd, rn, rm);
9710 void Assembler::shasx(Condition cond, Register rd, Register rn, Register rm) {
9714     // SHASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
9715     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9716       EmitT32_32(0xfaa0f020U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9722     // SHASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
9724         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9725       EmitA32(0x06300f30U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
9730   Delegate(kShasx, &Assembler::shasx, cond, rd, rn, rm);
9733 void Assembler::shsax(Condition cond, Register rd, Register rn, Register rm) {
9737     // SHSAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
9738     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9739       EmitT32_32(0xfae0f020U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9745     // SHSAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
9747         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9748       EmitA32(0x06300f50U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
9753   Delegate(kShsax, &Assembler::shsax, cond, rd, rn, rm);
9756 void Assembler::shsub16(Condition cond, Register rd, Register rn, Register rm) {
9760     // SHSUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
9761     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9762       EmitT32_32(0xfad0f020U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9768     // SHSUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
9770         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9771       EmitA32(0x06300f70U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
9776   Delegate(kShsub16, &Assembler::shsub16, cond, rd, rn, rm);
9779 void Assembler::shsub8(Condition cond, Register rd, Register rn, Register rm) {
9783     // SHSUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
9784     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9785       EmitT32_32(0xfac0f020U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9791     // SHSUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
9793         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9794       EmitA32(0x06300ff0U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
9799   Delegate(kShsub8, &Assembler::shsub8, cond, rd, rn, rm);
9803     Condition cond, Register rd, Register rn, Register rm, Register ra) {
9807     // SMLABB{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; T1
9809         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9810       EmitT32_32(0xfb100000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9816     // SMLABB{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; A1
9818         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||
9820       EmitA32(0x01000080U | (cond.GetCondition() << 28) | (rd.GetCode() << 16) |
9825   Delegate(kSmlabb, &Assembler::smlabb, cond, rd, rn, rm, ra);
9829     Condition cond, Register rd, Register rn, Register rm, Register ra) {
9833     // SMLABT{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; T1
9835         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9836       EmitT32_32(0xfb100010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9842     // SMLABT{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; A1
9844         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||
9846       EmitA32(0x010000c0U | (cond.GetCondition() << 28) | (rd.GetCode() << 16) |
9851   Delegate(kSmlabt, &Assembler::smlabt, cond, rd, rn, rm, ra);
9855     Condition cond, Register rd, Register rn, Register rm, Register ra) {
9859     // SMLAD{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; T1
9861         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9862       EmitT32_32(0xfb200000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9868     // SMLAD{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; A1
9870         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9871       EmitA32(0x07000010U | (cond.GetCondition() << 28) | (rd.GetCode() << 16) |
9876   Delegate(kSmlad, &Assembler::smlad, cond, rd, rn, rm, ra);
9880     Condition cond, Register rd, Register rn, Register rm, Register ra) {
9884     // SMLADX{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; T1
9886         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9887       EmitT32_32(0xfb200010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9893     // SMLADX{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; A1
9895         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9896       EmitA32(0x07000030U | (cond.GetCondition() << 28) | (rd.GetCode() << 16) |
9901   Delegate(kSmladx, &Assembler::smladx, cond, rd, rn, rm, ra);
9909     // SMLAL{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; T1
9918     // SMLAL{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; A1
9936     // SMLALBB{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; T1
9945 Rd>, <Rd>, <Rn>, <Rm> ; A1
9963     // SMLALBT{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; T1
9972     // SMLALBT{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; A1
9990     // SMLALD{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; T1
9999     // SMLALD{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; A1
10017     // SMLALDX{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; T1
10026     // SMLALDX{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; A1
10044     // SMLALS{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; A1
10062     // SMLALTB{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; T1
10071     // SMLALTB{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; A1
10089     // SMLALTT{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; T1
10098     // SMLALTT{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; A1
10112     Condition cond, Register rd, Register rn, Register rm, Register ra) {
10116     // SMLATB{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; T1
10118         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10119       EmitT32_32(0xfb100020U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10125     // SMLATB{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; A1
10127         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||
10129       EmitA32(0x010000a0U | (cond.GetCondition() << 28) | (rd.GetCode() << 16) |
10134   Delegate(kSmlatb, &Assembler::smlatb, cond, rd, rn, rm, ra);
10138     Condition cond, Register rd, Register rn, Register rm, Register ra) {
10142     // SMLATT{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; T1
10144         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10145       EmitT32_32(0xfb100030U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10151     // SMLATT{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; A1
10153         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||
10155       EmitA32(0x010000e0U | (cond.GetCondition() << 28) | (rd.GetCode() << 16) |
10160   Delegate(kSmlatt, &Assembler::smlatt, cond, rd, rn, rm, ra);
10164     Condition cond, Register rd, Register rn, Register rm, Register ra) {
10168     // SMLAWB{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; T1
10170         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10171       EmitT32_32(0xfb300000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10177     // SMLAWB{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; A1
10179         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||
10181       EmitA32(0x01200080U | (cond.GetCondition() << 28) | (rd.GetCode() << 16) |
10186   Delegate(kSmlawb, &Assembler::smlawb, cond, rd, rn, rm, ra);
10190     Condition cond, Register rd, Register rn, Register rm, Register ra) {
10194     // SMLAWT{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; T1
10196         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10197       EmitT32_32(0xfb300010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10203     // SMLAWT{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; A1
10205         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||
10207       EmitA32(0x012000c0U | (cond.GetCondition() << 28) | (rd.GetCode() << 16) |
10212   Delegate(kSmlawt, &Assembler::smlawt, cond, rd, rn, rm, ra);
10216     Condition cond, Register rd, Register rn, Register rm, Register ra) {
10220     // SMLSD{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; T1
10222         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10223       EmitT32_32(0xfb400000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10229     // SMLSD{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; A1
10231         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10232       EmitA32(0x07000050U | (cond.GetCondition() << 28) | (rd.GetCode() << 16) |
10237   Delegate(kSmlsd, &Assembler::smlsd, cond, rd, rn, rm, ra);
10241     Condition cond, Register rd, Register rn, Register rm, Register ra) {
10245     // SMLSDX{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; T1
10247         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10248       EmitT32_32(0xfb400010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10254     // SMLSDX{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; A1
10256         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10257       EmitA32(0x07000070U | (cond.GetCondition() << 28) | (rd.GetCode() << 16) |
10262   Delegate(kSmlsdx, &Assembler::smlsdx, cond, rd, rn, rm, ra);
10270     // SMLSLD{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; T1
10279     // SMLSLD{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; A1
10297     // SMLSLDX{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; T1
10306     // SMLSLDX{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; A1
10320     Condition cond, Register rd, Register rn, Register rm, Register ra) {
10324     // SMMLA{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; T1
10326         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10327       EmitT32_32(0xfb500000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10333     // SMMLA{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; A1
10335         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10336       EmitA32(0x07500010U | (cond.GetCondition() << 28) | (rd.GetCode() << 16) |
10341   Delegate(kSmmla, &Assembler::smmla, cond, rd, rn, rm, ra);
10345     Condition cond, Register rd, Register rn, Register rm, Register ra) {
10349     // SMMLAR{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; T1
10351         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10352       EmitT32_32(0xfb500010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10358     // SMMLAR{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; A1
10360         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10361       EmitA32(0x07500030U | (cond.GetCondition() << 28) | (rd.GetCode() << 16) |
10366   Delegate(kSmmlar, &Assembler::smmlar, cond, rd, rn, rm, ra);
10370     Condition cond, Register rd, Register rn, Register rm, Register ra) {
10374     // SMMLS{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; T1
10375     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||
10377       EmitT32_32(0xfb600000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10383     // SMMLS{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; A1
10385         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||
10387       EmitA32(0x075000d0U | (cond.GetCondition() << 28) | (rd.GetCode() << 16) |
10392   Delegate(kSmmls, &Assembler::smmls, cond, rd, rn, rm, ra);
10396     Condition cond, Register rd, Register rn, Register rm, Register ra) {
10400 Rd>, <Rn>, <Rm>, <Ra> ; T1
10401     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||
10403       EmitT32_32(0xfb600010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10409     // SMMLSR{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; A1
10411         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||
10413       EmitA32(0x075000f0U | (cond.GetCondition() << 28) | (rd.GetCode() << 16) |
10418   Delegate(kSmmlsr, &Assembler::smmlsr, cond, rd, rn, rm, ra);
10421 void Assembler::smmul(Condition cond, Register rd, Register rn, Register rm) {
10425     // SMMUL{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
10426     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10427       EmitT32_32(0xfb50f000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10433     // SMMUL{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
10435         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10436       EmitA32(0x0750f010U | (cond.GetCondition() << 28) | (rd.GetCode() << 16) |
10441   Delegate(kSmmul, &Assembler::smmul, cond, rd, rn, rm);
10444 void Assembler::smmulr(Condition cond, Register rd, Register rn, Register rm) {
10448     // SMMULR{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
10449     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10450       EmitT32_32(0xfb50f010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10456     // SMMULR{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
10458         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10459       EmitA32(0x0750f030U | (cond.GetCondition() << 28) | (rd.GetCode() << 16) |
10464   Delegate(kSmmulr, &Assembler::smmulr, cond, rd, rn, rm);
10467 void Assembler::smuad(Condition cond, Register rd, Register rn, Register rm) {
10471     // SMUAD{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
10472     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10473       EmitT32_32(0xfb20f000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10479     // SMUAD{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
10481         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10482       EmitA32(0x0700f010U | (cond.GetCondition() << 28) | (rd.GetCode() << 16) |
10487   Delegate(kSmuad, &Assembler::smuad, cond, rd, rn, rm);
10490 void Assembler::smuadx(Condition cond, Register rd, Register rn, Register rm) {
10494     // SMUADX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
10495     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10496       EmitT32_32(0xfb20f010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10502     // SMUADX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
10504         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10505       EmitA32(0x0700f030U | (cond.GetCondition() << 28) | (rd.GetCode() << 16) |
10510   Delegate(kSmuadx, &Assembler::smuadx, cond, rd, rn, rm);
10513 void Assembler::smulbb(Condition cond, Register rd, Register rn, Register rm) {
10517     // SMULBB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
10518     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10519       EmitT32_32(0xfb10f000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10525     // SMULBB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
10527         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10528       EmitA32(0x01600080U | (cond.GetCondition() << 28) | (rd.GetCode() << 16) |
10533   Delegate(kSmulbb, &Assembler::smulbb, cond, rd, rn, rm);
10536 void Assembler::smulbt(Condition cond, Register rd, Register rn, Register rm) {
10540     // SMULBT{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
10541     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10542       EmitT32_32(0xfb10f010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10548     // SMULBT{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
10550         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10551       EmitA32(0x016000c0U | (cond.GetCondition() << 28) | (rd.GetCode() << 16) |
10556   Delegate(kSmulbt, &Assembler::smulbt, cond, rd, rn, rm);
10564     // SMULL{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; T1
10573     // SMULL{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; A1
10591     // SMULLS{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; A1
10604 void Assembler::smultb(Condition cond, Register rd, Register rn, Register rm) {
10608     // SMULTB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
10609     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10610       EmitT32_32(0xfb10f020U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10616     // SMULTB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
10618         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10619       EmitA32(0x016000a0U | (cond.GetCondition() << 28) | (rd.GetCode() << 16) |
10624   Delegate(kSmultb, &Assembler::smultb, cond, rd, rn, rm);
10627 void Assembler::smultt(Condition cond, Register rd, Register rn, Register rm) {
10631     // SMULTT{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
10632     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10633       EmitT32_32(0xfb10f030U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10639     // SMULTT{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
10641         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10642       EmitA32(0x016000e0U | (cond.GetCondition() << 28) | (rd.GetCode() << 16) |
10647   Delegate(kSmultt, &Assembler::smultt, cond, rd, rn, rm);
10650 void Assembler::smulwb(Condition cond, Register rd, Register rn, Register rm) {
10654     // SMULWB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
10655     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10656       EmitT32_32(0xfb30f000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10662     // SMULWB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
10664         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10665       EmitA32(0x012000a0U | (cond.GetCondition() << 28) | (rd.GetCode() << 16) |
10670   Delegate(kSmulwb, &Assembler::smulwb, cond, rd, rn, rm);
10673 void Assembler::smulwt(Condition cond, Register rd, Register rn, Register rm) {
10677     // SMULWT{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
10678     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10679       EmitT32_32(0xfb30f010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10685     // SMULWT{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
10687         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10688       EmitA32(0x012000e0U | (cond.GetCondition() << 28) | (rd.GetCode() << 16) |
10693   Delegate(kSmulwt, &Assembler::smulwt, cond, rd, rn, rm);
10696 void Assembler::smusd(Condition cond, Register rd, Register rn, Register rm) {
10700     // SMUSD{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
10701     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10702       EmitT32_32(0xfb40f000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10708     // SMUSD{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
10710         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10711       EmitA32(0x0700f050U | (cond.GetCondition() << 28) | (rd.GetCode() << 16) |
10716   Delegate(kSmusd, &Assembler::smusd, cond, rd, rn, rm);
10719 void Assembler::smusdx(Condition cond, Register rd, Register rn, Register rm) {
10723     // SMUSDX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
10724     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10725       EmitT32_32(0xfb40f010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10731     // SMUSDX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
10733         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10734       EmitA32(0x0700f070U | (cond.GetCondition() << 28) | (rd.GetCode() << 16) |
10739   Delegate(kSmusdx, &Assembler::smusdx, cond, rd, rn, rm);
10743                      Register rd,
10753       // SSAT{<c>}{<q>} <Rd>, #<imm>, <Rn>, ASR #<amount> ; T1
10756           ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
10758         EmitT32_32(0xf3200000U | (rd.GetCode() << 8) | imm_ |
10764       // SSAT{<c>}{<q>} <Rd>, #<imm>, <Rn> {, LSL #<amount> } ; T1
10766           ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
10768         EmitT32_32(0xf3000000U | (rd.GetCode() << 8) | imm_ |
10775       // SSAT{<c>}{<q>} <Rd>, #<imm>, <Rn>, ASR #<amount> ; A1
10778           ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
10782                 (rd.GetCode() << 12) | (imm_ << 16) | rn.GetCode() |
10786       // SSAT{<c>}{<q>} <Rd>, #<imm>, <Rn> {, LSL #<amount> } ; A1
10789           ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
10792                 (rd.GetCode() << 12) | (imm_ << 16) | rn.GetCode() |
10798   Delegate(kSsat, &Assembler::ssat, cond, rd, imm, operand);
10801 void Assembler::ssat16(Condition cond, Register rd, uint32_t imm, Register rn) {
10805     // SSAT16{<c>}{<q>} <Rd>, #<imm>, <Rn> ; T1
10807         ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
10809       EmitT32_32(0xf3200000U | (rd.GetCode() << 8) | imm_ |
10815     // SSAT16{<c>}{<q>} <Rd>, #<imm>, <Rn> ; A1
10817         ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
10819       EmitA32(0x06a00f30U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
10824   Delegate(kSsat16, &Assembler::ssat16, cond, rd, imm, rn);
10827 void Assembler::ssax(Condition cond, Register rd, Register rn, Register rm) {
10831     // SSAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
10832     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10833       EmitT32_32(0xfae0f000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10839     // SSAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
10841         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10842       EmitA32(0x06100f50U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
10847   Delegate(kSsax, &Assembler::ssax, cond, rd, rn, rm);
10850 void Assembler::ssub16(Condition cond, Register rd, Register rn, Register rm) {
10854     // SSUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
10855     if (((!rd
10856       EmitT32_32(0xfad0f000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10862     // SSUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
10864         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10865       EmitA32(0x06100f70U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
10870   Delegate(kSsub16, &Assembler::ssub16, cond, rd, rn, rm);
10873 void Assembler::ssub8(Condition cond, Register rd, Register rn, Register rm) {
10877     // SSUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
10878     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10879       EmitT32_32(0xfac0f000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10885     // SSUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
10887         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10888       EmitA32(0x06100ff0U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
10893   Delegate(kSsub8, &Assembler::ssub8, cond, rd, rn, rm);
10949                       Register rd,
10957       // STLEX{<c>}{<q>} <Rd>, <Rt>, [<Rn>] ; T1
10959           ((!rd.IsPC() && !rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
10960         EmitT32_32(0xe8c00fe0U | rd.GetCode() | (rt.GetCode() << 12) |
10966       // STLEX{<c>}{<q>} <Rd>, <Rt>, [<Rn>] ; A1
10968           ((!rd.IsPC() && !rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
10970                 (rd.GetCode() << 12) | rt.GetCode() | (rn.GetCode() << 16));
10975   Delegate(kStlex, &Assembler::stlex, cond, rd, rt, operand);
10979                        Register rd,
10987       // STLEXB{<c>}{<q>} <Rd>, <Rt>, [<Rn>] ; T1
10989           ((!rd.IsPC() && !rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
10990         EmitT32_32(0xe8c00fc0U | rd.GetCode() | (rt.GetCode() << 12) |
10996       // STLEXB{<c>}{<q>} <Rd>, <Rt>, [<Rn>] ; A1
10998           ((!rd.IsPC() && !rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
11000                 (rd.GetCode() << 12) | rt.GetCode() | (rn.GetCode() << 16));
11005   Delegate(kStlexb, &Assembler::stlexb, cond, rd, rt, operand);
11009                        Register rd,
11018       // STLEXD{<c>}{<q>} <Rd>, <Rt>, <Rt2>, [<Rn>] ; T1
11020           ((!rd.IsPC() && !rt.IsPC() && !rt2.IsPC() && !rn.IsPC()) ||
11022         EmitT32_32(0xe8c000f0U | rd.GetCode() | (rt.GetCode() << 12) |
11028       // STLEXD{<c>}{<q>} <Rd>, <Rt>, <Rt2>, [<Rn>] ; A1
11031           ((!rd.IsPC() && ((rt.GetCode() & 1) == 0) && !rt2.IsPC() &&
11035                 (rd.GetCode() << 12) | rt.GetCode() | (rn.GetCode() << 16));
11040   Delegate(kStlexd, &Assembler::stlexd, cond, rd, rt, rt2, operand);
11044                        Register rd,
11052       // STLEXH{<c>}{<q>} <Rd>, <Rt>, [<Rn>] ; T1
11054           ((!rd.IsPC() && !rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
11055         EmitT32_32(0xe8c00fd0U | rd.GetCode() | (rt.GetCode() << 12) |
11061       // STLEXH{<c>}{<q>} <Rd>, <Rt>, [<Rn>] ; A1
11063           ((!rd.IsPC() && !rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
11065                 (rd.GetCode() << 12) | rt.GetCode() | (rn.GetCode() << 16));
11070   Delegate(kStlexh, &Assembler::stlexh, cond, rd, rt, operand);
11782                       Register rd,
11791       // STREX{<c>}{<q>} <Rd>, <Rt>, [<Rn>{, #<imm>}] ; T1
11794           ((!rd.IsPC() && !rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
11796         EmitT32_32(0xe8400000U | (rd.GetCode() << 8) | (rt.GetCode() << 12) |
11802       // STREX{<c>}{<q>} <Rd>, <Rt>, [<Rn>{, #<imm_1>}] ; A1
11804           ((!rd.IsPC() && !rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
11806                 (rd.GetCode() << 12) | rt.GetCode() | (rn.GetCode() << 16));
11811   Delegate(kStrex, &Assembler::strex, cond, rd, rt, operand);
11815                        Register rd,
11823       // STREXB{<c>}{<q>} <Rd>, <Rt>, [<Rn>] ; T1
11825           ((!rd.IsPC() && !rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
11826         EmitT32_32(0xe8c00f40U | rd.GetCode() | (rt.GetCode() << 12) |
11832       // STREXB{<c>}{<q>} <Rd>, <Rt>, [<Rn>] ; A1
11834           ((!rd.IsPC() && !rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
11836                 (rd.GetCode() << 12) | rt.GetCode() | (rn.GetCode() << 16));
11841   Delegate(kStrexb, &Assembler::strexb, cond, rd, rt, operand);
11845                        Register rd,
11854       // STREXD{<c>}{<q>} <Rd>, <Rt>, <Rt2>, [<Rn>] ; T1
11856           ((!rd.IsPC() && !rt.IsPC() && !rt2.IsPC() && !rn.IsPC()) ||
11858         EmitT32_32(0xe8c00070U | rd.GetCode() | (rt.GetCode() << 12) |
11864       // STREXD{<c>}{<q>} <Rd>, <Rt>, <Rt2>, [<Rn>] ; A1
11867           ((!rd.IsPC() && ((rt.GetCode() & 1) == 0) && !rt2.IsPC() &&
11871                 (rd.GetCode() << 12) | rt.GetCode() | (rn.GetCode() << 16));
11876   Delegate(kStrexd, &Assembler::strexd, cond, rd, rt, rt2, operand);
11880                        Register rd,
11888       // STREXH{<c>}{<q>} <Rd>, <Rt>, [<Rn>] ; T1
11890           ((!rd.IsPC() && !rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
11891         EmitT32_32(0xe8c00f50U | rd.GetCode() | (rt.GetCode() << 12) |
11897       // STREXH{<c>}{<q>} <Rd>, <Rt>, [<Rn>] ; A1
11899           ((!rd.IsPC() && !rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
11901                 (rd.GetCode() << 12) | rt.GetCode() | (rn.GetCode() << 16));
11906   Delegate(kStrexh, &Assembler::strexh, cond, rd, rt, operand);
12067 rd,
12076       // SUB<c>{<q>} <Rd>, <Rn>, #<imm3> ; T1
12077       if (InITBlock() && !size.IsWide() && rd.IsLow() && rn.IsLow() &&
12079         EmitT32_16(0x1e00 | rd.GetCode() | (rn.GetCode() << 3) | (imm << 6));
12084       if (InITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() &&
12086         EmitT32_16(0x3800 | (rd.GetCode() << 8) | imm);
12091       if (!size.IsWide() && rd.Is(sp) && rn.Is(sp) && (imm <= 508) &&
12098       // SUB{<c>}{<q>} <Rd>, PC, #<imm12> ; T2
12100           (!rd.IsPC() || AllowUnpredictable())) {
12101         EmitT32_32(0xf2af0000U | (rd.GetCode() << 8) | (imm & 0xff) |
12106       // SUB{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T3
12108           ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
12109         EmitT32_32(0xf1a00000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
12116       // SUB{<c>}{<q>} {<Rd>}, <Rn>, #<imm12> ; T4
12118           (!rd.IsPC() || AllowUnpredictable())) {
12119         EmitT32_32(0xf2a00000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
12124       // SUB{<c>}{<q>} {<Rd>}, SP, #<const> ; T2
12126           (!rd.IsPC() || AllowUnpredictable())) {
12127         EmitT32_32(0xf1ad0000U | (rd.GetCode() << 8) |
12134       // SUB{<c>}{<q>} {<Rd>}, SP, #<imm12> ; T3
12136           (!rd.IsPC() || AllowUnpredictable())) {
12137         EmitT32_32(0xf2ad0000U | (rd.GetCode() << 8) | (imm & 0xff) |
12144       // SUB{<c>}{<q>} <Rd>, PC, #<const> ; A2
12147                 (rd.GetCode() << 12) | immediate_a32.GetEncodingValue());
12150       // SUB{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
12154                 (rd.GetCode() << 12) | (rn.GetCode() << 16) |
12158       // SUB{<c>}{<q>} {<Rd>}, SP, #<const> ; A1
12161                 (rd.GetCode() << 12) | immediate_a32.GetEncodingValue());
12170         // SUB<c>{<q>} <Rd>, <Rn>, <Rm> ; T1
12171         if (InITBlock() && !size.IsWide() && rd.IsLow() && rn.IsLow() &&
12173           EmitT32_16(0x1a00 | rd.GetCode() | (rn.GetCode() << 3) |
12178         // SUB{<c>} {<Rd>}, SP, <Rm> ; T1
12179         if (rn.Is(sp) && ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12180           EmitT32_32(0xebad0000U | (rd.GetCode() << 8) | rm.GetCode());
12189       // SUB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
12191           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12193         EmitT32_32(0xeba00000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
12199       // SUB{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T1
12201           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12203         EmitT32_32(0xebad0000U | (rd.GetCode() << 8) | rm.GetCode() |
12210       // SUB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
12214                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
12218       // SUB{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; A1
12222                 (rd.GetCode() << 12) | rm.GetCode() |
12233       // SUB{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
12235           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
12238                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
12244   Delegate(kSub, &Assembler::sub, cond, size, rd, rn, operand);
12247 void Assembler::sub(Condition cond, Register rd, const Operand& operand) {
12254       if (InITBlock() && rd.IsLow() && (imm <= 255)) {
12255         EmitT32_16(0x3800 | (rd.GetCode() << 8) | imm);
12261   Delegate(kSub, &Assembler::sub, cond, rd, operand);
12266                      Register rd,
12275       // SUBS{<q>} <Rd>, <Rn>, #<imm3> ; T1
12276       if (OutsideITBlock() && !size.IsWide() && rd.IsLow() && rn.IsLow() &&
12278         EmitT32_16(0x1e00 | rd.GetCode() | (rn.GetCode() << 3) | (imm << 6));
12283       if (OutsideITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() &&
12285         EmitT32_16(0x3800 | (rd.GetCode() << 8) | imm);
12289       // SUBS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T3
12291           !rd.Is(pc) && (!rn.IsPC() || AllowUnpredictable())) {
12292         EmitT32_32(0xf1b00000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
12300       if (!size.IsNarrow() && rd.Is(pc) && rn.Is(lr) && (imm <= 255) &&
12306       // SUBS{<c>}{<q>} {<Rd>}, SP, #<const> ; T2
12308           !rd.Is(pc)) {
12309         EmitT32_32(0xf1bd0000U | (rd.GetCode() << 8) |
12318       // SUBS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
12321                 (rd.GetCode() << 12) | (rn.GetCode() << 16) |
12325       // SUBS{<c>}{<q>} {<Rd>}, SP, #<const> ; A1
12328                 (rd.GetCode() << 12) | immediate_a32.GetEncodingValue());
12337         // SUBS{<q>} {<Rd>}, <Rn>, <Rm> ; T1
12338         if (OutsideITBlock() && !size.IsWide() && rd.IsLow() && rn.IsLow() &&
12340           EmitT32_16(0x1a00 | rd.GetCode() | (rn.GetCode() << 3) |
12350       // SUBS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
12352           !rd.Is(pc) && ((!rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12354         EmitT32_32(0xebb00000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
12360       // SUBS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T1
12362           !rd.Is(pc) && (!rm.IsPC() || AllowUnpredictable())) {
12364         EmitT32_32(0xebbd0000U | (rd.GetCode() << 8) | rm.GetCode() |
12371       // SUBS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
12375                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
12379       // SUBS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; A1
12383                 (rd.GetCode() << 12) | rm.GetCode() |
12394       // SUBS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
12396           ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
12399                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
12405   Delegate(kSubs, &Assembler::subs, cond, size, rd, rn, operand);
12408 void Assembler::subs(Register rd, const Operand& operand) {
12415       if (OutsideITBlock() && rd.IsLow() && (imm <= 255)) {
12416         EmitT32_16(0x3800 | (rd.GetCode() << 8) | imm);
12422   Delegate(kSubs, &Assembler::subs, rd, operand);
12426                      Register rd,
12434       // SUBW{<c>}{<q>} {<Rd>}, <Rn>, #<imm12> ; T4
12436           (!rd.IsPC() || AllowUnpredictable())) {
12437         EmitT32_32(0xf2a00000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
12442       // SUBW{<c>}{<q>} {<Rd>}, SP, #<imm12> ; T3
12443       if (rn.Is(sp) && (imm <= 4095) && (!rd.IsPC() || AllowUnpredictable())) {
12444         EmitT32_32(0xf2ad0000U | (rd.GetCode() << 8) | (imm & 0xff) |
12451   Delegate(kSubw, &Assembler::subw, cond, rd, rn, operand);
12475                       Register rd,
12485       // SXTAB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1
12488           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12490         EmitT32_32(0xfa40f080U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
12496       // SXTAB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; A1
12499           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12502                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
12508   Delegate(kSxtab, &Assembler::sxtab, cond, rd, rn, operand);
12512                         Register rd,
12522       // SXTAB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1
12525           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12527         EmitT32_32(0xfa20f080U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
12533       // SXTAB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; A1
12536           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12539                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
12545   Delegate(kSxtab16, &Assembler::sxtab16, cond, rd, rn, operand);
12549                       Register rd,
12559       // SXTAH{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1
12562           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12564         EmitT32_32(0xfa00f080U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
12570       // SXTAH{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; A1
12573           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12576                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
12582   Delegate(kSxtah, &Assembler::sxtah, cond, rd, rn, operand);
12587                      Register rd,
12595         // SXTB{<c>}{<q>} {<Rd>}, <Rm> ; T1
12596         if (!size.IsWide() && rd.IsLow() && rm.IsLow()) {
12597           EmitT32_16(0xb240 | rd.GetCode() | (rm.GetCode() << 3));
12606       // SXTB{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; T2
12609           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12611         EmitT32_32(0xfa4ff080U | (rd.GetCode() << 8) | rm.GetCode() |
12617       // SXTB{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; A1
12620           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12623                 (rd.GetCode() << 12) | rm.GetCode() | (amount_ << 10));
12628   Delegate(kSxtb, &Assembler::sxtb, cond, size, rd, operand);
12631 void Assembler::sxtb16(Condition cond, Register rd, const Operand& operand) {
12639       // SXTB16{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; T1
12642           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12644         EmitT32_32(0xfa2ff080U | (rd.GetCode() << 8) | rm.GetCode() |
12650       // SXTB16{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; A1
12653           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12656                 (rd.GetCode() << 12) | rm.GetCode() | (amount_ << 10));
12661   Delegate(kSxtb16, &Assembler::sxtb16, cond, rd, operand);
12666                      Register rd,
12674         // SXTH{<c>}{<q>} {<Rd>}, <Rm> ; T1
12675         if (!size.IsWide() && rd.IsLow() && rm.IsLow()) {
12676           EmitT32_16(0xb200 | rd.GetCode() | (rm.GetCode() << 3));
12685       // SXTH{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; T2
12688           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12690         EmitT32_32(0xfa0ff080U | (rd.GetCode() << 8) | rm.GetCode() |
12696       // SXTH{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; A1
12699           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12702                 (rd.GetCode() << 12) | rm.GetCode() | (amount_ << 10));
12707   Delegate(kSxth, &Assembler::sxth, cond, size, rd, operand);
12894 void Assembler::uadd16(Condition cond, Register rd, Register rn, Register rm) {
12898     // UADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
12899     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12900       EmitT32_32(0xfa90f040U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
12906     // UADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
12908         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12909       EmitA32(0x06500f10U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
12914   Delegate(kUadd16, &Assembler::uadd16, cond, rd, rn, rm);
12917 void Assembler::uadd8(Condition cond, Register rd, Register rn, Register rm) {
12921     // UADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
12922     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12923       EmitT32_32(0xfa80f040U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
12929     // UADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
12931         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12932       EmitA32(0x06500f90U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
12937   Delegate(kUadd8, &Assembler::uadd8, cond, rd, rn, rm);
12940 void Assembler::uasx(Condition cond, Register rd, Register rn, Register rm) {
12944     // UASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
12945     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12946       EmitT32_32(0xfaa0f040U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
12952     // UASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
12954         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12955       EmitA32(0x06500f30U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
12960   Delegate(kUasx, &Assembler::uasx, cond, rd, rn, rm);
12964     Condition cond, Register rd, Register rn, uint32_t lsb, uint32_t width) {
12968     // UBFX{<c>}{<q>} <Rd>, <Rn>, #<lsb>, #<width> ; T1
12970         (((width >= 1) && (width <= 32 - lsb) && !rd.IsPC() && !rn.IsPC()) ||
12973       EmitT32_32(0xf3c00000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
12979     // UBFX{<c>}{<q>} <Rd>, <Rn>, #<lsb>, #<width> ; A1
12981         (((width >= 1) && (width <= 32 - lsb) && !rd.IsPC() && !rn.IsPC()) ||
12984       EmitA32(0x07e00050U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
12989   Delegate(kUbfx, &Assembler::ubfx, cond, rd, rn, lsb, width);
13024 void Assembler::udiv(Condition cond, Register rd, Register rn, Register rm) {
13028     // UDIV{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
13029     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13030       EmitT32_32(0xfbb0f0f0U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
13036     // UDIV{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
13038         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13039       EmitA32(0x0730f010U | (cond.GetCondition() << 28) | (rd.GetCode() << 16) |
13044   Delegate(kUdiv, &Assembler::udiv, cond, rd, rn, rm);
13047 void Assembler::uhadd16(Condition cond, Register rd, Register rn, Register rm) {
13051     // UHADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
13052     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13053       EmitT32_32(0xfa90f060U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
13059     // UHADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
13061         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13062       EmitA32(0x06700f10U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
13067   Delegate(kUhadd16, &Assembler::uhadd16, cond, rd, rn, rm);
13070 void Assembler::uhadd8(Condition cond, Register rd, Register rn, Register rm) {
13074     // UHADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
13075     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13076       EmitT32_32(0xfa80f060U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
13082     // UHADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
13084         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13085       EmitA32(0x06700f90U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
13090   Delegate(kUhadd8, &Assembler::uhadd8, cond, rd, rn, rm);
13093 void Assembler::uhasx(Condition cond, Register rd, Register rn, Register rm) {
13097     // UHASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
13098     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13099       EmitT32_32(0xfaa0f060U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
13105     // UHASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
13107         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13108       EmitA32(0x06700f30U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
13113   Delegate(kUhasx, &Assembler::uhasx, cond, rd, rn, rm);
13116 void Assembler::uhsax(Condition cond, Register rd, Register rn, Register rm) {
13120     // UHSAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
13121     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13122       EmitT32_32(0xfae0f060U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
13128     // UHSAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
13130         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13131       EmitA32(0x06700f50U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
13136   Delegate(kUhsax, &Assembler::uhsax, cond, rd, rn, rm);
13139 void Assembler::uhsub16(Condition cond, Register rd, Register rn, Register rm) {
13143     // UHSUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
13144     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13145       EmitT32_32(0xfad0f060U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
13151     // UHSUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
13153         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13154       EmitA32(0x06700f70U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
13159   Delegate(kUhsub16, &Assembler::uhsub16, cond, rd, rn, rm);
13162 void Assembler::uhsub8(Condition cond, Register rd, Register rn, Register rm) {
13166     // UHSUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
13167     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13168       EmitT32_32(0xfac0f060U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
13174     // UHSUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
13176         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13177       EmitA32(0x06700ff0U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
13182   Delegate(kUhsub8, &Assembler::uhsub8, cond, rd, rn, rm);
13190     // UMAAL{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; T1
13199     // UMAAL{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; A1
13217     // UMLAL{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; T1
13226     // UMLAL{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; A1
13244     // UMLALS{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; A1
13262     // UMULL{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; T1
13271     // UMULL{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; A1
13289     // UMULLS{<c>}{<q>} <Rd>, <Rd>, <Rn>, <Rm> ; A1
13302 void Assembler::uqadd16(Condition cond, Register rd, Register rn, Register rm) {
13306     // UQADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
13307     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13308       EmitT32_32(0xfa90f050U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
13314     // UQADD16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
13316         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13317       EmitA32(0x06600f10U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
13322   Delegate(kUqadd16, &Assembler::uqadd16, cond, rd, rn, rm);
13325 void Assembler::uqadd8(Condition cond, Register rd, Register rn, Register rm) {
13329     // UQADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
13330     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13331       EmitT32_32(0xfa80f050U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
13337     // UQADD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
13339         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13340       EmitA32(0x06600f90U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
13345   Delegate(kUqadd8, &Assembler::uqadd8, cond, rd, rn, rm);
13348 void Assembler::uqasx(Condition cond, Register rd, Register rn, Register rm) {
13352     // UQASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
13353     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13354       EmitT32_32(0xfaa0f050U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
13360     // UQASX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
13362         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13363       EmitA32(0x06600f30U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
13368   Delegate(kUqasx, &Assembler::uqasx, cond, rd, rn, rm);
13371 void Assembler::uqsax(Condition cond, Register rd, Register rn, Register rm) {
13375     // UQSAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
13376     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13377       EmitT32_32(0xfae0f050U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
13383     // UQSAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
13385         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13386       EmitA32(0x06600f50U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
13391   Delegate(kUqsax, &Assembler::uqsax, cond, rd, rn, rm);
13394 void Assembler::uqsub16(Condition cond, Register rd, Register rn, Register rm) {
13398     // UQSUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
13399     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13400       EmitT32_32(0xfad0f050U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
13406     // UQSUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
13408         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13409       EmitA32(0x06600f70U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
13414   Delegate(kUqsub16, &Assembler::uqsub16, cond, rd, rn, rm);
13417 void Assembler::uqsub8(Condition cond, Register rd, Register rn, Register rm) {
13421     // UQSUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
13422     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13423       EmitT32_32(0xfac0f050U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
13429     // UQSUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
13431         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13432       EmitA32(0x06600ff0U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
13437   Delegate(kUqsub8, &Assembler::uqsub8, cond, rd, rn, rm);
13440 void Assembler::usad8(Condition cond, Register rd, Register rn, Register rm) {
13444     // USAD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
13445     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13446       EmitT32_32(0xfb70f000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
13452     // USAD8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
13454         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13455       EmitA32(0x0780f010U | (cond.GetCondition() << 28) | (rd.GetCode() << 16) |
13460   Delegate(kUsad8, &Assembler::usad8, cond, rd, rn, rm);
13464     Condition cond, Register rd, Register rn, Register rm, Register ra) {
13468     // USADA8{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; T1
13470         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13471       EmitT32_32(0xfb700000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
13477     // USADA8{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> ; A1
13479         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13480       EmitA32(0x07800010U | (cond.GetCondition() << 28) | (rd.GetCode() << 16) |
13485   Delegate(kUsada8, &Assembler::usada8, cond, rd, rn, rm, ra);
13489                      Register rd,
13499       // USAT{<c>}{<q>} <Rd>, #<imm>, <Rn>, ASR #<amount> ; T1
13501           ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
13502         EmitT32_32(0xf3a00000U | (rd.GetCode() << 8) | imm |
13508       // USAT{<c>}{<q>} <Rd>, #<imm>, <Rn> {, LSL #<amount> } ; T1
13510           ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
13511         EmitT32_32(0xf3800000U | (rd.GetCode() << 8) | imm |
13518       // USAT{<c>}{<q>} <Rd>, #<imm>, <Rn>, ASR #<amount> ; A1
13521           ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
13524                 (rd.GetCode() << 12) | (imm << 16) | rn.GetCode() |
13528       // USAT{<c>}{<q>} <Rd>, #<imm>, <Rn> {, LSL #<amount> } ; A1
13530           ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
13532                 (rd.GetCode() << 12) | (imm << 16) | rn.GetCode() |
13538   Delegate(kUsat, &Assembler::usat, cond, rd, imm, operand);
13541 void Assembler::usat16(Condition cond, Register rd, uint32_t imm, Register rn) {
13545     // USAT16{<c>}{<q>} <Rd>, #<imm>, <Rn> ; T1
13546     if ((imm <= 15) && ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
13547       EmitT32_32(0xf3a00000U | (rd.GetCode() << 8) | imm |
13553     // USAT16{<c>}{<q>} <Rd>, #<imm>, <Rn> ; A1
13555         ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
13556       EmitA32(0x06e00f30U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
13561   Delegate(kUsat16, &Assembler::usat16, cond, rd, imm, rn);
13564 void Assembler::usax(Condition cond, Register rd, Register rn, Register rm) {
13568     // USAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
13569     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13570       EmitT32_32(0xfae0f040U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
13576     // USAX{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
13578         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13579       EmitA32(0x06500f50U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
13584   Delegate(kUsax, &Assembler::usax, cond, rd, rn, rm);
13587 void Assembler::usub16(Condition cond, Register rd, Register rn, Register rm) {
13591     // USUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
13592     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13593       EmitT32_32(0xfad0f040U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
13599     // USUB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
13601         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13602       EmitA32(0x06500f70U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
13607   Delegate(kUsub16, &Assembler::usub16, cond, rd, rn, rm);
13610 void Assembler::usub8(Condition cond, Register rd, Register rn, Register rm) {
13614     // USUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; T1
13615     if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13616       EmitT32_32(0xfac0f040U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
13622     // USUB8{<c>}{<q>} {<Rd>}, <Rn>, <Rm> ; A1
13624         ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13625       EmitA32(0x06500ff0U | (cond.GetCondition() << 28) | (rd.GetCode() << 12) |
13630   Delegate(kUsub8, &Assembler::usub8, cond, rd, rn, rm);
13634                       Register rd,
13644       // UXTAB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1
13647           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13649         EmitT32_32(0xfa50f080U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
13655       // UXTAB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; A1
13658           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13661                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
13667   Delegate(kUxtab, &Assembler::uxtab, cond, rd, rn, operand);
13671                         Register rd,
13681       // UXTAB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1
13684           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13686         EmitT32_32(0xfa30f080U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
13692       // UXTAB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; A1
13695           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13698                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
13704   Delegate(kUxtab16, &Assembler::uxtab16, cond, rd, rn, operand);
13708                       Register rd,
13718       // UXTAH{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1
13721           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13723         EmitT32_32(0xfa10f080U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
13729       // UXTAH{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; A1
13732           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13735                 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
13741   Delegate(kUxtah, &Assembler::uxtah, cond, rd, rn, operand);
13746                      Register rd,
13754         // UXTB{<c>}{<q>} {<Rd>}, <Rm> ; T1
13755         if (!size.IsWide() && rd.IsLow() && rm.IsLow()) {
13756           EmitT32_16(0xb2c0 | rd.GetCode() | (rm.GetCode() << 3));
13765       // UXTB{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; T2
13768           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13770         EmitT32_32(0xfa5ff080U | (rd.GetCode() << 8) | rm.GetCode() |
13776       // UXTB{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; A1
13779           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13782                 (rd.GetCode() << 12) | rm.GetCode() | (amount_ << 10));
13787   Delegate(kUxtb, &Assembler::uxtb, cond, size, rd, operand);
13790 void Assembler::uxtb16(Condition cond, Register rd, const Operand& operand) {
13798       // UXTB16{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; T1
13801           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13803         EmitT32_32(0xfa3ff080U | (rd.GetCode() << 8) | rm.GetCode() |
13809       // UXTB16{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; A1
13812           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13815                 (rd.GetCode() << 12) | rm.GetCode() | (amount_ << 10));
13820   Delegate(kUxtb16, &Assembler::uxtb16, cond, rd, operand);
13825                      Register rd,
13833         // UXTH{<c>}{<q>} {<Rd>}, <Rm> ; T1
13834         if (!size.IsWide() && rd
13835           EmitT32_16(0xb280 | rd.GetCode() | (rm.GetCode() << 3));
13844       // UXTH{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; T2
13847           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13849         EmitT32_32(0xfa1ff080U | (rd.GetCode() << 8) | rm.GetCode() |
13855       // UXTH{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; A1
13858           ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13861                 (rd.GetCode() << 12) | rm.GetCode() | (amount_ << 10));
13866   Delegate(kUxth, &Assembler::uxth, cond, size, rd, operand);
13870     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
13880                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
13891                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
13896   Delegate(kVaba, &Assembler::vaba, cond, dt, rd, rn, rm);
13900     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
13910                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
13921                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
13926   Delegate(kVaba, &Assembler::vaba, cond, dt, rd, rn, rm);
13930     Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
13940                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
13951                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
13956   Delegate(kVabal, &Assembler::vabal, cond, dt, rd, rn, rm);
13960     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
13968         EmitT32_32(0xff200d00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
13979                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
13988         EmitA32(0xf3200d00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
13998                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14003   Delegate(kVabd, &Assembler::vabd, cond, dt, rd, rn, rm);
14007     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
14015         EmitT32_32(0xff200d40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14026                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14035         EmitA32(0xf3200d40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14045                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14050   Delegate(kVabd, &Assembler::vabd, cond, dt, rd, rn, rm);
14054     Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
14064                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14075                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14080   Delegate(kVabdl, &Assembler::vabdl, cond, dt, rd, rn, rm);
14083 void Assembler::vabs(Condition cond, DataType dt, DRegister rd, DRegister rm) {
14093                    rd.Encode(22, 12) | rm.Encode(5, 0));
14100       EmitT32_32(0xeeb00bc0U | rd.Encode(22, 12) | rm.Encode(5, 0));
14110                 rd.Encode(22, 12) | rm.Encode(5, 0));
14116       EmitA32(0x0eb00bc0U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
14121   Delegate(kVabs, &Assembler::vabs, cond, dt, rd, rm);
14124 void Assembler::vabs(Condition cond, DataType dt, QRegister rd, QRegister rm) {
14134                    rd.Encode(22, 12) | rm.Encode(5, 0));
14145                 rd.Encode(22, 12) | rm.Encode(5, 0));
14150   Delegate(kVabs, &Assembler::vabs, cond, dt, rd, rm);
14153 void Assembler::vabs(Condition cond, DataType dt, SRegister rd, SRegister rm) {
14159       EmitT32_32(0xeeb00ac0U | rd.Encode(22, 12) | rm.Encode(5, 0));
14166       EmitA32(0x0eb00ac0U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
14171   Delegate(kVabs, &Assembler::vabs, cond, dt, rd, rm);
14175     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
14182         EmitT32_32(0xff000e10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14192         EmitA32(0xf3000e10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14198   Delegate(kVacge, &Assembler::vacge, cond, dt, rd, rn, rm);
14202     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
14209         EmitT32_32(0xff000e50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14219         EmitA32(0xf3000e50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14225   Delegate(kVacge, &Assembler::vacge, cond, dt, rd, rn, rm);
14229     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
14236         EmitT32_32(0xff200e10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14246         EmitA32(0xf3200e10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14252   Delegate(kVacgt, &Assembler::vacgt, cond, dt, rd, rn, rm);
14256     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
14263         EmitT32_32(0xff200e50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14273         EmitA32(0xf3200e50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14279   Delegate(kVacgt, &Assembler::vacgt, cond, dt, rd, rn, rm);
14283     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
14290         EmitT32_32(0xff000e10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14300         EmitA32(0xf3000e10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14306   Delegate(kVacle, &Assembler::vacle, cond, dt, rd, rn, rm);
14310     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
14317         EmitT32_32(0xff000e50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14327         EmitA32(0xf3000e50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14333   Delegate(kVacle, &Assembler::vacle, cond, dt, rd, rn, rm);
14337     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
14344 rd.Encode(22, 12) | rn.Encode(7, 16) |
14354         EmitA32(0xf3200e10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14360   Delegate(kVaclt, &Assembler::vaclt, cond, dt, rd, rn, rm);
14364     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
14371         EmitT32_32(0xff200e50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14381         EmitA32(0xf3200e50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14387   Delegate(kVaclt, &Assembler::vaclt, cond, dt, rd, rn, rm);
14391     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
14399         EmitT32_32(0xef000d00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14407       EmitT32_32(0xee300b00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14416                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14425         EmitA32(0xf2000d00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14432       EmitA32(0x0e300b00U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
14440                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14445   Delegate(kVadd, &Assembler::vadd, cond, dt, rd, rn, rm);
14449     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
14457         EmitT32_32(0xef000d40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14467                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14476         EmitA32(0xf2000d40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14485                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14490   Delegate(kVadd, &Assembler::vadd, cond, dt, rd, rn, rm);
14494     Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
14500       EmitT32_32(0xee300a00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14508       EmitA32(0x0e300a00U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
14513   Delegate(kVadd, &Assembler::vadd, cond, dt, rd, rn, rm);
14517     Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) {
14526                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14536                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14541   Delegate(kVaddhn, &Assembler::vaddhn, cond, dt, rd, rn, rm);
14545     Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
14555                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14566                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14571   Delegate(kVaddl, &Assembler::vaddl, cond, dt, rd, rn, rm);
14575     Condition cond, DataType dt, QRegister rd, QRegister rn, DRegister rm) {
14585                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14596                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14601   Delegate(kVaddw, &Assembler::vaddw, cond, dt, rd, rn, rm);
14606                      DRegister rd,
14615       if (encoded_dt.IsValid() && rd.Is(rn)) {
14618                      rd.Encode(22, 12) |
14628       if (encoded_dt.IsValid() && rd.Is(rn)) {
14631                   rd.Encode(22, 12) | (encoded_dt.GetEncodedImmediate() & 0xf) |
14645         EmitT32_32(0xef000110U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14653         EmitA32(0xf2000110U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14659   Delegate(kVand, &Assembler::vand, cond, dt, rd, rn, operand);
14664                      QRegister rd,
14673       if (encoded_dt.IsValid() && rd.Is(rn)) {
14676                      rd.Encode(22, 12) |
14686       if (encoded_dt.IsValid() && rd.Is(rn)) {
14689                   rd.Encode(22, 12) | (encoded_dt.GetEncodedImmediate() & 0xf) |
14703         EmitT32_32(0xef000150U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14711         EmitA32(0xf2000150U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14717   Delegate(kVand, &Assembler::vand, cond, dt, rd, rn, operand);
14722                      DRegister rd,
14731       if (encoded_dt.IsValid() && rd.Is(rn)) {
14734                      rd.Encode(22, 12) |
14744       if (encoded_dt.IsValid() && rd.Is(rn)) {
14747                   rd.Encode(22, 12) | (encoded_dt.GetEncodedImmediate() & 0xf) |
14761         EmitT32_32(0xef100110U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14769         EmitA32(0xf2100110U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14775   Delegate(kVbic, &Assembler::vbic, cond, dt, rd, rn, operand);
14780                      QRegister rd,
14789       if (encoded_dt.IsValid() && rd.Is(rn)) {
14792                      rd.Encode(22, 12) |
14802       if (encoded_dt.IsValid() && rd.Is(rn)) {
14805                   rd.Encode(22, 12) | (encoded_dt.GetEncodedImmediate() & 0xf) |
14819         EmitT32_32(0xef100150U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14827         EmitA32(0xf2100150U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14833   Delegate(kVbic, &Assembler::vbic, cond, dt, rd, rn, operand);
14837     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
14844       EmitT32_32(0xff300110U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14852       EmitA32(0xf3300110U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14857   Delegate(kVbif, &Assembler::vbif, cond, dt, rd, rn, rm);
14861     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
14868       EmitT32_32(0xff300150U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14876       EmitA32(0xf3300150U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14881   Delegate(kVbif, &Assembler::vbif, cond, dt, rd, rn, rm);
14885     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
14892       EmitT32_32(0xff200110U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14900       EmitA32(0xf3200110U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14905   Delegate(kVbit, &Assembler::vbit, cond, dt, rd, rn, rm);
14909     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
14916       EmitT32_32(0xff200150U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14924       EmitA32(0xf3200150U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14929   Delegate(kVbit, &Assembler::vbit, cond, dt, rd, rn, rm);
14933     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
14940       EmitT32_32(0xff100110U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14948       EmitA32(0xf3100110U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14953   Delegate(kVbsl, &Assembler::vbsl, cond, dt, rd, rn, rm);
14957     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
14964       EmitT32_32(0xff100150U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14972       EmitA32(0xf3100150U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14977   Delegate(kVbsl, &Assembler::vbsl, cond, dt, rd, rn, rm);
14982                      DRegister rd,
14998                        rd.Encode(22, 12) | rm.Encode(5, 0));
15010                     rd.Encode(22, 12) | rm.Encode(5, 0));
15017   Delegate(kVceq, &Assembler::vceq, cond, dt, rd, rm, operand);
15022                      QRegister rd,
15038                        rd.Encode(22, 12) | rm.Encode(5, 0));
15050                     rd.Encode(22, 12) | rm.Encode(5, 0));
15057   Delegate(kVceq, &Assembler::vceq, cond, dt, rd, rm, operand);
15061     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
15071                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15080                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15090                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15098                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15103   Delegate(kVceq, &Assembler::vceq, cond, dt, rd, rn, rm);
15107     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
15117                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15126                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15136                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15144                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15149   Delegate(kVceq, &Assembler::vceq, cond, dt, rd, rn, rm);
15154                      DRegister rd,
15170                        rd.Encode(22, 12) | rm.Encode(5, 0));
15182                     rd.Encode(22, 12) | rm.Encode(5, 0));
15189   Delegate(kVcge, &Assembler::vcge, cond, dt, rd, rm, operand);
15194                      QRegister rd,
15210                        rd.Encode(22, 12) | rm.Encode(5, 0));
15222                     rd.Encode(22, 12) | rm.Encode(5, 0));
15229   Delegate(kVcge, &Assembler::vcge, cond, dt, rd, rm, operand);
15233     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
15243                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15251         EmitT32_32(0xff000e00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
15263                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15270         EmitA32(0xf3000e00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
15276   Delegate(kVcge, &Assembler::vcge, cond, dt, rd, rn, rm);
15280     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
15290                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15298         EmitT32_32(0xff000e40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
15310                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15317         EmitA32(0xf3000e40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
15323   Delegate(kVcge, &Assembler::vcge, cond, dt, rd, rn, rm);
15328 rd,
15344                        rd.Encode(22, 12) | rm.Encode(5, 0));
15356                     rd.Encode(22, 12) | rm.Encode(5, 0));
15363   Delegate(kVcgt, &Assembler::vcgt, cond, dt, rd, rm, operand);
15368                      QRegister rd,
15384                        rd.Encode(22, 12) | rm.Encode(5, 0));
15396                     rd.Encode(22, 12) | rm.Encode(5, 0));
15403   Delegate(kVcgt, &Assembler::vcgt, cond, dt, rd, rm, operand);
15407     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
15417                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15425         EmitT32_32(0xff200e00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
15437                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15444         EmitA32(0xf3200e00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
15450   Delegate(kVcgt, &Assembler::vcgt, cond, dt, rd, rn, rm);
15454     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
15464                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15472         EmitT32_32(0xff200e40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
15484                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15491         EmitA32(0xf3200e40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
15497   Delegate(kVcgt, &Assembler::vcgt, cond, dt, rd, rn, rm);
15502                      DRegister rd,
15518                        rd.Encode(22, 12) | rm.Encode(5, 0));
15530                     rd.Encode(22, 12) | rm.Encode(5, 0));
15537   Delegate(kVcle, &Assembler::vcle, cond, dt, rd, rm, operand);
15542                      QRegister rd,
15558                        rd.Encode(22, 12) | rm.Encode(5, 0));
15570                     rd.Encode(22, 12) | rm.Encode(5, 0));
15577   Delegate(kVcle, &Assembler::vcle, cond, dt, rd, rm, operand);
15581     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
15591                    rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16));
15599         EmitT32_32(0xff000e00U | rd.Encode(22, 12) | rn.Encode(5, 0) |
15611                 rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16));
15618         EmitA32(0xf3000e00U | rd.Encode(22, 12) | rn.Encode(5, 0) |
15624   Delegate(kVcle, &Assembler::vcle, cond, dt, rd, rn, rm);
15628     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
15638                    rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16));
15646         EmitT32_32(0xff000e40U | rd.Encode(22, 12) | rn.Encode(5, 0) |
15658                 rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16));
15665         EmitA32(0xf3000e40U | rd.Encode(22, 12) | rn.Encode(5, 0) |
15671   Delegate(kVcle, &Assembler::vcle, cond, dt, rd, rn, rm);
15674 void Assembler::vcls(Condition cond, DataType dt, DRegister rd, DRegister rm) {
15683                    rd.Encode(22, 12) | rm.Encode(5, 0));
15693                 rd.Encode(22, 12) | rm.Encode(5, 0));
15698   Delegate(kVcls, &Assembler::vcls, cond, dt, rd, rm);
15701 void Assembler::vcls(Condition cond, DataType dt, QRegister rd, QRegister rm) {
15710                    rd.Encode(22, 12) | rm.Encode(5, 0));
15720                 rd.Encode(22, 12) | rm.Encode(5, 0));
15725   Delegate(kVcls, &Assembler::vcls, cond, dt, rd, rm);
15730                      DRegister rd,
15746                        rd.Encode(22, 12) | rm.Encode(5, 0));
15758                     rd.Encode(22, 12) | rm.Encode(5, 0));
15765   Delegate(kVclt, &Assembler::vclt, cond, dt, rd, rm, operand);
15770                      QRegister rd,
15786                        rd.Encode(22, 12) | rm.Encode(5, 0));
15798                     rd.Encode(22, 12) | rm.Encode(5, 0));
15805   Delegate(kVclt, &Assembler::vclt, cond, dt, rd
15809     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
15819                    rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16));
15827         EmitT32_32(0xff200e00U | rd.Encode(22, 12) | rn.Encode(5, 0) |
15839                 rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16));
15846         EmitA32(0xf3200e00U | rd.Encode(22, 12) | rn.Encode(5, 0) |
15852   Delegate(kVclt, &Assembler::vclt, cond, dt, rd, rn, rm);
15856     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
15866                    rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16));
15874         EmitT32_32(0xff200e40U | rd.Encode(22, 12) | rn.Encode(5, 0) |
15886                 rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16));
15893         EmitA32(0xf3200e40U | rd.Encode(22, 12) | rn.Encode(5, 0) |
15899   Delegate(kVclt, &Assembler::vclt, cond, dt, rd, rn, rm);
15902 void Assembler::vclz(Condition cond, DataType dt, DRegister rd, DRegister rm) {
15911                    rd.Encode(22, 12) | rm.Encode(5, 0));
15921                 rd.Encode(22, 12) | rm.Encode(5, 0));
15926   Delegate(kVclz, &Assembler::vclz, cond, dt, rd, rm);
15929 void Assembler::vclz(Condition cond, DataType dt, QRegister rd, QRegister rm) {
15938                    rd.Encode(22, 12) | rm.Encode(5, 0));
15948                 rd.Encode(22, 12) | rm.Encode(5, 0));
15953   Delegate(kVclz, &Assembler::vclz, cond, dt, rd, rm);
15958                      SRegister rd,
15967         EmitT32_32(0xeeb40a40U | rd.Encode(22, 12) | rm.Encode(5, 0));
15974         EmitA32(0x0eb40a40U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
15984         EmitT32_32(0xeeb50a40U | rd.Encode(22, 12));
15991         EmitA32(0x0eb50a40U | (cond.GetCondition() << 28) | rd.Encode(22, 12));
15996   Delegate(kVcmp, &Assembler::vcmp, cond, dt, rd, operand);
16001                      DRegister rd,
16010         EmitT32_32(0xeeb40b40U | rd.Encode(22, 12) | rm.Encode(5, 0));
16017         EmitA32(0x0eb40b40U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
16027         EmitT32_32(0xeeb50b40U | rd.Encode(22, 12));
16034         EmitA32(0x0eb50b40U | (cond.GetCondition() << 28) | rd.Encode(22, 12));
16039   Delegate(kVcmp, &Assembler::vcmp, cond, dt, rd, operand);
16044                       SRegister rd,
16053         EmitT32_32(0xeeb40ac0U | rd.Encode(22, 12) | rm.Encode(5, 0));
16060         EmitA32(0x0eb40ac0U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
16070         EmitT32_32(0xeeb50ac0U | rd.Encode(22, 12));
16077         EmitA32(0x0eb50ac0U | (cond.GetCondition() << 28) | rd.Encode(22, 12));
16082   Delegate(kVcmpe, &Assembler::vcmpe, cond, dt, rd, operand);
16087                       DRegister rd,
16096         EmitT32_32(0xeeb40bc0U | rd.Encode(22, 12) | rm.Encode(5, 0));
16103         EmitA32(0x0eb40bc0U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
16113         EmitT32_32(0xeeb50bc0U | rd.Encode(22, 12));
16120         EmitA32(0x0eb50bc0U | (cond.GetCondition() << 28) | rd.Encode(22, 12));
16125   Delegate(kVcmpe, &Assembler::vcmpe, cond, dt, rd, operand);
16128 void Assembler::vcnt(Condition cond, DataType dt, DRegister rd, DRegister rm) {
16135         EmitT32_32(0xffb00500U | rd.Encode(22, 12) | rm.Encode(5, 0));
16144         EmitA32(0xf3b00500U | rd.Encode(22, 12) | rm.Encode(5, 0));
16149   Delegate(kVcnt, &Assembler::vcnt, cond, dt, rd, rm);
16152 void Assembler::vcnt(Condition cond, DataType dt, QRegister rd, QRegister rm) {
16159         EmitT32_32(0xffb00540U | rd.Encode(22, 12) | rm.Encode(5, 0));
16168         EmitA32(0xf3b00540U | rd.Encode(22, 12) | rm.Encode(5, 0));
16173   Delegate(kVcnt, &Assembler::vcnt, cond, dt, rd, rm);
16177     Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm) {
16184       EmitT32_32(0xeeb70ac0U | rd.Encode(22, 12) | rm.Encode(5, 0));
16191                  rd.Encode(22, 12) | rm.Encode(5, 0));
16198       EmitA32(0x0eb70ac0U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
16205               (encoded_dt.GetEncodingValue() << 7) | rd.Encode(22, 12) |
16210   Delegate(kVcvt, &Assembler::vcvt, cond, dt1, dt2, rd, rm);
16214     Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
16220       EmitT32_32(0xeeb70bc0U | rd.Encode(22, 12) | rm.Encode(5, 0));
16226       EmitT32_32(0xeebc0bc0U | rd.Encode(22, 12) | rm.Encode(5, 0));
16232       EmitT32_32(0xeebd0bc0U | rd.Encode(22, 12) | rm.Encode(5, 0));
16239       EmitA32(0x0eb70bc0U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
16245       EmitA32(0x0ebc0bc0U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
16251       EmitA32(0x0ebd0bc0U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
16256   Delegate(kVcvt, &Assembler::vcvt, cond, dt1, dt2, rd, rm);
16262                      DRegister rd,
16277                    rd.Encode(22, 12) | rm.Encode(5, 0) | (fbits_ << 16));
16283     if (dt1.Is(F64) && encoded_dt_2.IsValid() && rd.Is(rm) &&
16293                  rd.Encode(22, 12) | ((fbits_ & 0x1) << 5) |
16299     if (encoded_dt_3.IsValid() && dt2.Is(F64) && rd.Is(rm) &&
16309                  rd.Encode(22, 12) | ((fbits_ & 0x1) << 5) |
16321                 rd.Encode(22, 12) | rm.Encode(5, 0) | (fbits_ << 16));
16326     if (dt1.Is(F64) && encoded_dt_2.IsValid() && rd.Is(rm) &&
16338               rd.Encode(22, 12) | ((fbits_ & 0x1) << 5) |
16343     if (encoded_dt_3.IsValid() && dt2.Is(F64) && rd.Is(rm) &&
16355               rd.Encode(22, 12) | ((fbits_ & 0x1) << 5) |
16360   Delegate(kVcvt, &Assembler::vcvt, cond, dt1, dt2, rd, rm, fbits);
16366                      QRegister rd,
16379                    rd.Encode(22, 12) | rm.Encode(5, 0) | (fbits_ << 16));
16391                 rd.Encode(22, 12) | rm.Encode(5, 0) | (fbits_ << 16));
16396   Delegate(kVcvt, &Assembler::vcvt, cond, dt1, dt2, rd, rm, fbits);
16402                      SRegister rd,
16411     if (dt1.Is(F32) && encoded_dt.IsValid() && rd.Is(rm) &&
16421                  rd.Encode(22, 12) | ((fbits_ & 0x1) << 5) |
16427     if (encoded_dt_2.IsValid() && dt2.Is(F32) && rd.Is(rm) &&
16437                  rd.Encode(22, 12) | ((fbits_ & 0x1) << 5) |
16444     if (dt1.Is(F32) && encoded_dt.IsValid() && rd.Is(rm) &&
16456               rd.Encode(22, 12) | ((fbits_ & 0x1) << 5) |
16461     if (encoded_dt_2.IsValid() && dt2.Is(F32) && rd.Is(rm) &&
16473               rd.Encode(22, 12) | ((fbits_ & 0x1) << 5) |
16478   Delegate(kVcvt, &Assembler::vcvt, cond, dt1, dt2, rd, rm, fbits);
16482     Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
16491                    rd.Encode(22, 12) | rm.Encode(5, 0));
16501                 rd.Encode(22, 12) | rm.Encode(5, 0));
16506   Delegate(kVcvt, &Assembler::vcvt, cond, dt1, dt2, rd, rm);
16510     Condition cond, DataType dt1, DataType dt2, QRegister rd, QRegister rm) {
16519                    rd.Encode(22, 12) | rm.Encode(5, 0));
16529                 rd.Encode(22, 12) | rm.Encode(5, 0));
16534   Delegate(kVcvt, &Assembler::vcvt, cond, dt1, dt2, rd, rm);
16538     Condition cond, DataType dt1, DataType dt2, DRegister rd, QRegister rm) {
16545         EmitT32_32(0xffb60600U | rd.Encode(22, 12) | rm.Encode(5, 0));
16554         EmitA32(0xf3b60600U | rd.Encode(22, 12) | rm.Encode(5, 0));
16559   Delegate(kVcvt, &Assembler::vcvt, cond, dt1, dt2, rd, rm);
16563     Condition cond, DataType dt1, DataType dt2, QRegister rd, DRegister rm) {
16570         EmitT32_32(0xffb60700U | rd.Encode(22, 12) | rm.Encode(5, 0));
16579         EmitA32(0xf3b60700U | rd.Encode(22, 12) | rm.Encode(5, 0));
16584   Delegate(kVcvt, &Assembler::vcvt, cond, dt1, dt2, rd, rm);
16588     Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
16595       EmitT32_32(0xeebc0ac0U | rd.Encode(22, 12) | rm.Encode(5, 0));
16601       EmitT32_32(0xeebd0ac0U | rd.Encode(22, 12) | rm.Encode(5, 0));
16608                  rd.Encode(22, 12) | rm.Encode(5, 0));
16615       EmitA32(0x0ebc0ac0U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
16621       EmitA32(0x0ebd0ac0U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
16628               (encoded_dt.GetEncodingValue() << 7) | rd.Encode(22, 12) |
16633   Delegate(kVcvt, &Assembler::vcvt, cond, dt1, dt2, rd, rm);
16636 void Assembler::vcvta(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
16644                  rd.Encode(22, 12) | rm.Encode(5, 0));
16652               rd.Encode(22, 12) | rm.Encode(5, 0));
16656   Delegate(kVcvta, &Assembler::vcvta, dt1, dt2, rd, rm);
16659 void Assembler::vcvta(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {
16667                  rd.Encode(22, 12) | rm.Encode(5, 0));
16675               rd.Encode(22, 12) | rm.Encode(5, 0));
16679   Delegate(kVcvta, &Assembler::vcvta, dt1, dt2, rd, rm);
16682 void Assembler::vcvta(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
16690                  rd.Encode(22, 12) | rm.Encode(5, 0));
16698               rd.Encode(22, 12) | rm.Encode(5, 0));
16702   Delegate(kVcvta, &Assembler::vcvta, dt1, dt2, rd, rm);
16705 void Assembler::vcvta(DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
16713                  rd.Encode(22, 12) | rm.Encode(5, 0));
16721               rd.Encode(22, 12) | rm.Encode(5, 0));
16725   Delegate(kVcvta, &Assembler::vcvta, dt1, dt2, rd, rm);
16729     Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
16735       EmitT32_32(0xeeb20a40U | rd.Encode(22, 12) | rm.Encode(5, 0));
16741       EmitT32_32(0xeeb30a40U | rd.Encode(22, 12) | rm.Encode(5, 0));
16748       EmitA32(0x0eb20a40U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
16754       EmitA32(0x0eb30a40U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
16759   Delegate(kVcvtb, &Assembler::vcvtb, cond, dt1, dt2, rd, rm);
16763     Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm) {
16769       EmitT32_32(0xeeb20b40U | rd.Encode(22, 12) | rm.Encode(5, 0));
16776       EmitA32(0x0eb20b40U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
16781   Delegate(kVcvtb, &Assembler::vcvtb, cond, dt1, dt2, rd, rm);
16785     Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
16791       EmitT32_32(0xeeb30b40U | rd.Encode(22, 12) | rm.Encode(5, 0));
16798       EmitA32(0x0eb30b40U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
16803   Delegate(kVcvtb, &Assembler::vcvtb, cond, dt1, dt2, rd, rm);
16806 void Assembler::vcvtm(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
16814                  rd.Encode(22, 12) | rm.Encode(5, 0));
16822               rd.Encode(22, 12) | rm.Encode(5, 0));
16826   Delegate(kVcvtm, &Assembler::vcvtm, dt1, dt2, rd, rm);
16829 void Assembler::vcvtm(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {
16837                  rd.Encode(22, 12) | rm.Encode(5, 0));
16845               rd.Encode(22, 12) | rm.Encode(5, 0));
16849   Delegate(kVcvtm, &Assembler::vcvtm, dt1, dt2, rd, rm);
16852 void Assembler::vcvtm(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
16860                  rd.Encode(22, 12) | rm.Encode(5, 0));
16868               rd.Encode(22, 12) | rm.Encode(5, 0));
16872   Delegate(kVcvtm, &Assembler::vcvtm, dt1, dt2, rd, rm);
16875 void Assembler::vcvtm(DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
16883                  rd.Encode(22, 12) | rm.Encode(5, 0));
16891               rd.Encode(22, 12) | rm.Encode(5, 0));
16895   Delegate(kVcvtm, &Assembler::vcvtm, dt1, dt2, rd, rm);
16898 void Assembler::vcvtn(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
16906                  rd.Encode(22, 12) | rm.Encode(5, 0));
16914               rd.Encode(22, 12) | rm.Encode(5, 0));
16918   Delegate(kVcvtn, &Assembler::vcvtn, dt1, dt2, rd, rm);
16921 void Assembler::vcvtn(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {
16929                  rd.Encode(22, 12) | rm.Encode(5, 0));
16937               rd.Encode(22, 12) | rm.Encode(5, 0));
16941   Delegate(kVcvtn, &Assembler::vcvtn, dt1, dt2, rd, rm);
16944 void Assembler::vcvtn(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
16952                  rd.Encode(22, 12) | rm.Encode(5, 0));
16960               rd.Encode(22, 12) | rm.Encode(5, 0));
16964   Delegate(kVcvtn, &Assembler::vcvtn, dt1, dt2, rd, rm);
16967 void Assembler::vcvtn(DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
16975                  rd.Encode(22, 12) | rm.Encode(5, 0));
16983               rd.Encode(22, 12) | rm.Encode(5, 0));
16987   Delegate(kVcvtn, &Assembler::vcvtn, dt1, dt2, rd, rm);
16990 void Assembler::vcvtp(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
16998                  rd.Encode(22, 12) | rm.Encode(5, 0));
17006               rd.Encode(22, 12) | rm.Encode(5, 0));
17010   Delegate(kVcvtp, &Assembler::vcvtp, dt1, dt2, rd, rm);
17013 void Assembler::vcvtp(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {
17021                  rd.Encode(22, 12) | rm.Encode(5, 0));
17029               rd.Encode(22, 12) | rm.Encode(5, 0));
17033   Delegate(kVcvtp, &Assembler::vcvtp, dt1, dt2, rd, rm);
17036 void Assembler::vcvtp(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
17044                  rd.Encode(22, 12) | rm.Encode(5, 0));
17052               rd.Encode(22, 12) | rm.Encode(5, 0));
17056   Delegate(kVcvtp, &Assembler::vcvtp, dt1, dt2, rd, rm);
17059 void Assembler::vcvtp(DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
17067                  rd.Encode(22, 12) | rm.Encode(5, 0));
17075               rd.Encode(22, 12) | rm.Encode(5, 0));
17079   Delegate(kVcvtp, &Assembler::vcvtp, dt1, dt2, rd, rm);
17083     Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
17089       EmitT32_32(0xeebc0a40U | rd.Encode(22, 12) | rm.Encode(5, 0));
17095       EmitT32_32(0xeebd0a40U | rd.Encode(22, 12) | rm.Encode(5, 0));
17102       EmitA32(0x0ebc0a40U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
17108       EmitA32(0x0ebd0a40U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
17113   Delegate(kVcvtr, &Assembler::vcvtr, cond, dt1, dt2, rd, rm);
17117     Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
17123       EmitT32_32(0xeebc0b40U | rd.Encode(22, 12) | rm.Encode(5, 0));
17129       EmitT32_32(0xeebd0b40U | rd.Encode(22, 12) | rm.Encode(5, 0));
17136       EmitA32(0x0ebc0b40U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
17142       EmitA32(0x0ebd0b40U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
17147   Delegate(kVcvtr, &Assembler::vcvtr, cond, dt1, dt2, rd, rm);
17151     Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
17157       EmitT32_32(0xeeb20ac0U | rd.Encode(22, 12) | rm.Encode(5, 0));
17163       EmitT32_32(0xeeb30ac0U | rd.Encode(22, 12) | rm.Encode(5, 0));
17170       EmitA32(0x0eb20ac0U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
17176       EmitA32(0x0eb30ac0U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
17181   Delegate(kVcvtt, &Assembler::vcvtt, cond, dt1, dt2, rd, rm);
17185     Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm) {
17191       EmitT32_32(0xeeb20bc0U | rd.Encode(22, 12) | rm.Encode(5, 0));
17198       EmitA32(0x0eb20bc0U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
17203   Delegate(kVcvtt, &Assembler::vcvtt, cond, dt1, dt2, rd, rm);
17207     Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
17213       EmitT32_32(0xeeb30bc0U | rd.Encode(22, 12) | rm.Encode(5, 0));
17220       EmitA32(0x0eb30bc0U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
17225   Delegate(kVcvtt, &Assembler::vcvtt, cond, dt1, dt2, rd, rm);
17229     Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
17235       EmitT32_32(0xee800a00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17243       EmitA32(0x0e800a00U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
17248   Delegate(kVdiv, &Assembler::vdiv, cond, dt, rd, rn, rm);
17252     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
17258       EmitT32_32(0xee800b00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17266       EmitA32(0x0e800b00U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
17271   Delegate(kVdiv, &Assembler::vdiv, cond, dt, rd, rn, rm);
17274 void Assembler::vdup(Condition cond, DataType dt, QRegister rd, Register rt) {
17284                    rd.Encode(7, 16) | (rt.GetCode() << 12));
17297                 rd.Encode(7, 16) | (rt.GetCode() << 12));
17302 rd, rt);
17305 void Assembler::vdup(Condition cond, DataType dt, DRegister rd, Register rt) {
17315                    rd.Encode(7, 16) | (rt.GetCode() << 12));
17328                 rd.Encode(7, 16) | (rt.GetCode() << 12));
17333   Delegate(kVdup, &Assembler::vdup, cond, dt, rd, rt);
17338                      DRegister rd,
17348                    rd.Encode(22, 12) | rm.Encode(5, 0));
17358                 rd.Encode(22, 12) | rm.Encode(5, 0));
17363   Delegate(kVdup, &Assembler::vdup, cond, dt, rd, rm);
17368                      QRegister rd,
17378                    rd.Encode(22, 12) | rm.Encode(5, 0));
17388                 rd.Encode(22, 12) | rm.Encode(5, 0));
17393   Delegate(kVdup, &Assembler::vdup, cond, dt, rd, rm);
17397     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
17404       EmitT32_32(0xff000110U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17412       EmitA32(0xf3000110U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17417   Delegate(kVeor, &Assembler::veor, cond, dt, rd, rn, rm);
17421     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
17428       EmitT32_32(0xff000150U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17436       EmitA32(0xf3000150U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17441   Delegate(kVeor, &Assembler::veor, cond, dt, rd, rn, rm);
17446                      DRegister rd,
17459             EmitT32_32(0xefb00000U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17470             EmitT32_32(0xefb00000U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17480             EmitA32(0xf2b00000U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17490             EmitA32(0xf2b00000U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17498   Delegate(kVext, &Assembler::vext, cond, dt, rd, rn, rm, operand);
17503                      QRegister rd,
17516             EmitT32_32(0xefb00040U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17527             EmitT32_32(0xefb00040U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17537             EmitA32(0xf2b00040U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17547             EmitA32(0xf2b00040U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17555   Delegate(kVext, &Assembler::vext, cond, dt, rd, rn, rm, operand);
17559     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
17566         EmitT32_32(0xef000c10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17574       EmitT32_32(0xeea00b00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17583         EmitA32(0xf2000c10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17590       EmitA32(0x0ea00b00U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
17595   Delegate(kVfma, &Assembler::vfma, cond, dt, rd, rn, rm);
17599     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
17606         EmitT32_32(0xef000c50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17616         EmitA32(0xf2000c50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17622   Delegate(kVfma, &Assembler::vfma, cond, dt, rd, rn, rm);
17626     Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
17632       EmitT32_32(0xeea00a00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17640       EmitA32(0x0ea00a00U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
17645   Delegate(kVfma, &Assembler::vfma, cond, dt, rd, rn, rm);
17649     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
17656         EmitT32_32(0xef200c10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17664       EmitT32_32(0xeea00b40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17673         EmitA32(0xf2200c10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17680       EmitA32(0x0ea00b40U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
17685   Delegate(kVfms, &Assembler::vfms, cond, dt, rd, rn, rm);
17689     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
17696         EmitT32_32(0xef200c50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17706         EmitA32(0xf2200c50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17712   Delegate(kVfms, &Assembler::vfms, cond, dt, rd, rn, rm);
17716     Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
17722       EmitT32_32(0xeea00a40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17730       EmitA32(0x0ea00a40U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
17735   Delegate(kVfms, &Assembler::vfms, cond, dt, rd, rn, rm);
17739     Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
17745       EmitT32_32(0xee900a40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17753       EmitA32(0x0e900a40U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
17758   Delegate(kVfnma, &Assembler::vfnma, cond, dt, rd, rn, rm);
17762     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
17768       EmitT32_32(0xee900b40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17776       EmitA32(0x0e900b40U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
17781   Delegate(kVfnma, &Assembler::vfnma, cond, dt, rd, rn, rm);
17785     Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
17791       EmitT32_32(0xee900a00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17799       EmitA32(0x0e900a00U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
17804   Delegate(kVfnms, &Assembler::vfnms, cond, dt, rd, rn, rm);
17808     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
17814       EmitT32_32(0xee900b00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17822       EmitA32(0x0e900b00U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
17827   Delegate(kVfnms, &Assembler::vfnms, cond, dt, rd, rn, rm);
17831     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
17841                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
17852                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
17857   Delegate(kVhadd, &Assembler::vhadd, cond, dt, rd, rn, rm);
17861     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
17871                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
17882                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
17887   Delegate(kVhadd, &Assembler::vhadd, cond, dt, rd, rn, rm);
17891     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
17901                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
17912                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
17917   Delegate(kVhsub, &Assembler::vhsub, cond, dt, rd, rn, rm);
17921     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
17931                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
17942                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
17947   Delegate(kVhsub, &Assembler::vhsub, cond, dt, rd, rn, rm);
19558                      DRegister rd,
19589       EmitT32_32(Link(0xed1f0b00U | rd.Encode(22, 12),
19620           Link(0x0d1f0b00U | (cond.GetCondition() << 28) | rd.Encode(22, 12),
19627   Delegate(kVldr, &Assembler::vldr, cond, dt, rd, location);
19632                           DRegister rd,
19637   USE(rd);
19656                      DRegister rd,
19669         EmitT32_32(0xed1f0b00U | rd.Encode(22, 12) | offset_ | (sign << 23));
19679         EmitT32_32(0xed100b00U | rd.Encode(22, 12) | (rn.GetCode() << 16) |
19691         EmitA32(0x0d1f0b00U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
19701         EmitA32(0x0d100b00U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
19707   Delegate(kVldr, &Assembler::vldr, cond, dt, rd, operand);
19712                      SRegister rd,
19743       EmitT32_32(Link(0xed1f0a00U | rd.Encode(22, 12),
19774           Link(0x0d1f0a00U | (cond.GetCondition() << 28) | rd.Encode(22, 12),
19781   Delegate(kVldr, &Assembler::vldr, cond, dt, rd, location);
19786                           SRegister rd,
19791   USE(rd);
19810                      SRegister rd,
19823         EmitT32_32(0xed1f0a00U | rd.Encode(22, 12) | offset_ | (sign << 23));
19833         EmitT32_32(0xed100a00U | rd.Encode(22, 12) | (rn.GetCode() << 16) |
19845         EmitA32(0x0d1f0a00U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
19855         EmitA32(0x0d100a00U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
19861   Delegate(kVldr, &Assembler::vldr, cond, dt, rd, operand);
19865     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
19873         EmitT32_32(0xef000f00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
19884                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
19893         EmitA32(0xf2000f00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
19903                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
19908   Delegate(kVmax, &Assembler::vmax, cond, dt, rd, rn, rm);
19912     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
19920         EmitT32_32(0xef000f40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
19931                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
19940         EmitA32(0xf2000f40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
19950                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
19955   Delegate(kVmax, &Assembler::vmax, cond, dt, rd, rn, rm);
19958 void Assembler::vmaxnm(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
19964       EmitT32_32(0xff000f10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
19971       EmitT32_32(0xfe800b00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
19979       EmitA32(0xf3000f10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
19985       EmitA32(0xfe800b00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
19990   Delegate(kVmaxnm, &Assembler::vmaxnm, dt, rd, rn, rm);
19993 void Assembler::vmaxnm(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
19999       EmitT32_32(0xff000f50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20007       EmitA32(0xf3000f50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20012   Delegate(kVmaxnm, &Assembler::vmaxnm, dt, rd, rn, rm);
20015 void Assembler::vmaxnm(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
20021       EmitT32_32(0xfe800a00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20029       EmitA32(0xfe800a00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20034   Delegate(kVmaxnm, &Assembler::vmaxnm, dt, rd, rn, rm);
20038     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
20046         EmitT32_32(0xef200f00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20057                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
20066         EmitA32(0xf2200f00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20076                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
20081   Delegate(kVmin, &Assembler::vmin, cond, dt, rd, rn, rm);
20085     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
20093         EmitT32_32(0xef200f40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20104                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
20113         EmitA32(0xf2200f40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20123                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
20128   Delegate(kVmin, &Assembler::vmin, cond, dt, rd, rn, rm);
20131 void Assembler::vminnm(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
20137       EmitT32_32(0xff200f10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20144       EmitT32_32(0xfe800b40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20152       EmitA32(0xf3200f10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20158       EmitA32(0xfe800b40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20163   Delegate(kVminnm, &Assembler::vminnm, dt, rd, rn, rm);
20166 void Assembler::vminnm(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
20172       EmitT32_32(0xff200f50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20180       EmitA32(0xf3200f50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20185   Delegate(kVminnm, &Assembler::vminnm, dt, rd, rn, rm);
20188 void Assembler::vminnm(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
20194       EmitT32_32(0xfe800a40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20202       EmitA32(0xfe800a40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20207   Delegate(kVminnm, &Assembler::vminnm, dt, rd, rn, rm);
20211     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) {
20223                    (encoded_dt.GetEncodingValue() << 20) | rd.Encode(22, 12) |
20237                 (encoded_dt.GetEncodingValue() << 20) | rd.Encode(22, 12) |
20243   Delegate(kVmla, &Assembler::vmla, cond, dt, rd, rn, rm);
20247     Condition cond, DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) {
20259                    (encoded_dt.GetEncodingValue() << 20) | rd.Encode(22, 12) |
20273                 (encoded_dt.GetEncodingValue() << 20) | rd.Encode(22, 12) |
20279   Delegate(kVmla, &Assembler::vmla, cond, dt, rd, rn, rm);
20283     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
20291         EmitT32_32(0xef000d10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20299       EmitT32_32(0xee000b00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20308                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
20317         EmitA32(0xf2000d10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20324       EmitA32(0x0e000b00U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
20332                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
20337   Delegate(kVmla, &Assembler::vmla, cond, dt, rd, rn, rm);
20341     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
20349         EmitT32_32(0xef000d50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20359                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
20368         EmitA32(0xf2000d50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20377                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
20382   Delegate(kVmla, &Assembler::vmla, cond, dt, rd, rn, rm);
20386     Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
20392       EmitT32_32(0xee000a00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20400       EmitA32(0x0e000a00U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
20405   Delegate(kVmla, &Assembler::vmla, cond, dt, rd, rn, rm);
20409     Condition cond, DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) {
20421                    (encoded_dt.GetEncodingValue() << 20) | rd.Encode(22, 12) |
20435                 (encoded_dt.GetEncodingValue() << 20) | rd.Encode(22, 12) |
20441   Delegate(kVmlal, &Assembler::vmlal, cond, dt, rd, rn, rm);
20445     Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
20454                    (encoded_dt.GetEncodingValue() << 20) | rd.Encode(22, 12) |
20465                 (encoded_dt.GetEncodingValue() << 20) | rd.Encode(22, 12) |
20471   Delegate(kVmlal, &Assembler::vmlal, cond, dt, rd, rn, rm);
20475     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) {
20487                    (encoded_dt.GetEncodingValue() << 20) | rd.Encode(22, 12) |
20501                 (encoded_dt.GetEncodingValue() << 20) | rd.Encode(22, 12) |
20507   Delegate(kVmls, &Assembler::vmls, cond, dt, rd, rn, rm);
20511     Condition cond, DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) {
20523                    (encoded_dt.GetEncodingValue() << 20) | rd.Encode(22, 12) |
20537                 (encoded_dt.GetEncodingValue() << 20) | rd.Encode(22, 12) |
20543   Delegate(kVmls, &Assembler::vmls, cond, dt, rd, rn, rm);
20547     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
20555         EmitT32_32(0xef200d10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20563       EmitT32_32(0xee000b40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20572                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
20581         EmitA32(0xf2200d10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20588       EmitA32(0x0e000b40U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
20596                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
20601   Delegate(kVmls, &Assembler::vmls, cond, dt, rd, rn, rm);
20605     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
20613         EmitT32_32(0xef200d50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20623                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
20632         EmitA32(0xf2200d50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20641                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
20646   Delegate(kVmls, &Assembler::vmls, cond, dt, rd, rn, rm);
20650     Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
20656       EmitT32_32(0xee000a40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20664       EmitA32(0x0e000a40U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
20669   Delegate(kVmls, &Assembler::vmls, cond, dt, rd, rn, rm);
20673     Condition cond, DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) {
20685                    (encoded_dt.GetEncodingValue() << 20) | rd.Encode(22, 12) |
20699                 (encoded_dt.GetEncodingValue() << 20) | rd.Encode(22, 12) |
20705   Delegate(kVmlsl, &Assembler::vmlsl, cond, dt, rd, rn, rm);
20709     Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
20718                    (encoded_dt.GetEncodingValue() << 20) | rd.Encode(22, 12) |
20729                 (encoded_dt.GetEncodingValue() << 20) | rd.Encode(22, 12) |
20735   Delegate(kVmlsl, &Assembler::vmlsl, cond, dt, rd, rn, rm);
20880                      DRegisterLane rd,
20884   Dt_opc1_opc2_1 encoded_dt(dt, rd);
20890                  rd.Encode(7, 16) | (rt.GetCode() << 12));
20900               ((encoded_dt.GetEncodingValue() & 0xc) << 19) | rd.Encode(7, 16) |
20905   Delegate(kVmov, &Assembler::vmov, cond, dt, rd, rt);
20910                      DRegister rd,
20923               rd.Encode(22, 12) | (encoded_dt.GetEncodedImmediate() & 0xf) |
20936                   rd.Encode(22, 12) | (encoded_dt.GetEncodedImmediate() & 0xf) |
20949         EmitT32_32(0xeeb00b00U | rd.Encode(22, 12) |
20958         EmitA32(0x0eb00b00U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
20970         EmitT32_32(0xeeb00b40U | rd.Encode(22, 12) | rm.Encode(5, 0));
20977           EmitT32_32(0xef200110U | rd.Encode(22, 12) | rm.Encode(7, 16) |
20986         EmitA32(0x0eb00b40U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
20993           EmitA32(0xf2200110U | rd.Encode(22, 12) | rm.Encode(7, 16) |
21000   Delegate(kVmov, &Assembler::vmov, cond, dt, rd, operand);
21005                      QRegister rd,
21018               rd.Encode(22, 12) | (encoded_dt.GetEncodedImmediate() & 0xf) |
21031                   rd.Encode(22, 12) | (encoded_dt.GetEncodedImmediate() & 0xf) |
21045           EmitT32_32(0xef200150U | rd.Encode(22, 12) | rm.Encode(7, 16) |
21055           EmitA32(0xf2200150U | rd.Encode(22, 12) | rm.Encode(7, 16) |
21062   Delegate(kVmov, &Assembler::vmov, cond, dt, rd, operand);
21067                      SRegister rd,
21076         EmitT32_32(0xeeb00a00U | rd.Encode(22, 12) |
21085         EmitA32(0x0eb00a00U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
21097         EmitT32_32(0xeeb00a40U | rd.Encode(22, 12) | rm.Encode(5, 0));
21104         EmitA32(0x0eb00a40U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
21110   Delegate(kVmov, &Assembler::vmov, cond, dt, rd, operand);
21145 void Assembler::vmovl(Condition cond, DataType dt, QRegister rd, DRegister rm) {
21155                    rd.Encode(22, 12) | rm.Encode(5, 0));
21166                 rd.Encode(22, 12) | rm.Encode(5, 0));
21171   Delegate(kVmovl, &Assembler::vmovl, cond, dt, rd, rm);
21174 void Assembler::vmovn(Condition cond, DataType dt, DRegister rd, QRegister rm) {
21183                    rd.Encode(22, 12) | rm.Encode(5, 0));
21193                 rd.Encode(22, 12) | rm.Encode(5, 0));
21198   Delegate(kVmovn, &Assembler::vmovn, cond, dt, rd, rm);
21246                      DRegister rd,
21266                    rd.Encode(22, 12) | rn.Encode(7, 16) | (mvm & 0xf) |
21285                 rd.Encode(22, 12) | rn.Encode(7, 16) | (mvm & 0xf) |
21291   Delegate(kVmul, &Assembler::vmul, cond, dt, rd, rn, dm, index);
21296                      QRegister rd,
21316                    rd.Encode(22, 12) | rn.Encode(7, 16) | (mvm & 0xf) |
21335                 rd.Encode(22, 12) | rn.Encode(7, 16) | (mvm & 0xf) |
21341   Delegate(kVmul, &Assembler::vmul, cond, dt, rd, rn, dm, index);
21345     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
21353         EmitT32_32(0xff000d10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
21361       EmitT32_32(0xee200b00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
21371                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
21380         EmitA32(0xf3000d10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
21387       EmitA32(0x0e200b00U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
21396                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
21401   Delegate(kVmul, &Assembler::vmul, cond, dt, rd, rn, rm);
21405     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
21413         EmitT32_32(0xff000d50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
21424                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
21433         EmitA32(0xf3000d50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
21443                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
21448   Delegate(kVmul, &Assembler::vmul, cond, dt, rd, rn, rm);
21452     Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
21458       EmitT32_32(0xee200a00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
21466       EmitA32(0x0e200a00U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
21471   Delegate(kVmul, &Assembler::vmul, cond, dt, rd, rn, rm);
21476                       QRegister rd,
21497                    rd.Encode(22, 12) | rn.Encode(7, 16) | (mvm & 0xf) |
21517                 rd.Encode(22, 12) | rn.Encode(7, 16) | (mvm & 0xf) |
21523   Delegate(kVmull, &Assembler::vmull, cond, dt, rd, rn, dm, index);
21527     Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
21538                    rd
21550                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
21555   Delegate(kVmull, &Assembler::vmull, cond, dt, rd, rn, rm);
21560                      DRegister rd,
21571                      rd.Encode(22, 12) |
21584                   rd.Encode(22, 12) | (encoded_dt.GetEncodedImmediate() & 0xf) |
21598         EmitT32_32(0xffb00580U | rd.Encode(22, 12) | rm.Encode(5, 0));
21605         EmitA32(0xf3b00580U | rd.Encode(22, 12) | rm.Encode(5, 0));
21610   Delegate(kVmvn, &Assembler::vmvn, cond, dt, rd, operand);
21615                      QRegister rd,
21626                      rd.Encode(22, 12) |
21639                   rd.Encode(22, 12) | (encoded_dt.GetEncodedImmediate() & 0xf) |
21653         EmitT32_32(0xffb005c0U | rd.Encode(22, 12) | rm.Encode(5, 0));
21660         EmitA32(0xf3b005c0U | rd.Encode(22, 12) | rm.Encode(5, 0));
21665   Delegate(kVmvn, &Assembler::vmvn, cond, dt, rd, operand);
21668 void Assembler::vneg(Condition cond, DataType dt, DRegister rd, DRegister rm) {
21678                    rd.Encode(22, 12) | rm.Encode(5, 0));
21685       EmitT32_32(0xeeb10b40U | rd.Encode(22, 12) | rm.Encode(5, 0));
21695                 rd.Encode(22, 12) | rm.Encode(5, 0));
21701       EmitA32(0x0eb10b40U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
21706   Delegate(kVneg, &Assembler::vneg, cond, dt, rd, rm);
21709 void Assembler::vneg(Condition cond, DataType dt, QRegister rd, QRegister rm) {
21719                    rd.Encode(22, 12) | rm.Encode(5, 0));
21730                 rd.Encode(22, 12) | rm.Encode(5, 0));
21735   Delegate(kVneg, &Assembler::vneg, cond, dt, rd, rm);
21738 void Assembler::vneg(Condition cond, DataType dt, SRegister rd, SRegister rm) {
21744       EmitT32_32(0xeeb10a40U | rd.Encode(22, 12) | rm.Encode(5, 0));
21751       EmitA32(0x0eb10a40U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
21756   Delegate(kVneg, &Assembler::vneg, cond, dt, rd, rm);
21760     Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
21766       EmitT32_32(0xee100a40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
21774       EmitA32(0x0e100a40U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
21779   Delegate(kVnmla, &Assembler::vnmla, cond, dt, rd, rn, rm);
21783     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
21789       EmitT32_32(0xee100b40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
21797       EmitA32(0x0e100b40U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
21802   Delegate(kVnmla, &Assembler::vnmla, cond, dt, rd, rn, rm);
21806     Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
21812       EmitT32_32(0xee100a00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
21820       EmitA32(0x0e100a00U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
21825   Delegate(kVnmls, &Assembler::vnmls, cond, dt, rd, rn, rm);
21829     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
21835       EmitT32_32(0xee100b00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
21843       EmitA32(0x0e100b00U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
21848   Delegate(kVnmls, &Assembler::vnmls, cond, dt, rd, rn, rm);
21852     Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
21858       EmitT32_32(0xee200a40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
21866       EmitA32(0x0e200a40U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
21871   Delegate(kVnmul, &Assembler::vnmul, cond, dt, rd, rn, rm);
21875     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
21881       EmitT32_32(0xee200b40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
21889       EmitA32(0x0e200b40U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
21894   Delegate(kVnmul, &Assembler::vnmul, cond, dt, rd, rn, rm);
21899                      DRegister rd,
21908       if (encoded_dt.IsValid() && rd.Is(rn)) {
21911                      rd.Encode(22, 12) |
21921       if (encoded_dt.IsValid() && rd.Is(rn)) {
21924                   rd.Encode(22, 12) | (encoded_dt.GetEncodedImmediate() & 0xf) |
21938         EmitT32_32(0xef300110U | rd.Encode(22, 12) | rn.Encode(7, 16) |
21946         EmitA32(0xf2300110U | rd.Encode(22, 12) | rn.Encode(7, 16) |
21952   Delegate(kVorn, &Assembler::vorn, cond, dt, rd, rn, operand);
21957                      QRegister rd,
21966       if (encoded_dt.IsValid() && rd.Is(rn)) {
21969                      rd.Encode(22, 12) |
21979       if (encoded_dt.IsValid() && rd.Is(rn)) {
21982                   rd.Encode(22, 12) | (encoded_dt.GetEncodedImmediate() & 0xf) |
21996         EmitT32_32(0xef300150U | rd.Encode(22, 12) | rn.Encode(7, 16) |
22004         EmitA32(0xf2300150U | rd.Encode(22, 12) | rn.Encode(7, 16) |
22010   Delegate(kVorn, &Assembler::vorn, cond, dt, rd, rn, operand);
22015                      DRegister rd,
22026         EmitT32_32(0xef200110U | rd.Encode(22, 12) | rn.Encode(7, 16) |
22034         EmitA32(0xf2200110U | rd
22044       if (encoded_dt.IsValid() && rd.Is(rn)) {
22047                      rd.Encode(22, 12) |
22057       if (encoded_dt.IsValid() && rd.Is(rn)) {
22060                   rd.Encode(22, 12) | (encoded_dt.GetEncodedImmediate() & 0xf) |
22068   Delegate(kVorr, &Assembler::vorr, cond, dt, rd, rn, operand);
22073                      QRegister rd,
22084         EmitT32_32(0xef200150U | rd.Encode(22, 12) | rn.Encode(7, 16) |
22092         EmitA32(0xf2200150U | rd.Encode(22, 12) | rn.Encode(7, 16) |
22102       if (encoded_dt.IsValid() && rd.Is(rn)) {
22105                      rd.Encode(22, 12) |
22115       if (encoded_dt.IsValid() && rd.Is(rn)) {
22118                   rd.Encode(22, 12) | (encoded_dt.GetEncodedImmediate() & 0xf) |
22126   Delegate(kVorr, &Assembler::vorr, cond, dt, rd, rn, operand);
22131                        DRegister rd,
22142                    rd.Encode(22, 12) | rm.Encode(5, 0));
22153                 rd.Encode(22, 12) | rm.Encode(5, 0));
22158   Delegate(kVpadal, &Assembler::vpadal, cond, dt, rd, rm);
22163                        QRegister rd,
22174                    rd.Encode(22, 12) | rm.Encode(5, 0));
22185                 rd.Encode(22, 12) | rm.Encode(5, 0));
22190   Delegate(kVpadal, &Assembler::vpadal, cond, dt, rd, rm);
22194     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
22202         EmitT32_32(0xff000d00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
22212                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22221         EmitA32(0xf3000d00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
22230                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22235   Delegate(kVpadd, &Assembler::vpadd, cond, dt, rd, rn, rm);
22240                        DRegister rd,
22251                    rd.Encode(22, 12) | rm.Encode(5, 0));
22262                 rd.Encode(22, 12) | rm.Encode(5, 0));
22267   Delegate(kVpaddl, &Assembler::vpaddl, cond, dt, rd, rm);
22272                        QRegister rd,
22283                    rd.Encode(22, 12) | rm.Encode(5, 0));
22294                 rd.Encode(22, 12) | rm.Encode(5, 0));
22299   Delegate(kVpaddl, &Assembler::vpaddl, cond, dt, rd, rm);
22303     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
22311         EmitT32_32(0xff000f00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
22322                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22331         EmitA32(0xf3000f00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
22341                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22346   Delegate(kVpmax, &Assembler::vpmax, cond, dt, rd, rn, rm);
22350     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
22358         EmitT32_32(0xff200f00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
22369                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22378         EmitA32(0xf3200f00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
22388                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22393   Delegate(kVpmin, &Assembler::vpmin, cond, dt, rd, rn, rm);
22498 void Assembler::vqabs(Condition cond, DataType dt, DRegister rd, DRegister rm) {
22507                    rd.Encode(22, 12) | rm.Encode(5, 0));
22517                 rd.Encode(22, 12) | rm.Encode(5, 0));
22522   Delegate(kVqabs, &Assembler::vqabs, cond, dt, rd, rm);
22525 rd, QRegister rm) {
22534                    rd.Encode(22, 12) | rm.Encode(5, 0));
22544                 rd.Encode(22, 12) | rm.Encode(5, 0));
22549   Delegate(kVqabs, &Assembler::vqabs, cond, dt, rd, rm);
22553     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
22563                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22574                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22579   Delegate(kVqadd, &Assembler::vqadd, cond, dt, rd, rn, rm);
22583     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
22593                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22604                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22609   Delegate(kVqadd, &Assembler::vqadd, cond, dt, rd, rn, rm);
22613     Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
22622                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22632                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22637   Delegate(kVqdmlal, &Assembler::vqdmlal, cond, dt, rd, rn, rm);
22642                         QRegister rd,
22662                    rd.Encode(22, 12) | rn.Encode(7, 16) | (mvm & 0xf) |
22681                 rd.Encode(22, 12) | rn.Encode(7, 16) | (mvm & 0xf) |
22687   Delegate(kVqdmlal, &Assembler::vqdmlal, cond, dt, rd, rn, dm, index);
22691     Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
22700                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22710                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22715   Delegate(kVqdmlsl, &Assembler::vqdmlsl, cond, dt, rd, rn, rm);
22720                         QRegister rd,
22740                    rd.Encode(22, 12) | rn.Encode(7, 16) | (mvm & 0xf) |
22759                 rd.Encode(22, 12) | rn.Encode(7, 16) | (mvm & 0xf) |
22765   Delegate(kVqdmlsl, &Assembler::vqdmlsl, cond, dt, rd, rn, dm, index);
22769     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
22778                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22788                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22793   Delegate(kVqdmulh, &Assembler::vqdmulh, cond, dt, rd, rn, rm);
22797     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
22806                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22816                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22821   Delegate(kVqdmulh, &Assembler::vqdmulh, cond, dt, rd, rn, rm);
22825     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) {
22838                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
22852                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
22857   Delegate(kVqdmulh, &Assembler::vqdmulh, cond, dt, rd, rn, rm);
22861     Condition cond, DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) {
22874                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
22888                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
22893   Delegate(kVqdmulh, &Assembler::vqdmulh, cond, dt, rd, rn, rm);
22897     Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
22906                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22916                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22921   Delegate(kVqdmull, &Assembler::vqdmull, cond, dt, rd, rn, rm);
22925     Condition cond, DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) {
22938                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
22952                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
22957   Delegate(kVqdmull, &Assembler::vqdmull, cond, dt, rd, rn, rm);
22962                        DRegister rd,
22973                    rd.Encode(22, 12) | rm.Encode(5, 0));
22984                 rd.Encode(22, 12) | rm.Encode(5, 0));
22989   Delegate(kVqmovn, &Assembler::vqmovn, cond, dt, rd, rm);
22994                         DRegister rd,
23004                    rd.Encode(22, 12) | rm.Encode(5, 0));
23014                 rd.Encode(22, 12) | rm.Encode(5, 0));
23019   Delegate(kVqmovun, &Assembler::vqmovun, cond, dt, rd, rm);
23022 void Assembler::vqneg(Condition cond, DataType dt, DRegister rd, DRegister rm) {
23031                    rd.Encode(22, 12) | rm.Encode(5, 0));
23041                 rd.Encode(22, 12) | rm.Encode(5, 0));
23046   Delegate(kVqneg, &Assembler::vqneg, cond, dt, rd, rm);
23049 void Assembler::vqneg(Condition cond, DataType dt, QRegister rd, QRegister rm) {
23058                    rd.Encode(22, 12) | rm.Encode(5, 0));
23068                 rd.Encode(22, 12) | rm.Encode(5, 0));
23073   Delegate(kVqneg, &Assembler::vqneg, cond, dt, rd, rm);
23077     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
23086                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
23096                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
23101   Delegate(kVqrdmulh, &Assembler::vqrdmulh, cond, dt, rd, rn, rm);
23105     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
23114                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
23124                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
23129   Delegate(kVqrdmulh, &Assembler::vqrdmulh, cond, dt, rd, rn, rm);
23133     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) {
23146                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
23160                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
23165   Delegate(kVqrdmulh, &Assembler::vqrdmulh, cond, dt, rd, rn, rm);
23169     Condition cond, DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) {
23182                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
23196                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
23201   Delegate(kVqrdmulh, &Assembler::vqrdmulh, cond, dt, rd, rn, rm);
23205     Condition cond, DataType dt, DRegister rd, DRegister rm, DRegister rn) {
23215                    rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
23226                 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
23231   Delegate(kVqrshl, &Assembler::vqrshl, cond, dt, rd, rm, rn);
23235     Condition cond, DataType dt, QRegister rd, QRegister rm, QRegister rn) {
23245                    rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
23256                 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
23261   Delegate(kVqrshl, &Assembler::vqrshl, cond, dt, rd, rm, rn);
23266                         DRegister rd,
23283                        rd.Encode(22, 12) | rm.Encode(5, 0));
23295                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
23307                     rd.Encode(22, 12) | rm.Encode(5, 0));
23317                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
23324   Delegate(kVqrshrn, &Assembler::vqrshrn, cond, dt, rd, rm, operand);
23329                          DRegister rd,
23346                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
23355                        rd.Encode(22, 12) | rm.Encode(5, 0));
23367                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
23375                     rd.Encode(22, 12) | rm.Encode(5, 0));
23382   Delegate(kVqrshrun, &Assembler::vqrshrun, cond, dt, rd, rm, operand);
23387                       DRegister rd,
23402                      rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
23413                   rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
23431                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
23444                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
23451   Delegate(kVqshl, &Assembler::vqshl, cond, dt, rd, rm, operand);
23456                       QRegister rd,
23471                      rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
23482                   rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
23500                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
23513                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
23520   Delegate(kVqshl, &Assembler::vqshl, cond, dt, rd, rm, operand);
23525                        DRegister rd,
23542                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
23555                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
23562   Delegate(kVqshlu, &Assembler::vqshlu, cond, dt, rd, rm, operand);
23567                        QRegister rd,
23584                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
23597                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
23604   Delegate(kVqshlu, &Assembler::vqshlu, cond, dt, rd, rm, operand);
23609                        DRegister rd,
23626                        rd.Encode(22, 12) | rm.Encode(5, 0));
23638                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
23650                     rd.Encode(22, 12) | rm.Encode(5, 0));
23660                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
23667   Delegate(kVqshrn, &Assembler::vqshrn, cond, dt, rd, rm, operand);
23672                         DRegister rd,
23689                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
23698                        rd.Encode(22, 12) | rm.Encode(5, 0));
23710                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
23718                     rd.Encode(22, 12) | rm.Encode(5, 0));
23725   Delegate(kVqshrun, &Assembler::vqshrun, cond, dt, rd, rm, operand);
23729     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
23739                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
23750                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
23755   Delegate(kVqsub, &Assembler::vqsub, cond, dt, rd, rn, rm);
23759     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
23769                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
23780                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
23785   Delegate(kVqsub, &Assembler::vqsub, cond, dt, rd, rn, rm);
23789     Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) {
23798                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
23808                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
23813   Delegate(kVraddhn, &Assembler::vraddhn, cond, dt, rd, rn, rm);
23818                        DRegister rd,
23829                    rd.Encode(22, 12) | rm.Encode(5, 0));
23840                 rd.Encode(22, 12) | rm.Encode(5, 0));
23845   Delegate(kVrecpe, &Assembler::vrecpe, cond, dt, rd, rm);
23850                        QRegister rd,
23861                    rd.Encode(22, 12) | rm.Encode(5, 0));
23872                 rd.Encode(22, 12) | rm.Encode(5, 0));
23877   Delegate(kVrecpe, &Assembler::vrecpe, cond, dt, rd, rm);
23881 rd, DRegister rn, DRegister rm) {
23888         EmitT32_32(0xef000f10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
23898         EmitA32(0xf2000f10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
23904   Delegate(kVrecps, &Assembler::vrecps, cond, dt, rd, rn, rm);
23908     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
23915         EmitT32_32(0xef000f50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
23925         EmitA32(0xf2000f50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
23931   Delegate(kVrecps, &Assembler::vrecps, cond, dt, rd, rn, rm);
23936                        DRegister rd,
23946                    rd.Encode(22, 12) | rm.Encode(5, 0));
23956                 rd.Encode(22, 12) | rm.Encode(5, 0));
23961   Delegate(kVrev16, &Assembler::vrev16, cond, dt, rd, rm);
23966                        QRegister rd,
23976                    rd.Encode(22, 12) | rm.Encode(5, 0));
23986                 rd.Encode(22, 12) | rm.Encode(5, 0));
23991   Delegate(kVrev16, &Assembler::vrev16, cond, dt, rd, rm);
23996                        DRegister rd,
24006                    rd.Encode(22, 12) | rm.Encode(5, 0));
24016                 rd.Encode(22, 12) | rm.Encode(5, 0));
24021   Delegate(kVrev32, &Assembler::vrev32, cond, dt, rd, rm);
24026                        QRegister rd,
24036                    rd.Encode(22, 12) | rm.Encode(5, 0));
24046                 rd.Encode(22, 12) | rm.Encode(5, 0));
24051   Delegate(kVrev32, &Assembler::vrev32, cond, dt, rd, rm);
24056                        DRegister rd,
24066                    rd.Encode(22, 12) | rm.Encode(5, 0));
24076                 rd.Encode(22, 12) | rm.Encode(5, 0));
24081   Delegate(kVrev64, &Assembler::vrev64, cond, dt, rd, rm);
24086                        QRegister rd,
24096                    rd.Encode(22, 12) | rm.Encode(5, 0));
24106                 rd.Encode(22, 12) | rm.Encode(5, 0));
24111   Delegate(kVrev64, &Assembler::vrev64, cond, dt, rd, rm);
24115     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
24125                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
24136                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
24141   Delegate(kVrhadd, &Assembler::vrhadd, cond, dt, rd, rn, rm);
24145     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
24155                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
24166                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
24171   Delegate(kVrhadd, &Assembler::vrhadd, cond, dt, rd, rn, rm);
24174 void Assembler::vrinta(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
24180       EmitT32_32(0xffba0500U | rd.Encode(22, 12) | rm.Encode(5, 0));
24186       EmitT32_32(0xfeb80b40U | rd.Encode(22, 12) | rm.Encode(5, 0));
24193       EmitA32(0xf3ba0500U | rd.Encode(22, 12) | rm.Encode(5, 0));
24198       EmitA32(0xfeb80b40U | rd.Encode(22, 12) | rm.Encode(5, 0));
24202   Delegate(kVrinta, &Assembler::vrinta, dt1, dt2, rd, rm);
24205 void Assembler::vrinta(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {
24211       EmitT32_32(0xffba0540U | rd.Encode(22, 12) | rm.Encode(5, 0));
24218       EmitA32(0xf3ba0540U | rd.Encode(22, 12) | rm.Encode(5, 0));
24222   Delegate(kVrinta, &Assembler::vrinta, dt1, dt2, rd, rm);
24225 void Assembler::vrinta(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
24231       EmitT32_32(0xfeb80a40U | rd.Encode(22, 12) | rm.Encode(5, 0));
24238       EmitA32(0xfeb80a40U | rd.Encode(22, 12) | rm.Encode(5, 0));
24242   Delegate(kVrinta, &Assembler::vrinta, dt1, dt2, rd, rm);
24245 void Assembler::vrintm(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
24251       EmitT32_32(0xffba0680U | rd.Encode(22, 12) | rm.Encode(5, 0));
24257       EmitT32_32(0xfebb0b40U | rd.Encode(22, 12) | rm.Encode(5, 0));
24264       EmitA32(0xf3ba0680U | rd.Encode(22, 12) | rm.Encode(5, 0));
24269       EmitA32(0xfebb0b40U | rd.Encode(22, 12) | rm.Encode(5, 0));
24273   Delegate(kVrintm, &Assembler::vrintm, dt1, dt2, rd, rm);
24276 void Assembler::vrintm(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {
24282       EmitT32_32(0xffba06c0U | rd.Encode(22, 12) | rm.Encode(5, 0));
24289       EmitA32(0xf3ba06c0U | rd.Encode(22, 12) | rm.Encode(5, 0));
24293   Delegate(kVrintm, &Assembler::vrintm, dt1, dt2, rd, rm);
24296 void Assembler::vrintm(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
24302       EmitT32_32(0xfebb0a40U | rd.Encode(22, 12) | rm.Encode(5, 0));
24309       EmitA32(0xfebb0a40U | rd.Encode(22, 12) | rm.Encode(5, 0));
24313   Delegate(kVrintm, &Assembler::vrintm, dt1, dt2, rd, rm);
24316 void Assembler::vrintn(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
24322       EmitT32_32(0xffba0400U | rd.Encode(22, 12) | rm.Encode(5, 0));
24328       EmitT32_32(0xfeb90b40U | rd.Encode(22, 12) | rm.Encode(5, 0));
24335       EmitA32(0xf3ba0400U | rd.Encode(22, 12) | rm.Encode(5, 0));
24340       EmitA32(0xfeb90b40U | rd.Encode(22, 12) | rm.Encode(5, 0));
24344   Delegate(kVrintn, &Assembler::vrintn, dt1, dt2, rd, rm);
24347 void Assembler::vrintn(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {
24353       EmitT32_32(0xffba0440U | rd.Encode(22, 12) | rm.Encode(5, 0));
24360       EmitA32(0xf3ba0440U | rd.Encode(22, 12) | rm.Encode(5, 0));
24364   Delegate(kVrintn, &Assembler::vrintn, dt1, dt2, rd, rm);
24367 void Assembler::vrintn(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
24373       EmitT32_32(0xfeb90a40U | rd.Encode(22, 12) | rm.Encode(5, 0));
24380       EmitA32(0xfeb90a40U | rd.Encode(22, 12) | rm.Encode(5, 0));
24384   Delegate(kVrintn, &Assembler::vrintn, dt1, dt2, rd, rm);
24387 void Assembler::vrintp(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
24393       EmitT32_32(0xffba0780U | rd.Encode(22, 12) | rm.Encode(5, 0));
24399       EmitT32_32(0xfeba0b40U | rd.Encode(22, 12) | rm.Encode(5, 0));
24406       EmitA32(0xf3ba0780U | rd.Encode(22, 12) | rm.Encode(5, 0));
24411       EmitA32(0xfeba0b40U | rd.Encode(22, 12) | rm.Encode(5, 0));
24415   Delegate(kVrintp, &Assembler::vrintp, dt1, dt2, rd, rm);
24418 void Assembler::vrintp(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {
24424       EmitT32_32(0xffba07c0U | rd.Encode(22, 12) | rm.Encode(5, 0));
24431       EmitA32(0xf3ba07c0U | rd.Encode(22, 12) | rm.Encode(5, 0));
24435   Delegate(kVrintp, &Assembler::vrintp, dt1, dt2, rd, rm);
24438 void Assembler::vrintp(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
24444       EmitT32_32(0xfeba0a40U | rd.Encode(22, 12) | rm.Encode(5, 0));
24451       EmitA32(0xfeba0a40U | rd.Encode(22, 12) | rm.Encode(5, 0));
24455   Delegate(kVrintp, &Assembler::vrintp, dt1, dt2, rd, rm);
24459     Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
24465       EmitT32_32(0xeeb60a40U | rd.Encode(22, 12) | rm.Encode(5, 0));
24472       EmitA32(0x0eb60a40U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
24477   Delegate(kVrintr, &Assembler::vrintr, cond, dt1, dt2, rd, rm);
24481     Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
24487       EmitT32_32(0xeeb60b40U | rd.Encode(22, 12) | rm.Encode(5, 0));
24494       EmitA32(0x0eb60b40U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
24499   Delegate(kVrintr, &Assembler::vrintr, cond, dt1, dt2, rd, rm);
24503     Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
24509       EmitT32_32(0xffba0480U | rd.Encode(22, 12) | rm.Encode(5, 0));
24515       EmitT32_32(0xeeb70b40U | rd.Encode(22, 12) | rm.Encode(5, 0));
24522       EmitA32(0xf3ba0480U | rd.Encode(22, 12) | rm.Encode(5, 0));
24527       EmitA32(0x0eb70b40U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
24532   Delegate(kVrintx, &Assembler::vrintx, cond, dt1, dt2, rd, rm);
24535 void Assembler::vrintx(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {
24541       EmitT32_32(0xffba04c0U | rd.Encode(22, 12) | rm.Encode(5, 0));
24548       EmitA32(0xf3ba04c0U | rd.Encode(22, 12) | rm.Encode(5, 0));
24552   Delegate(kVrintx, &Assembler::vrintx, dt1, dt2, rd, rm);
24556     Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
24562       EmitT32_32(0xeeb70a40U | rd.Encode(22, 12) | rm.Encode(5, 0));
24569       EmitA32(0x0eb70a40U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
24574   Delegate(kVrintx, &Assembler::vrintx, cond, dt1, dt2, rd, rm);
24578     Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
24584       EmitT32_32(0xffba0580U | rd.Encode(22, 12) | rm.Encode(5, 0));
24590       EmitT32_32(0xeeb60bc0U | rd.Encode(22, 12) | rm.Encode(5, 0));
24597       EmitA32(0xf3ba0580U | rd.Encode(22, 12) | rm.Encode(5, 0));
24602       EmitA32(0x0eb60bc0U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
24607   Delegate(kVrintz, &Assembler::vrintz, cond, dt1, dt2, rd, rm);
24610 void Assembler::vrintz(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {
24616       EmitT32_32(0xffba05c0U | rd.Encode(22, 12) | rm.Encode(5, 0));
24623       EmitA32(0xf3ba05c0U | rd.Encode(22, 12) | rm.Encode(5, 0));
24627   Delegate(kVrintz, &Assembler::vrintz, dt1, dt2, rd, rm);
24631     Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
24637       EmitT32_32(0xeeb60ac0U | rd.Encode(22, 12) | rm.Encode(5, 0));
24644       EmitA32(0x0eb60ac0U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
24649   Delegate(kVrintz, &Assembler::vrintz, cond, dt1, dt2, rd, rm);
24653     Condition cond, DataType dt, DRegister rd, DRegister rm, DRegister rn) {
24663                    rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
24674                 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
24679   Delegate(kVrshl, &Assembler::vrshl, cond, dt, rd, rm, rn);
24683     Condition cond, DataType dt, QRegister rd, QRegister rm, QRegister rn) {
24693                    rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
24704                 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
24709   Delegate(kVrshl, &Assembler::vrshl, cond, dt, rd, rm, rn);
24714                       DRegister rd,
24731                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
24739             EmitT32_32(0xef200110U | rd.Encode(22, 12) | rm.Encode(7, 16) |
24753                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
24760             EmitA32(0xf2200110U | rd.Encode(22, 12) | rm.Encode(7, 16) |
24768   Delegate(kVrshr, &Assembler::vrshr, cond, dt, rd, rm, operand);
24773                       QRegister rd,
24790                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
24798             EmitT32_32(0xef200150U | rd.Encode(22, 12) | rm.Encode(7, 16) |
24812                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
24819             EmitA32(0xf2200150U | rd.Encode(22, 12) | rm.Encode(7, 16) |
24827   Delegate(kVrshr, &Assembler::vrshr, cond, dt, rd, rm, operand);
24832                        DRegister rd,
24849                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
24858                        rd.Encode(22, 12) | rm.Encode(5, 0));
24870                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
24878                     rd.Encode(22, 12) | rm.Encode(5, 0));
24885   Delegate(kVrshrn, &Assembler::vrshrn, cond, dt, rd, rm, operand);
24890                         DRegister rd,
24901                    rd.Encode(22, 12) | rm.Encode(5, 0));
24912                 rd.Encode(22, 12) | rm.Encode(5, 0));
24917   Delegate(kVrsqrte, &Assembler::vrsqrte, cond, dt, rd, rm);
24922                         QRegister rd,
24933                    rd.Encode(22, 12) | rm.Encode(5, 0));
24944                 rd.Encode(22, 12) | rm.Encode(5, 0));
24949   Delegate(kVrsqrte, &Assembler::vrsqrte, cond, dt, rd, rm);
24953     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
24960         EmitT32_32(0xef200f10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
24970         EmitA32(0xf2200f10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
24976   Delegate(kVrsqrts, &Assembler::vrsqrts, cond, dt, rd, rn, rm);
24980     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
24987         EmitT32_32(0xef200f50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
24997         EmitA32(0xf2200f50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
25003   Delegate(kVrsqrts, &Assembler::vrsqrts, cond, dt, rd, rn, rm);
25008                       DRegister rd,
25025                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25038                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25045   Delegate(kVrsra, &Assembler::vrsra, cond, dt, rd, rm, operand);
25050                       QRegister rd,
25067                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25080                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25087   Delegate(kVrsra, &Assembler::vrsra, cond, dt, rd, rm, operand);
25091     Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) {
25100                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
25110                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
25115   Delegate(kVrsubhn, &Assembler::vrsubhn, cond, dt, rd, rn, rm);
25118 void Assembler::vseleq(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
25124       EmitT32_32(0xfe000b00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
25132       EmitA32(0xfe000b00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
25137   Delegate(kVseleq, &Assembler::vseleq, dt, rd, rn, rm);
25140 void Assembler::vseleq(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
25146       EmitT32_32(0xfe000a00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
25154       EmitA32(0xfe000a00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
25159   Delegate(kVseleq, &Assembler::vseleq, dt, rd, rn, rm);
25162 void Assembler::vselge(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
25168       EmitT32_32(0xfe200b00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
25176       EmitA32(0xfe200b00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
25181   Delegate(kVselge, &Assembler::vselge, dt, rd, rn, rm);
25184 void Assembler::vselge(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
25190       EmitT32_32(0xfe200a00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
25198       EmitA32(0xfe200a00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
25203   Delegate(kVselge, &Assembler::vselge, dt, rd, rn, rm);
25206 void Assembler::vselgt(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
25212       EmitT32_32(0xfe300b00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
25220       EmitA32(0xfe300b00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
25225   Delegate(kVselgt, &Assembler::vselgt, dt, rd, rn, rm);
25228 void Assembler::vselgt(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
25234       EmitT32_32(0xfe300a00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
25242       EmitA32(0xfe300a00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
25247   Delegate(kVselgt, &Assembler::vselgt, dt, rd, rn, rm);
25250 void Assembler::vselvs(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
25256       EmitT32_32(0xfe100b00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
25264       EmitA32(0xfe100b00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
25269   Delegate(kVselvs, &Assembler::vselvs, dt, rd, rn, rm);
25272 void Assembler::vselvs(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
25278       EmitT32_32(0xfe100a00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
25286       EmitA32(0xfe100a00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
25291   Delegate(kVselvs, &Assembler::vselvs, dt, rd, rn, rm);
25296                      DRegister rd,
25313                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25326                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25343                      rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
25354                   rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
25360   Delegate(kVshl, &Assembler::vshl, cond, dt, rd, rm, operand);
25365                      QRegister rd,
25382                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25395                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25412                      rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
25423                   rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
25429   Delegate(kVshl, &Assembler::vshl, cond, dt, rd, rm, operand);
25434                       QRegister rd,
25451                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25460                        rd.Encode(22, 12) | rm.Encode(5, 0));
25472                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25480                     rd.Encode(22, 12) | rm.Encode(5, 0));
25487   Delegate(kVshll, &Assembler::vshll, cond, dt, rd, rm, operand);
25492                      DRegister rd,
25509                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25517             EmitT32_32(0xef200110U | rd.Encode(22, 12) | rm.Encode(7, 16) |
25531                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25538             EmitA32(0xf2200110U | rd.Encode(22, 12) | rm.Encode(7, 16) |
25546   Delegate(kVshr, &Assembler::vshr, cond, dt, rd, rm, operand);
25551                      QRegister rd,
25568                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25576             EmitT32_32(0xef200150U | rd.Encode(22, 12) | rm.Encode(7, 16) |
25590                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25597             EmitA32(0xf2200150U | rd.Encode(22, 12) | rm.Encode(7, 16) |
25605   Delegate(kVshr, &Assembler::vshr, cond, dt, rd, rm, operand);
25610                       DRegister rd,
25627                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25636                        rd.Encode(22, 12) | rm.Encode(5, 0));
25648                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25656                     rd.Encode(22, 12) | rm.Encode(5, 0));
25663   Delegate(kVshrn, &Assembler::vshrn, cond, dt, rd, rm, operand);
25668                      DRegister rd,
25685                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25698                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25705   Delegate(kVsli, &Assembler::vsli, cond, dt, rd, rm, operand);
25710                      QRegister rd,
25727                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25740                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25747   Delegate(kVsli, &Assembler::vsli, cond, dt, rd, rm, operand);
25750 void Assembler::vsqrt(Condition cond, DataType dt, SRegister rd, SRegister rm) {
25756       EmitT32_32(0xeeb10ac0U | rd.Encode(22, 12) | rm.Encode(5, 0));
25763       EmitA32(0x0eb10ac0U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
25768   Delegate(kVsqrt, &Assembler::vsqrt, cond, dt, rd, rm);
25771 void Assembler::vsqrt(Condition cond, DataType dt, DRegister rd, DRegister rm) {
25777       EmitT32_32(0xeeb10bc0U | rd.Encode(22, 12) | rm.Encode(5, 0));
25784       EmitA32(0x0eb10bc0U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
25789   Delegate(kVsqrt, &Assembler::vsqrt, cond, dt, rd, rm);
25794                      DRegister rd,
25811 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25824                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25831   Delegate(kVsra, &Assembler::vsra, cond, dt, rd, rm, operand);
25836                      QRegister rd,
25853                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25866                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25873   Delegate(kVsra, &Assembler::vsra, cond, dt, rd, rm, operand);
25878                      DRegister rd,
25895                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25908                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25915   Delegate(kVsri, &Assembler::vsri, cond, dt, rd, rm, operand);
25920                      QRegister rd,
25937                        rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25950                     rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25957   Delegate(kVsri, &Assembler::vsri, cond, dt, rd, rm, operand);
27186                      DRegister rd,
27200         EmitT32_32(0xed000b00U | rd.Encode(22, 12) | (rn.GetCode() << 16) |
27211         EmitA32(0x0d000b00U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
27217   Delegate(kVstr, &Assembler::vstr, cond, dt, rd, operand);
27222                      SRegister rd,
27236         EmitT32_32(0xed000a00U | rd.Encode(22, 12) | (rn.GetCode() << 16) |
27247         EmitA32(0x0d000a00U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
27253   Delegate(kVstr, &Assembler::vstr, cond, dt, rd, operand);
27257     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
27265         EmitT32_32(0xef200d00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
27273       EmitT32_32(0xee300b40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
27282                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
27291         EmitA32(0xf2200d00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
27298       EmitA32(0x0e300b40U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
27306                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
27311   Delegate(kVsub, &Assembler::vsub, cond, dt, rd, rn, rm);
27315     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
27323         EmitT32_32(0xef200d40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
27333                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
27342         EmitA32(0xf2200d40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
27351                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
27356   Delegate(kVsub, &Assembler::vsub, cond, dt, rd, rn, rm);
27360     Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
27366       EmitT32_32(0xee300a40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
27374       EmitA32(0x0e300a40U | (cond.GetCondition() << 28) | rd.Encode(22, 12) |
27379   Delegate(kVsub, &Assembler::vsub, cond, dt, rd, rn, rm);
27383     Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) {
27392                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
27402                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
27407   Delegate(kVsubhn, &Assembler::vsubhn, cond, dt, rd, rn, rm);
27411     Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
27421                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
27432                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
27437   Delegate(kVsubl, &Assembler::vsubl, cond, dt, rd, rn, rm);
27441     Condition cond, DataType dt, QRegister rd, QRegister rn, DRegister rm) {
27451                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
27462                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
27467   Delegate(kVsubw, &Assembler::vsubw, cond, dt, rd, rn, rm);
27470 void Assembler::vswp(Condition cond, DataType dt, DRegister rd, DRegister rm) {
27477       EmitT32_32(0xffb20000U | rd.Encode(22, 12) | rm.Encode(5, 0));
27484       EmitA32(0xf3b20000U | rd.Encode(22, 12) | rm.Encode(5, 0));
27488   Delegate(kVswp, &Assembler::vswp, cond, dt, rd, rm);
27491 void Assembler::vswp(Condition cond, DataType dt, QRegister rd, QRegister rm) {
27498       EmitT32_32(0xffb20040U | rd.Encode(22, 12) | rm.Encode(5, 0));
27505       EmitA32(0xf3b20040U | rd.Encode(22, 12) | rm.Encode(5, 0));
27509   Delegate(kVswp, &Assembler::vswp, cond, dt, rd, rm);
27514                      DRegister rd,
27526         EmitT32_32(0xffb00800U | rd.Encode(22, 12) | first.Encode(7, 16) |
27539         EmitA32(0xf3b00800U | rd.Encode(22, 12) | first.Encode(7, 16) |
27545   Delegate(kVtbl, &Assembler::vtbl, cond, dt, rd, nreglist, rm);
27550                      DRegister rd,
27562         EmitT32_32(0xffb00840U | rd.Encode(22, 12) | first.Encode(7, 16) |
27575         EmitA32(0xf3b00840U | rd.Encode(22, 12) | first.Encode(7, 16) |
27581   Delegate(kVtbx, &Assembler::vtbx, cond, dt, rd, nreglist, rm);
27584 void Assembler::vtrn(Condition cond, DataType dt, DRegister rd, DRegister rm) {
27593                    rd.Encode(22, 12) | rm.Encode(5, 0));
27603                 rd.Encode(22, 12) | rm.Encode(5, 0));
27608   Delegate(kVtrn, &Assembler::vtrn, cond, dt, rd, rm);
27611 void Assembler::vtrn(Condition cond, DataType dt, QRegister rd, QRegister rm) {
27620                    rd.Encode(22, 12) | rm.Encode(5, 0));
27630                 rd.Encode(22, 12) | rm.Encode(5, 0));
27635   Delegate(kVtrn, &Assembler::vtrn, cond, dt, rd, rm);
27639     Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
27648                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
27658                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
27663   Delegate(kVtst, &Assembler::vtst, cond, dt, rd, rn, rm);
27667     Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
27676                    rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
27686                 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
27691   Delegate(kVtst, &Assembler::vtst, cond, dt, rd, rn, rm);
27694 void Assembler::vuzp(Condition cond, DataType dt, DRegister rd, DRegister rm) {
27703                    rd.Encode(22, 12) | rm.Encode(5, 0));
27711         EmitT32_32(0xffba0080U | rd.Encode(22, 12) | rm.Encode(5, 0));
27721                 rd.Encode(22, 12) | rm.Encode(5, 0));
27728         EmitA32(0xf3ba0080U | rd.Encode(22, 12) | rm.Encode(5, 0));
27733   Delegate(kVuzp, &Assembler::vuzp, cond, dt, rd, rm);
27736 void Assembler::vuzp(Condition cond, DataType dt, QRegister rd, QRegister rm) {
27745                    rd.Encode(22, 12) | rm.Encode(5, 0));
27755                 rd.Encode(22, 12) | rm.Encode(5, 0));
27760   Delegate(kVuzp, &Assembler::vuzp, cond, dt, rd, rm);
27763 void Assembler::vzip(Condition cond, DataType dt, DRegister rd, DRegister rm) {
27772                    rd.Encode(22, 12) | rm.Encode(5, 0));
27780         EmitT32_32(0xffba0080U | rd.Encode(22, 12) | rm.Encode(5, 0));
27790                 rd.Encode(22, 12) | rm.Encode(5, 0));
27797         EmitA32(0xf3ba0080U | rd.Encode(22, 12) | rm.Encode(5, 0));
27802   Delegate(kVzip, &Assembler::vzip, cond, dt, rd, rm);
27805 void Assembler::vzip(Condition cond, DataType dt, QRegister rd, QRegister rm) {
27814                    rd.Encode(22, 12) | rm.Encode(5, 0));
27824                 rd.Encode(22, 12) | rm.Encode(5, 0));
27829   Delegate(kVzip, &Assembler::vzip, cond, dt, rd, rm);
OpenGrok
