Lines Matching full:rdlo
3585 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
3586 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo));
3594 smlal(cond, rdlo, rdhi, rn, rm);
3596 void Smlal(Register rdlo, Register rdhi, Register rn, Register rm) {
3597 Smlal(al, rdlo, rdhi, rn, rm);
3601 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
3602 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo));
3610 smlalbb(cond, rdlo, rdhi, rn, rm);
3612 void Smlalbb(Register rdlo, Register rdhi, Register rn, Register rm) {
3613 Smlalbb(al, rdlo, rdhi, rn, rm);
3617 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
3618 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo));
3626 smlalbt(cond, rdlo, rdhi, rn, rm);
3628 void Smlalbt(Register rdlo, Register rdhi, Register rn, Register rm) {
3629 Smlalbt(al, rdlo, rdhi, rn, rm);
3633 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
3634 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo));
3642 smlald(cond, rdlo, rdhi, rn, rm);
3644 void Smlald(Register rdlo, Register rdhi, Register rn, Register rm) {
3645 Smlald(al, rdlo, rdhi, rn, rm);
3649 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
3650 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo));
3658 smlaldx(cond, rdlo, rdhi, rn, rm);
3660 void Smlaldx(Register rdlo, Register rdhi, Register rn, Register rm) {
3661 Smlaldx(al, rdlo, rdhi, rn, rm);
3665 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
3666 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo));
3674 smlals(cond, rdlo, rdhi, rn, rm);
3676 void Smlals(Register rdlo, Register rdhi, Register rn, Register rm) {
3677 Smlals(al, rdlo, rdhi, rn, rm);
3681 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
3682 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo));
3690 smlaltb(cond, rdlo, rdhi, rn, rm);
3692 void Smlaltb(Register rdlo, Register rdhi, Register rn, Register rm) {
3693 Smlaltb(al, rdlo, rdhi, rn, rm);
3697 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
3698 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo));
3706 smlaltt(cond, rdlo, rdhi, rn, rm);
3708 void Smlaltt(Register rdlo, Register rdhi, Register rn, Register rm) {
3709 Smlaltt(al, rdlo, rdhi, rn, rm);
3809 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
3810 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo));
3818 smlsld(cond, rdlo, rdhi, rn, rm);
3820 void Smlsld(Register rdlo, Register rdhi, Register rn, Register rm) {
3821 Smlsld(al, rdlo, rdhi, rn, rm);
3825 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
3826 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo));
3834 smlsldx(cond, rdlo, rdhi, rn, rm);
3836 void Smlsldx(Register rdlo, Register rdhi, Register rn, Register rm) {
3837 Smlsldx(al, rdlo, rdhi, rn, rm);
3977 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
3978 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo));
3986 smull(cond, rdlo, rdhi, rn, rm);
3988 void Smull(Register rdlo, Register rdhi, Register rn, Register rm) {
3989 Smull(al, rdlo, rdhi, rn, rm);
3993 Register rdlo,
3999 Smull(cond, rdlo, rdhi, rn, rm);
4002 Smulls(cond, rdlo, rdhi, rn, rm);
4005 Smull(cond, rdlo, rdhi, rn, rm);
4010 Register rdlo,
4014 Smull(flags, al, rdlo, rdhi, rn, rm);
4018 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
4019 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo));
4027 smulls(cond, rdlo, rdhi, rn, rm);
4029 void Smulls(Register rdlo, Register rdhi, Register rn, Register rm) {
4030 Smulls(al, rdlo, rdhi, rn, rm);
4911 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
4912 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo));
4920 umaal(cond, rdlo, rdhi, rn, rm);
4922 void Umaal(Register rdlo, Register rdhi, Register rn, Register rm) {
4923 Umaal(al, rdlo, rdhi, rn, rm);
4927 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
4928 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo));
4936 umlal(cond, rdlo, rdhi, rn, rm);
4938 void Umlal(Register rdlo, Register rdhi, Register rn, Register rm) {
4939 Umlal(al, rdlo, rdhi, rn, rm);
4943 Register rdlo,
4949 Umlal(cond, rdlo, rdhi, rn, rm);
4952 Umlals(cond, rdlo, rdhi, rn, rm);
4955 Umlal(cond, rdlo, rdhi, rn, rm);
4960 Register rdlo,
4964 Umlal(flags, al, rdlo, rdhi, rn, rm);
4968 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
4969 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo));
4977 umlals(cond, rdlo, rdhi, rn, rm);
4979 void Umlals(Register rdlo, Register rdhi, Register rn, Register rm) {
4980 Umlals(al, rdlo, rdhi, rn, rm);
4984 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
4985 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo));
4993 umull(cond, rdlo, rdhi, rn, rm);
4995 void Umull(Register rdlo, Register rdhi, Register rn, Register rm) {
4996 Umull(al, rdlo, rdhi, rn, rm);
5000 Register rdlo,
5006 Umull(cond, rdlo, rdhi, rn, rm);
5009 Umulls(cond, rdlo, rdhi, rn, rm);
5012 Umull(cond, rdlo, rdhi, rn, rm);
5017 Register rdlo,
5021 Umull(flags, al, rdlo, rdhi, rn, rm);
5025 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
5026 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo));
5034 umulls(cond, rdlo, rdhi, rn, rm);
5036 void Umulls(Register rdlo, Register rdhi, Register rn, Register rm) {
5037 Umulls(al, rdlo, rdhi, rn, rm);
