Cross Reference: /external/vixl/src/aarch32/macro-assembler-aarch32.h

Lines Matching refs:rd
552   void Adr(Condition cond, Register rd, RawLiteral* literal) {
553     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
560       bool can_encode = adr_info(cond, Best, rd, literal, &info);
568     adr(cond, Best, rd, literal);
571   void Adr(Register rd, RawLiteral* literal) { Adr(al, rd, literal); }
704   void Vldr(Condition cond, DataType dt, DRegister rd, RawLiteral* literal) {
705     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
712       bool can_encode = vldr_info(cond, dt, rd, literal, &info);
720     vldr(cond, dt, rd, literal);
723   void Vldr(DataType dt, DRegister rd, RawLiteral* literal) {
724     Vldr(al, dt, rd, literal);
726   void Vldr(Condition cond, DRegister rd, RawLiteral* literal) {
727     Vldr(cond, Untyped64, rd, literal);
729   void Vldr(DRegister rd, RawLiteral* literal) {
730     Vldr(al, Untyped64, rd, literal);
733   void Vldr(Condition cond, DataType dt, SRegister rd, RawLiteral* literal) {
734     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
741       bool can_encode = vldr_info(cond, dt, rd, literal, &info);
749     vldr(cond, dt, rd, literal);
752   void Vldr(DataType dt, SRegister rd, RawLiteral* literal) {
753     Vldr(al, dt, rd, literal);
755   void Vldr(Condition cond, SRegister rd, RawLiteral* literal) {
756     Vldr(cond, Untyped32, rd, literal);
758   void Vldr(SRegister rd, RawLiteral* literal) {
759     Vldr(al, Untyped32, rd, literal);
791   void Vldr(Condition cond, SRegister rd, float v) {
792     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
797     Vldr(cond, rd, literal);
799   void Vldr(SRegister rd, float v) { Vldr(al, rd, v); }
801   void Vldr(Condition cond, DRegister rd, double v) {
802     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
807     Vldr(cond, rd, literal);
809   void Vldr(DRegister rd, double v) { Vldr(al, rd, v); }
879                         Register rd,
888                         Register rd,
892                                 Register rd,
900                         Register rd,
913                         SRegister rd,
920                         DRegister rd,
927                         QRegister rd,
934                         Register rd,
959                         SRegister rd,
966                         DRegister rd,
978                         DRegister rd,
984                         SRegister rd,
989   void Adc(Condition cond, Register rd, Register rn, const Operand& operand) {
990     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
998         operand.IsPlainRegister() && rn.IsLow() && rd.Is(rn) &&
1001     adc(cond, rd, rn, operand);
1003   void Adc(Register rd, Register rn, const Operand& operand) {
1004     Adc(al, rd, rn, operand);
1008            Register rd,
1013         Adc(cond, rd, rn, operand);
1016         Adcs(cond, rd, rn, operand);
1019         bool setflags_is_smaller = IsUsingT32() && cond.Is(al) && rd.IsLow() &&
1020                                    rn.Is(rd) && operand.IsPlainRegister() &&
1023           Adcs(cond, rd, rn, operand);
1025           Adc(cond, rd, rn, operand);
1031            Register rd,
1034     Adc(flags, al, rd, rn, operand);
1037   void Adcs(Condition cond, Register rd, Register rn, const Operand& operand) {
1038     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
1045     adcs(cond, rd, rn, operand);
1047   void Adcs(Register rd, Register rn, const Operand& operand) {
1048     Adcs(al, rd, rn, operand);
1051   void Add(Condition cond, Register rd, Register rn, const Operand& operand) {
1052     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
1058     if (cond.Is(al) && rd.Is(rn) && operand.IsImmediate()) {
1065         // ADD<c>{<q>} <Rd>, <Rn>, #<imm3> ; T1
1067          rd.IsLow()) ||
1070          rd.IsLow() && rn.Is(rd)) ||
1071         // ADD{<c>}{<q>} <Rd>, SP, #<imm8> ; T1
1073          ((operand.GetImmediate() & 0x3) == 0) && rd.IsLow() && rn.IsSP()) ||
1074         // ADD<c>{<q>} <Rd>, <Rn>, <Rm>
1075         (operand.IsPlainRegister() && rd.IsLow() && rn.IsLow() &&
1078         (operand.IsPlainRegister() && !rd.IsPC() && rn.Is(rd) &&
1082         (operand.IsPlainRegister() && !rd.IsPC() && rn.IsSP() &&
1083          operand.GetBaseRegister().Is(rd));
1085     add(cond, rd, rn, operand);
1087   void Add(Register rd, Register rn, const Operand& operand) {
1088     Add(al, rd, rn, operand);
1092            Register rd,
1097         Add(cond, rd, rn, operand);
1100         Adds(cond, rd, rn, operand);
1105             ((operand.IsPlainRegister() && rd.IsLow() && rn.IsLow() &&
1106               !rd.Is(rn) && operand.GetBaseRegister().IsLow()) ||
1108               ((rd.IsLow() && rn.IsLow() && (operand.GetImmediate() < 8)) ||
1109                (rd.IsLow() && rn.Is(rd) && (operand.GetImmediate() < 256)))));
1111           Adds(cond, rd, rn, operand);
1115               ((rd.IsLow() && rn.IsLow() &&
1117                (rd.IsLow() && rn.Is(rd) &&
1120             Subs(cond, rd, rn, -operand.GetSignedImmediate());
1122             Add(cond, rd, rn, operand);
1129            Register rd,
1132     Add(flags, al, rd, rn, operand);
1135   void Adds(Condition cond, Register rd, Register rn, const Operand& operand) {
1136     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
1143     adds(cond, rd, rn, operand);
1145   void Adds(Register rd, Register rn, const Operand& operand) {
1146     Adds(al, rd, rn, operand);
1149   void And(Condition cond, Register rd, Register rn, const Operand& operand) {
1150     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
1156     if (rd.Is(rn) && operand.IsPlainRegister() &&
1157         rd.Is(operand.GetBaseRegister())) {
1163         mov(rd, 0);
1166       if ((immediate == 0xffffffff) && rd.Is(rn)) {
1172         operand.IsPlainRegister() && rd.Is(rn) && rn.IsLow() &&
1175     and_(cond, rd, rn, operand);
1177   void And(Register rd, Register rn, const Operand& operand) {
1178     And(al, rd, rn, operand);
1182            Register rd,
1187         And(cond, rd, rn, operand);
1190         Ands(cond, rd, rn, operand);
1193         if (operand.IsPlainRegister() && rd.Is(rn) &&
1194             rd.Is(operand.GetBaseRegister())) {
1197         bool setflags_is_smaller = IsUsingT32() && cond.Is(al) && rd.IsLow() &&
1198                                    rn.Is(rd) && operand.IsPlainRegister() &&
1201           Ands(cond, rd, rn, operand);
1203           And(cond, rd, rn, operand);
1209            Register rd,
1212     And(flags, al, rd, rn, operand);
1215   void Ands(Condition cond, Register rd, Register rn, const Operand& operand) {
1216     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
1223     ands(cond, rd, rn, operand);
1225   void Ands(Register rd, Register rn, const Operand& operand) {
1226     Ands(al, rd, rn, operand);
1229   void Asr(Condition cond, Register rd, Register rm, const Operand& operand) {
1230     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
1237         // ASR<c>{<q>} {<Rd>,} <Rm>, #<imm> ; T2
1239          (operand.GetImmediate() <= 32) && rd.IsLow() && rm.IsLow()) ||
1241         (operand.IsPlainRegister() && rd.Is(rm) && rd.IsLow() &&
1244     asr(cond, rd, rm, operand);
1246   void Asr(Register rd, Register rm, const Operand& operand) {
1247     Asr(al, rd, rm, operand);
1251            Register rd,
1256         Asr(cond, rd, rm, operand);
1259         Asrs(cond, rd, rm, operand);
1263             IsUsingT32() && cond.Is(al) && rd.IsLow() && rm.IsLow() &&
1266              (operand.IsPlainRegister() && rd.Is(rm)));
1268           Asrs(cond, rd, rm, operand);
1270           Asr(cond, rd, rm, operand);
1276            Register rd,
1279     Asr(flags, al, rd, rm, operand);
1282   void Asrs(Condition cond, Register rd, Register rm, const Operand& operand) {
1283     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
1290     asrs(cond, rd, rm, operand);
1292   void Asrs(Register rd, Register rm, const Operand& operand) {
1293     Asrs(al, rd, rm, operand);
1321   void Bfc(Condition cond, Register rd, uint32_t lsb, uint32_t width) {
1322     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
1327     bfc(cond, rd, lsb, width);
1329   void Bfc(Register rd, uint32_t lsb, uint32_t width) {
1330     Bfc(al, rd, lsb, width);
1334       Condition cond, Register rd, Register rn, uint32_t lsb, uint32_t width) {
1335     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
1341     bfi(cond, rd, rn, lsb, width);
1343   void Bfi(Register rd, Register rn, uint32_t lsb, uint32_t width) {
1344     Bfi(al, rd, rn, lsb, width);
1347   void Bic(Condition cond, Register rd, Register rn, const Operand& operand) {
1348     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
1356       if ((immediate == 0) && rd.Is(rn)) {
1360         mov(rd, 0);
1366         operand.IsPlainRegister() && rd.Is(rn) && rn.IsLow() &&
1369     bic(cond, rd, rn, operand);
1371   void Bic(Register rd, Register rn, const Operand& operand) {
1372     Bic(al, rd, rn, operand);
1376            Register rd,
1381         Bic(cond, rd, rn, operand);
1384         Bics(cond, rd, rn, operand);
1387         bool setflags_is_smaller = IsUsingT32() && cond.Is(al) && rd.IsLow() &&
1388                                    rn.Is(rd) && operand.IsPlainRegister() &&
1391           Bics(cond, rd, rn, operand);
1393           Bic(cond, rd, rn, operand);
1399            Register rd,
1402     Bic(flags, al, rd, rn, operand);
1405   void Bics(Condition cond, Register rd, Register rn, const Operand& operand) {
1406     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
1413     bics(cond, rd, rn, operand);
1415   void Bics(Register rd, Register rn, const Operand& operand) {
1416     Bics(al, rd, rn, operand);
1551   void Clz(Condition cond, Register rd, Register rm) {
1552     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
1558     clz(cond, rd, rm);
1560   void Clz(Register rd, Register rm) { Clz(al, rd, rm); }
1595   void Crc32b(Condition cond, Register rd, Register rn, Register rm) {
1596     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
1603     crc32b(cond, rd, rn, rm);
1605   void Crc32b(Register rd, Register rn, Register rm) { Crc32b(al, rd, rn, rm); }
1607   void Crc32cb(Condition cond, Register rd, Register rn, Register rm) {
1608     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
1615     crc32cb(cond, rd, rn, rm);
1617   void Crc32cb(Register rd, Register rn, Register rm) {
1618     Crc32cb(al, rd, rn, rm);
1621   void Crc32ch(Condition cond, Register rd, Register rn, Register rm) {
1622     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
1629     crc32ch(cond, rd, rn, rm);
1631   void Crc32ch(Register rd, Register rn, Register rm) {
1632     Crc32ch(al, rd, rn, rm);
1635   void Crc32cw(Condition cond, Register rd, Register rn, Register rm) {
1636     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
1643     crc32cw(cond, rd, rn, rm);
1645   void Crc32cw(Register rd, Register rn, Register rm) {
1646     Crc32cw(al, rd, rn, rm);
1649   void Crc32h(Condition cond, Register rd, Register rn, Register rm) {
1650     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
1657     crc32h(cond, rd, rn, rm);
1659   void Crc32h(Register rd, Register rn, Register rm) { Crc32h(al, rd, rn, rm); }
1661   void Crc32w(Condition cond, Register rd, Register rn, Register rm) {
1662     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
1669     crc32w(cond, rd, rn, rm);
1671   void Crc32w(Register rd, Register rn, Register rm) { Crc32w(al, rd, rn, rm); }
1691   void Eor(Condition cond, Register rd, Register rn, const Operand& operand) {
1692     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
1698     if (cond.Is(al) && rd.Is(rn) && operand.IsImmediate()) {
1704         mvn(rd, rn);
1710         operand.IsPlainRegister() && rd.Is(rn) && rn.IsLow() &&
1713     eor(cond, rd, rn, operand);
1715   void Eor(Register rd, Register rn, const Operand& operand) {
1716     Eor(al, rd, rn, operand);
1720            Register rd,
1725         Eor(cond, rd, rn, operand);
1728         Eors(cond, rd, rn, operand);
1731         bool setflags_is_smaller = IsUsingT32() && cond.Is(al) && rd.IsLow() &&
1732                                    rn.Is(rd) && operand.IsPlainRegister() &&
1735           Eors(cond, rd, rn, operand);
1737           Eor(cond, rd, rn, operand);
1743            Register rd,
1746     Eor(flags, al, rd, rn, operand);
1749   void Eors(Condition cond, Register rd, Register rn, const Operand& operand) {
1750     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
1757     eors(cond, rd, rn, operand);
1759   void Eors(Register rd, Register rn, const Operand& operand) {
1760     Eors(al, rd, rn, operand);
2251   void Lsl(Condition cond, Register rd, Register rm, const Operand& operand) {
2252     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
2259         // LSL<c>{<q>} {<Rd>,} <Rm>, #<imm> ; T2
2261          (operand.GetImmediate() <= 31) && rd.IsLow() && rm.IsLow()) ||
2263         (operand.IsPlainRegister() && rd.Is(rm) && rd.IsLow() &&
2266     lsl(cond, rd, rm, operand);
2268   void Lsl(Register rd, Register rm, const Operand& operand) {
2269     Lsl(al, rd, rm, operand);
2273            Register rd,
2278         Lsl(cond, rd, rm, operand);
2281         Lsls(cond, rd, rm, operand);
2285             IsUsingT32() && cond.Is(al) && rd.IsLow() && rm.IsLow() &&
2288              (operand.IsPlainRegister() && rd.Is(rm)));
2290           Lsls(cond, rd, rm, operand);
2292           Lsl(cond, rd, rm, operand);
2298            Register rd,
2301     Lsl(flags, al, rd, rm, operand);
2304   void Lsls(Condition cond, Register rd, Register rm, const Operand& operand) {
2305     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
2312     lsls(cond, rd, rm, operand);
2314   void Lsls(Register rd, Register rm, const Operand& operand) {
2315     Lsls(al, rd, rm, operand);
2318   void Lsr(Condition cond, Register rd, Register rm, const Operand& operand) {
2319     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
2326         // LSR<c>{<q>} {<Rd>,} <Rm>, #<imm> ; T2
2328          (operand.GetImmediate() <= 32) && rd.IsLow() && rm.IsLow()) ||
2330         (operand.IsPlainRegister() && rd.Is(rm) && rd.IsLow() &&
2333     lsr(cond, rd, rm, operand);
2335   void Lsr(Register rd, Register rm, const Operand& operand) {
2336     Lsr(al, rd, rm, operand);
2340            Register rd,
2345         Lsr(cond, rd, rm, operand);
2348         Lsrs(cond, rd, rm, operand);
2352             IsUsingT32() && cond.Is(al) && rd.IsLow() && rm.IsLow() &&
2355              (operand.IsPlainRegister() && rd.Is(rm)));
2357           Lsrs(cond, rd, rm, operand);
2359           Lsr(cond, rd, rm, operand);
2365            Register rd,
2368     Lsr(flags, al, rd, rm, operand);
2371   void Lsrs(Condition cond, Register rd, Register rm, const Operand& operand) {
2372     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
2379     lsrs(cond, rd, rm, operand);
2381   void Lsrs(Register rd, Register rm, const Operand& operand) {
2382     Lsrs(al, rd, rm, operand);
2385   void Mla(Condition cond, Register rd, Register rn, Register rm, Register ra) {
2386     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
2394     mla(cond, rd, rn, rm, ra);
2396   void Mla(Register rd, Register rn, Register rm, Register ra) {
2397     Mla(al, rd, rn, rm, ra);
2401            Register rd,
2407         Mla(cond, rd, rn, rm, ra);
2410         Mlas(cond, rd, rn, rm, ra);
2413         Mla(cond, rd, rn, rm, ra);
2418       FlagsUpdate flags, Register rd, Register rn, Register rm, Register ra) {
2419     Mla(flags, al, rd, rn, rm, ra);
2423       Condition cond, Register rd, Register rn, Register rm, Register ra) {
2424     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
2432     mlas(cond, rd, rn, rm, ra);
2434   void Mlas(Register rd, Register rn, Register rm, Register ra) {
2435     Mlas(al, rd, rn, rm, ra);
2438   void Mls(Condition cond, Register rd, Register rn, Register rm, Register ra) {
2439     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
2447     mls(cond, rd, rn, rm, ra);
2449   void Mls(Register rd, Register rn, Register rm, Register ra) {
2450     Mls(al, rd, rn, rm, ra);
2453   void Mov(Condition cond, Register rd, const Operand& operand) {
2454     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
2459     if (operand.IsPlainRegister() && rd.Is(operand.GetBaseRegister())) {
2463         // MOV<c>{<q>} <Rd>, #<imm8> ; T1
2464         (operand.IsImmediate() && rd.IsLow() &&
2466         // MOV{<c>}{<q>} <Rd>, <Rm> ; T1
2467         (operand.IsPlainRegister() && !rd.IsPC() &&
2469         // MOV<c>{<q>} <Rd>, <Rm> {, <shift> #<amount>} ; T2
2470         (operand.IsImmediateShiftedRegister() && rd.IsLow() &&
2479          rd.Is(operand.GetBaseRegister()) && rd.IsLow() &&
2484     mov(cond, rd, operand);
2486   void Mov(Register rd, const Operand& operand) { Mov(al, rd, operand); }
2489            Register rd,
2493         Mov(cond, rd, operand);
2496         Movs(cond, rd, operand);
2499         if (operand.IsPlainRegister() && rd.Is(operand.GetBaseRegister())) {
2504             ((operand.IsImmediateShiftedRegister() && rd.IsLow() &&
2511              (operand.IsRegisterShiftedRegister() && rd.IsLow() &&
2512               operand.GetBaseRegister().Is(rd) &&
2516              (operand.IsImmediate() && rd.IsLow() &&
2519           Movs(cond, rd, operand);
2521           Mov(cond, rd, operand);
2526   void Mov(FlagsUpdate flags, Register rd, const Operand& operand) {
2527     Mov(flags, al, rd, operand);
2530   void Movs(Condition cond, Register rd, const Operand& operand) {
2531     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
2537     movs(cond, rd, operand);
2539   void Movs(Register rd, const Operand& operand) { Movs(al, rd, operand); }
2541   void Movt(Condition cond, Register rd, const Operand& operand) {
2542     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
2548     movt(cond, rd, operand);
2550   void Movt(Register rd, const Operand& operand) { Movt(al, rd, operand); }
2552   void Mrs(Condition cond, Register rd, SpecialRegister spec_reg) {
2553     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
2558     mrs(cond, rd, spec_reg);
2560   void Mrs(Register rd, SpecialRegister spec_reg) { Mrs(al, rd, spec_reg); }
2576   void Mul(Condition cond, Register rd, Register rn, Register rm) {
2577     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
2585         rd.Is(rm) && rn.IsLow() && rm.IsLow();
2587     mul(cond, rd, rn, rm);
2589   void Mul(Register rd, Register rn, Register rm) { Mul(al, rd, rn, rm); }
2592            Register rd,
2597         Mul(cond, rd, rn, rm);
2600         Muls(cond, rd, rn, rm);
2603         bool setflags_is_smaller = IsUsingT32() && cond.Is(al) && rd.IsLow() &&
2604                                    rn.IsLow() && rm.Is(rd);
2606           Muls(cond, rd, rn, rm);
2608           Mul(cond, rd, rn, rm);
2613   void Mul(FlagsUpdate flags, Register rd, Register rn, Register rm) {
2614     Mul(flags, al, rd, rn, rm);
2617   void Muls(Condition cond, Register rd, Register rn, Register rm) {
2618     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
2625     muls(cond, rd, rn, rm);
2627   void Muls(Register rd, Register rn, Register rm) { Muls(al, rd, rn, rm); }
2629   void Mvn(Condition cond, Register rd, const Operand& operand) {
2630     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
2636         // MVN<c>{<q>} <Rd>, <Rm> ; T1
2637         operand.IsPlainRegister() && rd.IsLow() &&
2640     mvn(cond, rd, operand);
2642   void Mvn(Register rd, const Operand& operand) { Mvn(al, rd, operand); }
2645            Register rd,
2649         Mvn(cond, rd, operand);
2652         Mvns(cond, rd, operand);
2655         bool setflags_is_smaller = IsUsingT32() && cond.Is(al) && rd.IsLow() &&
2659           Mvns(cond, rd, operand);
2661           Mvn(cond, rd, operand);
2666   void Mvn(FlagsUpdate flags, Register rd, const Operand& operand) {
2667     Mvn(flags, al, rd, operand);
2670   void Mvns(Condition cond, Register rd, const Operand& operand) {
2671     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
2677     mvns(cond, rd, operand);
2679   void Mvns(Register rd, const Operand& operand) { Mvns(al, rd, operand); }
2690   void Orn(Condition cond, Register rd, Register rn, const Operand& operand) {
2691     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
2700         mvn(rd, 0);
2703       if ((immediate == 0xffffffff) && rd.Is(rn)) {
2708     orn(cond, rd, rn, operand);
2710   void Orn(Register rd, Register rn, const Operand& operand) {
2711     Orn(al, rd, rn, operand);
2715            Register rd,
2720         Orn(cond, rd, rn, operand);
2723         Orns(cond, rd, rn, operand);
2726         Orn(cond, rd, rn, operand);
2731            Register rd,
2734     Orn(flags, al, rd, rn, operand);
2737   void Orns(Condition cond, Register rd, Register rn, const Operand& operand) {
2738     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
2745     orns(cond, rd, rn, operand);
2747   void Orns(Register rd, Register rn, const Operand& operand) {
2748     Orns(al, rd, rn, operand);
2751   void Orr(Condition cond, Register rd, Register rn, const Operand& operand) {
2752     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
2758     if (rd.Is(rn) && operand.IsPlainRegister() &&
2759         rd.Is(operand.GetBaseRegister())) {
2764       if ((immediate == 0) && rd.Is(rn)) {
2768         mvn(rd, 0);
2774         operand.IsPlainRegister() && rd.Is(rn) && rn.IsLow() &&
2777     orr(cond, rd, rn, operand);
2779   void Orr(Register rd, Register rn, const Operand& operand) {
2780     Orr(al, rd, rn, operand);
2784            Register rd,
2789         Orr(cond, rd, rn, operand);
2792         Orrs(cond, rd, rn, operand);
2795         if (operand.IsPlainRegister() && rd.Is(rn) &&
2796             rd.Is(operand.GetBaseRegister())) {
2799         bool setflags_is_smaller = IsUsingT32() && cond.Is(al) && rd.IsLow() &&
2800                                    rn.Is(rd) && operand.IsPlainRegister() &&
2803           Orrs(cond, rd, rn, operand);
2805           Orr(cond, rd, rn, operand);
2811            Register rd,
2814     Orr(flags, al, rd, rn, operand);
2817   void Orrs(Condition cond, Register rd, Register rn, const Operand& operand) {
2818     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
2825     orrs(cond, rd, rn, operand);
2827   void Orrs(Register rd, Register rn, const Operand& operand) {
2828     Orrs(al, rd, rn, operand);
2831   void Pkhbt(Condition cond, Register rd, Register rn, const Operand& operand) {
2832     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
2839     pkhbt(cond, rd, rn, operand);
2841   void Pkhbt(Register rd, Register rn, const Operand& operand) {
2842     Pkhbt(al, rd, rn, operand);
2845   void Pkhtb(Condition cond, Register rd, Register rn, const Operand& operand) {
2846     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
2853     pkhtb(cond, rd, rn, operand);
2855   void Pkhtb(Register rd, Register rn, const Operand& operand) {
2856     Pkhtb(al, rd, rn, operand);
2931   void Qadd(Condition cond, Register rd, Register rm, Register rn) {
2932     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
2939     qadd(cond, rd, rm, rn);
2941   void Qadd(Register rd, Register rm, Register rn) { Qadd(al, rd, rm, rn); }
2943   void Qadd16(Condition cond, Register rd, Register rn, Register rm) {
2944     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
2951     qadd16(cond, rd, rn, rm);
2953   void Qadd16(Register rd, Register rn, Register rm) { Qadd16(al, rd, rn, rm); }
2955   void Qadd8(Condition cond, Register rd, Register rn, Register rm) {
2956     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
2963     qadd8(cond, rd, rn, rm);
2965   void Qadd8(Register rd, Register rn, Register rm) { Qadd8(al, rd, rn, rm); }
2967   void Qasx(Condition cond, Register rd, Register rn, Register rm) {
2968     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
2975     qasx(cond, rd, rn, rm);
2977   void Qasx(Register rd, Register rn, Register rm) { Qasx(al, rd, rn, rm); }
2979   void Qdadd(Condition cond, Register rd, Register rm, Register rn) {
2980     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
2987     qdadd(cond, rd, rm, rn);
2989   void Qdadd(Register rd, Register rm, Register rn) { Qdadd(al, rd, rm, rn); }
2991   void Qdsub(Condition cond, Register rd, Register rm, Register rn) {
2992     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
2999     qdsub(cond, rd, rm, rn);
3001   void Qdsub(Register rd, Register rm, Register rn) { Qdsub(al, rd, rm, rn); }
3003   void Qsax(Condition cond, Register rd, Register rn, Register rm) {
3004     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3011     qsax(cond, rd, rn, rm);
3013   void Qsax(Register rd, Register rn, Register rm) { Qsax(al, rd, rn, rm); }
3015   void Qsub(Condition cond, Register rd, Register rm, Register rn) {
3016     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3023     qsub(cond, rd, rm, rn);
3025   void Qsub(Register rd, Register rm, Register rn) { Qsub(al, rd, rm, rn); }
3027   void Qsub16(Condition cond, Register rd, Register rn, Register rm) {
3028     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3035     qsub16(cond, rd, rn, rm);
3037   void Qsub16(Register rd, Register rn, Register rm) { Qsub16(al, rd, rn, rm); }
3039   void Qsub8(Condition cond, Register rd, Register rn, Register rm) {
3040     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3047 rd, rn, rm);
3049   void Qsub8(Register rd, Register rn, Register rm) { Qsub8(al, rd, rn, rm); }
3051   void Rbit(Condition cond, Register rd, Register rm) {
3052     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3058     rbit(cond, rd, rm);
3060   void Rbit(Register rd, Register rm) { Rbit(al, rd, rm); }
3062   void Rev(Condition cond, Register rd, Register rm) {
3063     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3069     rev(cond, rd, rm);
3071   void Rev(Register rd, Register rm) { Rev(al, rd, rm); }
3073   void Rev16(Condition cond, Register rd, Register rm) {
3074     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3080     rev16(cond, rd, rm);
3082   void Rev16(Register rd, Register rm) { Rev16(al, rd, rm); }
3084   void Revsh(Condition cond, Register rd, Register rm) {
3085     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3091     revsh(cond, rd, rm);
3093   void Revsh(Register rd, Register rm) { Revsh(al, rd, rm); }
3095   void Ror(Condition cond, Register rd, Register rm, const Operand& operand) {
3096     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3104         operand.IsPlainRegister() && rd.Is(rm) && rd.IsLow() &&
3107     ror(cond, rd, rm, operand);
3109   void Ror(Register rd, Register rm, const Operand& operand) {
3110     Ror(al, rd, rm, operand);
3114            Register rd,
3119         Ror(cond, rd, rm, operand);
3122         Rors(cond, rd, rm, operand);
3125         bool setflags_is_smaller = IsUsingT32() && cond.Is(al) && rd.IsLow() &&
3127                                    rd.Is(rm);
3129           Rors(cond, rd, rm, operand);
3131           Ror(cond, rd, rm, operand);
3137            Register rd,
3140     Ror(flags, al, rd, rm, operand);
3143   void Rors(Condition cond, Register rd, Register rm, const Operand& operand) {
3144     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3151     rors(cond, rd, rm, operand);
3153   void Rors(Register rd, Register rm, const Operand& operand) {
3154     Rors(al, rd, rm, operand);
3157   void Rrx(Condition cond, Register rd, Register rm) {
3158     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3164     rrx(cond, rd, rm);
3166   void Rrx(Register rd, Register rm) { Rrx(al, rd, rm); }
3167   void Rrx(FlagsUpdate flags, Condition cond, Register rd, Register rm) {
3170         Rrx(cond, rd, rm);
3173         Rrxs(cond, rd, rm);
3176         Rrx(cond, rd, rm);
3180   void Rrx(FlagsUpdate flags, Register rd, Register rm) {
3181     Rrx(flags, al, rd, rm);
3184   void Rrxs(Condition cond, Register rd, Register rm) {
3185     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3191     rrxs(cond, rd, rm);
3193   void Rrxs(Register rd, Register rm) { Rrxs(al, rd, rm); }
3195   void Rsb(Condition cond, Register rd, Register rn, const Operand& operand) {
3196     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3203         // RSB<c>{<q>} {<Rd>, }<Rn>, #0 ; T1
3204         operand.IsImmediate() && rd.IsLow() && rn.IsLow() &&
3207     rsb(cond, rd, rn, operand);
3209   void Rsb(Register rd, Register rn, const Operand& operand) {
3210     Rsb(al, rd, rn, operand);
3214            Register rd,
3219         Rsb(cond, rd, rn, operand);
3222         Rsbs(cond, rd, rn, operand);
3225         bool setflags_is_smaller = IsUsingT32() && cond.Is(al) && rd.IsLow() &&
3229           Rsbs(cond, rd, rn, operand);
3231           Rsb(cond, rd, rn, operand);
3237            Register rd,
3240     Rsb(flags, al, rd, rn, operand);
3243   void Rsbs(Condition cond, Register rd, Register rn, const Operand& operand) {
3244     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3251     rsbs(cond, rd, rn, operand);
3253   void Rsbs(Register rd, Register rn, const Operand& operand) {
3254     Rsbs(al, rd, rn, operand);
3257   void Rsc(Condition cond, Register rd, Register rn, const Operand& operand) {
3258     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3265     rsc(cond, rd, rn, operand);
3267   void Rsc(Register rd, Register rn, const Operand& operand) {
3268     Rsc(al, rd, rn, operand);
3272            Register rd,
3277         Rsc(cond, rd, rn, operand);
3280         Rscs(cond, rd, rn, operand);
3283         Rsc(cond, rd, rn, operand);
3288            Register rd,
3291     Rsc(flags, al, rd, rn, operand);
3294   void Rscs(Condition cond, Register rd, Register rn, const Operand& operand) {
3295     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3302     rscs(cond, rd, rn, operand);
3304   void Rscs(Register rd, Register rn, const Operand& operand) {
3305     Rscs(al, rd, rn, operand);
3308   void Sadd16(Condition cond, Register rd, Register rn, Register rm) {
3309     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3316     sadd16(cond, rd, rn, rm);
3318   void Sadd16(Register rd, Register rn, Register rm) { Sadd16(al, rd, rn, rm); }
3320   void Sadd8(Condition cond, Register rd, Register rn, Register rm) {
3321     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3328     sadd8(cond, rd, rn, rm);
3330   void Sadd8(Register rd, Register rn, Register rm) { Sadd8(al, rd, rn, rm); }
3332   void Sasx(Condition cond, Register rd, Register rn, Register rm) {
3333     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3340     sasx(cond, rd, rn, rm);
3342   void Sasx(Register rd, Register rn, Register rm) { Sasx(al, rd, rn, rm); }
3344   void Sbc(Condition cond, Register rd, Register rn, const Operand& operand) {
3345     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3353         operand.IsPlainRegister() && rn.IsLow() && rd.Is(rn) &&
3356     sbc(cond, rd, rn, operand);
3358   void Sbc(Register rd, Register rn, const Operand& operand) {
3359     Sbc(al, rd, rn, operand);
3363            Register rd,
3368         Sbc(cond, rd, rn, operand);
3371         Sbcs(cond, rd, rn, operand);
3374         bool setflags_is_smaller = IsUsingT32() && cond.Is(al) && rd.IsLow() &&
3375                                    rn.Is(rd) && operand.IsPlainRegister() &&
3378           Sbcs(cond, rd, rn, operand);
3380           Sbc(cond, rd, rn, operand);
3386            Register rd,
3389     Sbc(flags, al, rd, rn, operand);
3392   void Sbcs(Condition cond, Register rd, Register rn, const Operand& operand) {
3393     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3400     sbcs(cond, rd, rn, operand);
3402   void Sbcs(Register rd, Register rn, const Operand& operand) {
3403     Sbcs(al, rd, rn, operand);
3407       Condition cond, Register rd, Register rn, uint32_t lsb, uint32_t width) {
3408     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3414     sbfx(cond, rd, rn, lsb, width);
3416   void Sbfx(Register rd, Register rn, uint32_t lsb, uint32_t width) {
3417     Sbfx(al, rd, rn, lsb, width);
3420   void Sdiv(Condition cond, Register rd, Register rn, Register rm) {
3421     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3428     sdiv(cond, rd, rn, rm);
3430   void Sdiv(Register rd, Register rn, Register rm) { Sdiv(al, rd, rn, rm); }
3432   void Sel(Condition cond, Register rd, Register rn, Register rm) {
3433     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3440     sel(cond, rd, rn, rm);
3442   void Sel(Register rd, Register rn, Register rm) { Sel(al, rd, rn, rm); }
3444   void Shadd16(Condition cond, Register rd, Register rn, Register rm) {
3445     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3452     shadd16(cond, rd, rn, rm);
3454   void Shadd16(Register rd, Register rn, Register rm) {
3455     Shadd16(al, rd, rn, rm);
3458   void Shadd8(Condition cond, Register rd, Register rn, Register rm) {
3459     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3466     shadd8(cond, rd, rn, rm);
3468   void Shadd8(Register rd, Register rn, Register rm) { Shadd8(al, rd, rn, rm); }
3470   void Shasx(Condition cond, Register rd, Register rn, Register rm) {
3471     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3478     shasx(cond, rd, rn, rm);
3480   void Shasx(Register rd, Register rn, Register rm) { Shasx(al, rd, rn, rm); }
3482   void Shsax(Condition cond, Register rd, Register rn, Register rm) {
3483     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3490     shsax(cond, rd, rn, rm);
3492   void Shsax(Register rd, Register rn, Register rm) { Shsax(al, rd, rn, rm); }
3494   void Shsub16(Condition cond, Register rd, Register rn, Register rm) {
3495     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3502     shsub16(cond, rd, rn, rm);
3504   void Shsub16(Register rd, Register rn, Register rm) {
3505     Shsub16(al, rd, rn, rm);
3508   void Shsub8(Condition cond, Register rd, Register rn, Register rm) {
3509     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3516     shsub8(cond, rd, rn, rm);
3518   void Shsub8(Register rd, Register rn, Register rm) { Shsub8(al, rd, rn, rm); }
3521       Condition cond, Register rd, Register rn, Register rm, Register ra) {
3522     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3530     smlabb(cond, rd, rn, rm, ra);
3532   void Smlabb(Register rd, Register rn, Register rm, Register ra) {
3533     Smlabb(al, rd, rn, rm, ra);
3537       Condition cond, Register rd, Register rn, Register rm, Register ra) {
3538     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3546     smlabt(cond, rd, rn, rm, ra);
3548   void Smlabt(Register rd, Register rn, Register rm, Register ra) {
3549     Smlabt(al, rd, rn, rm, ra);
3553       Condition cond, Register rd, Register rn, Register rm, Register ra) {
3554     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3562     smlad(cond, rd, rn, rm, ra);
3564   void Smlad(Register rd, Register rn, Register rm, Register ra) {
3565     Smlad(al, rd, rn, rm, ra);
3569       Condition cond, Register rd, Register rn, Register rm, Register ra) {
3570     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3578     smladx(cond, rd, rn, rm, ra);
3580   void Smladx(Register rd, Register rn, Register rm, Register ra) {
3581     Smladx(al, rd, rn, rm, ra);
3713       Condition cond, Register rd, Register rn, Register rm, Register ra) {
3714     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3722     smlatb(cond, rd, rn, rm, ra);
3724   void Smlatb(Register rd, Register rn, Register rm, Register ra) {
3725     Smlatb(al, rd, rn, rm, ra);
3729       Condition cond, Register rd, Register rn, Register rm, Register ra) {
3730     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3738     smlatt(cond, rd, rn, rm, ra);
3740   void Smlatt(Register rd, Register rn, Register rm, Register ra) {
3741     Smlatt(al, rd, rn, rm, ra);
3745       Condition cond, Register rd, Register rn, Register rm, Register ra) {
3746     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3754     smlawb(cond, rd, rn, rm, ra);
3756   void Smlawb(Register rd, Register rn, Register rm, Register ra) {
3757     Smlawb(al, rd, rn, rm, ra);
3761       Condition cond, Register rd, Register rn, Register rm, Register ra) {
3762     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3770     smlawt(cond, rd, rn, rm, ra);
3772   void Smlawt(Register rd, Register rn, Register rm, Register ra) {
3773     Smlawt(al, rd, rn, rm, ra);
3777       Condition cond, Register rd, Register rn, Register rm, Register ra) {
3778     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3786     smlsd(cond, rd, rn, rm, ra);
3788   void Smlsd(Register rd, Register rn, Register rm, Register ra) {
3789     Smlsd(al, rd, rn, rm, ra);
3793       Condition cond, Register rd, Register rn, Register rm, Register ra) {
3794     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3802     smlsdx(cond, rd, rn, rm, ra);
3804   void Smlsdx(Register rd, Register rn, Register rm, Register ra) {
3805     Smlsdx(al, rd, rn, rm, ra);
3841       Condition cond, Register rd, Register rn, Register rm, Register ra) {
3842     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3850     smmla(cond, rd, rn, rm, ra);
3852   void Smmla(Register rd, Register rn, Register rm, Register ra) {
3853     Smmla(al, rd, rn, rm, ra);
3857       Condition cond, Register rd, Register rn, Register rm, Register ra) {
3858     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3866     smmlar(cond, rd, rn, rm, ra);
3868   void Smmlar(Register rd, Register rn, Register rm, Register ra) {
3869     Smmlar(al, rd, rn, rm, ra);
3873       Condition cond, Register rd, Register rn, Register rm, Register ra) {
3874     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3882     smmls(cond, rd, rn, rm, ra);
3884   void Smmls(Register rd, Register rn, Register rm, Register ra) {
3885     Smmls(al, rd, rn, rm, ra);
3889       Condition cond, Register rd, Register rn, Register rm, Register ra) {
3890     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3898     smmlsr(cond, rd, rn, rm, ra);
3900   void Smmlsr(Register rd, Register rn, Register rm, Register ra) {
3901     Smmlsr(al, rd, rn, rm, ra);
3904   void Smmul(Condition cond, Register rd, Register rn, Register rm) {
3905     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3912     smmul(cond, rd, rn, rm);
3914   void Smmul(Register rd, Register rn, Register rm) { Smmul(al, rd, rn, rm); }
3916 rd, Register rn, Register rm) {
3917     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3924     smmulr(cond, rd, rn, rm);
3926   void Smmulr(Register rd, Register rn, Register rm) { Smmulr(al, rd, rn, rm); }
3928   void Smuad(Condition cond, Register rd, Register rn, Register rm) {
3929     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3936     smuad(cond, rd, rn, rm);
3938   void Smuad(Register rd, Register rn, Register rm) { Smuad(al, rd, rn, rm); }
3940   void Smuadx(Condition cond, Register rd, Register rn, Register rm) {
3941     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3948     smuadx(cond, rd, rn, rm);
3950   void Smuadx(Register rd, Register rn, Register rm) { Smuadx(al, rd, rn, rm); }
3952   void Smulbb(Condition cond, Register rd, Register rn, Register rm) {
3953     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3960     smulbb(cond, rd, rn, rm);
3962   void Smulbb(Register rd, Register rn, Register rm) { Smulbb(al, rd, rn, rm); }
3964   void Smulbt(Condition cond, Register rd, Register rn, Register rm) {
3965     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3972     smulbt(cond, rd, rn, rm);
3974   void Smulbt(Register rd, Register rn, Register rm) { Smulbt(al, rd, rn, rm); }
4033   void Smultb(Condition cond, Register rd, Register rn, Register rm) {
4034     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4041     smultb(cond, rd, rn, rm);
4043   void Smultb(Register rd, Register rn, Register rm) { Smultb(al, rd, rn, rm); }
4045   void Smultt(Condition cond, Register rd, Register rn, Register rm) {
4046     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4053     smultt(cond, rd, rn, rm);
4055   void Smultt(Register rd, Register rn, Register rm) { Smultt(al, rd, rn, rm); }
4057   void Smulwb(Condition cond, Register rd, Register rn, Register rm) {
4058     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4065     smulwb(cond, rd, rn, rm);
4067   void Smulwb(Register rd, Register rn, Register rm) { Smulwb(al, rd, rn, rm); }
4069   void Smulwt(Condition cond, Register rd, Register rn, Register rm) {
4070     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4077     smulwt(cond, rd, rn, rm);
4079   void Smulwt(Register rd, Register rn, Register rm) { Smulwt(al, rd, rn, rm); }
4081   void Smusd(Condition cond, Register rd, Register rn, Register rm) {
4082     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4089     smusd(cond, rd, rn, rm);
4091   void Smusd(Register rd, Register rn, Register rm) { Smusd(al, rd, rn, rm); }
4093   void Smusdx(Condition cond, Register rd, Register rn, Register rm) {
4094     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4101     smusdx(cond, rd, rn, rm);
4103   void Smusdx(Register rd, Register rn, Register rm) { Smusdx(al, rd, rn, rm); }
4105   void Ssat(Condition cond, Register rd, uint32_t imm, const Operand& operand) {
4106     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4112     ssat(cond, rd, imm, operand);
4114   void Ssat(Register rd, uint32_t imm, const Operand& operand) {
4115     Ssat(al, rd, imm, operand);
4118   void Ssat16(Condition cond, Register rd, uint32_t imm, Register rn) {
4119     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4125     ssat16(cond, rd, imm, rn);
4127   void Ssat16(Register rd, uint32_t imm, Register rn) {
4128     Ssat16(al, rd, imm, rn);
4131   void Ssax(Condition cond, Register rd, Register rn, Register rm) {
4132     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4139     ssax(cond, rd, rn, rm);
4141   void Ssax(Register rd, Register rn, Register rm) { Ssax(al, rd, rn, rm); }
4143   void Ssub16(Condition cond, Register rd, Register rn, Register rm) {
4144     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4151     ssub16(cond, rd, rn, rm);
4153   void Ssub16(Register rd, Register rn, Register rm) { Ssub16(al, rd, rn, rm); }
4155   void Ssub8(Condition cond, Register rd, Register rn, Register rm) {
4156     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4163     ssub8(cond, rd, rn, rm);
4165   void Ssub8(Register rd, Register rn, Register rm) { Ssub8(al, rd, rn, rm); }
4190              Register rd,
4193     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4200     stlex(cond, rd, rt, operand);
4202   void Stlex(Register rd, Register rt, const MemOperand& operand) {
4203     Stlex(al, rd, rt, operand);
4207               Register rd,
4210     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4217     stlexb(cond, rd, rt, operand);
4219   void Stlexb(Register rd, Register rt, const MemOperand& operand) {
4220     Stlexb(al, rd, rt, operand);
4224               Register rd,
4228     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4236     stlexd(cond, rd, rt, rt2, operand);
4238   void Stlexd(Register rd,
4242     Stlexd(al, rd, rt, rt2, operand);
4246               Register rd,
4249     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4256     stlexh(cond, rd, rt, operand);
4258   void Stlexh(Register rd, Register rt, const MemOperand& operand) {
4259     Stlexh(al, rd, rt, operand);
4468              Register rd,
4471     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4478     strex(cond, rd, rt, operand);
4480   void Strex(Register rd, Register rt, const MemOperand& operand) {
4481     Strex(al, rd, rt, operand);
4485               Register rd,
4488     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4495     strexb(cond, rd, rt, operand);
4497   void Strexb(Register rd, Register rt, const MemOperand& operand) {
4498     Strexb(al, rd, rt, operand);
4502               Register rd,
4506     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4514     strexd(cond, rd, rt, rt2, operand);
4516   void Strexd(Register rd,
4520     Strexd(al, rd, rt, rt2, operand);
4524               Register rd,
4527     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4534     strexh(cond, rd, rt, operand);
4536   void Strexh(Register rd, Register rt, const MemOperand& operand) {
4537     Strexh(al, rd, rt, operand);
4562   void Sub(Condition cond, Register rd, Register rn, const Operand& operand) {
4563     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4569     if (cond.Is(al) && rd.Is(rn) && operand.IsImmediate()) {
4576         // SUB<c>{<q>} <Rd>, <Rn>, #<imm3> ; T1
4578          rd.IsLow()) ||
4581          rd.IsLow() && rn.Is(rd)) ||
4582         // SUB<c>{<q>} <Rd>, <Rn>, <Rm>
4583         (operand.IsPlainRegister() && rd.IsLow() && rn.IsLow() &&
4586     sub(cond, rd, rn, operand);
4588   void Sub(Register rd, Register rn, const Operand& operand) {
4589     Sub(al, rd, rn, operand);
4593            Register rd,
4598         Sub(cond, rd, rn, operand);
4601         Subs(cond, rd, rn, operand);
4606             ((operand.IsPlainRegister() && rd.IsLow() && rn.IsLow() &&
4609               ((rd.IsLow() && rn.IsLow() && (operand.GetImmediate() < 8)) ||
4610                (rd.IsLow() && rn.Is(rd) && (operand.GetImmediate() < 256)))));
4612           Subs(cond, rd, rn, operand);
4616               ((rd.IsLow() && rn.IsLow() &&
4618                (rd.IsLow() && rn.Is(rd) &&
4621             Adds(cond, rd, rn, -operand.GetSignedImmediate());
4623             Sub(cond, rd, rn, operand);
4630            Register rd,
4633     Sub(flags, al, rd, rn, operand);
4636   void Subs(Condition cond, Register rd, Register rn, const Operand& operand) {
4637     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4644     subs(cond, rd, rn, operand);
4646   void Subs(Register rd, Register rn, const Operand& operand) {
4647     Subs(al, rd, rn, operand);
4659   void Sxtab(Condition cond, Register rd, Register rn, const Operand& operand) {
4660     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4667     sxtab(cond, rd, rn, operand);
4669   void Sxtab(Register rd, Register rn, const Operand& operand) {
4670     Sxtab(al, rd, rn, operand);
4674                Register rd,
4677     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4684     sxtab16(cond, rd, rn, operand);
4686   void Sxtab16(Register rd, Register rn, const Operand& operand) {
4687     Sxtab16(al, rd, rn, operand);
4690   void Sxtah(Condition cond, Register rd, Register rn, const Operand& operand) {
4691     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4698     sxtah(cond, rd, rn, operand);
4700   void Sxtah(Register rd, Register rn, const Operand& operand) {
4701     Sxtah(al, rd, rn, operand);
4704   void Sxtb(Condition cond, Register rd, const Operand& operand) {
4705     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4711     sxtb(cond, rd, operand);
4713   void Sxtb(Register rd, const Operand& operand) { Sxtb(al, rd, operand); }
4715   void Sxtb16(Condition cond, Register rd, const Operand& operand) {
4716     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4722     sxtb16(cond, rd, operand);
4724   void Sxtb16(Register rd, const Operand& operand) { Sxtb16(al, rd, operand); }
4726   void Sxth(Condition cond, Register rd, const Operand& operand) {
4727     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4733     sxth(cond, rd, operand);
4735   void Sxth(Register rd, const Operand& operand) { Sxth(al, rd, operand); }
4763   void Uadd16(Condition cond, Register rd
4764     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4771     uadd16(cond, rd, rn, rm);
4773   void Uadd16(Register rd, Register rn, Register rm) { Uadd16(al, rd, rn, rm); }
4775   void Uadd8(Condition cond, Register rd, Register rn, Register rm) {
4776     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4783     uadd8(cond, rd, rn, rm);
4785   void Uadd8(Register rd, Register rn, Register rm) { Uadd8(al, rd, rn, rm); }
4787   void Uasx(Condition cond, Register rd, Register rn, Register rm) {
4788     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4795     uasx(cond, rd, rn, rm);
4797   void Uasx(Register rd, Register rn, Register rm) { Uasx(al, rd, rn, rm); }
4800       Condition cond, Register rd, Register rn, uint32_t lsb, uint32_t width) {
4801     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4807     ubfx(cond, rd, rn, lsb, width);
4809   void Ubfx(Register rd, Register rn, uint32_t lsb, uint32_t width) {
4810     Ubfx(al, rd, rn, lsb, width);
4822   void Udiv(Condition cond, Register rd, Register rn, Register rm) {
4823     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4830     udiv(cond, rd, rn, rm);
4832   void Udiv(Register rd, Register rn, Register rm) { Udiv(al, rd, rn, rm); }
4834   void Uhadd16(Condition cond, Register rd, Register rn, Register rm) {
4835     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4842     uhadd16(cond, rd, rn, rm);
4844   void Uhadd16(Register rd, Register rn, Register rm) {
4845     Uhadd16(al, rd, rn, rm);
4848   void Uhadd8(Condition cond, Register rd, Register rn, Register rm) {
4849     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4856     uhadd8(cond, rd, rn, rm);
4858   void Uhadd8(Register rd, Register rn, Register rm) { Uhadd8(al, rd, rn, rm); }
4860   void Uhasx(Condition cond, Register rd, Register rn, Register rm) {
4861     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4868     uhasx(cond, rd, rn, rm);
4870   void Uhasx(Register rd, Register rn, Register rm) { Uhasx(al, rd, rn, rm); }
4872   void Uhsax(Condition cond, Register rd, Register rn, Register rm) {
4873     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4880     uhsax(cond, rd, rn, rm);
4882   void Uhsax(Register rd, Register rn, Register rm) { Uhsax(al, rd, rn, rm); }
4884   void Uhsub16(Condition cond, Register rd, Register rn, Register rm) {
4885     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4892     uhsub16(cond, rd, rn, rm);
4894   void Uhsub16(Register rd, Register rn, Register rm) {
4895     Uhsub16(al, rd, rn, rm);
4898   void Uhsub8(Condition cond, Register rd, Register rn, Register rm) {
4899     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4906     uhsub8(cond, rd, rn, rm);
4908   void Uhsub8(Register rd, Register rn, Register rm) { Uhsub8(al, rd, rn, rm); }
5040   void Uqadd16(Condition cond, Register rd, Register rn, Register rm) {
5041     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5048     uqadd16(cond, rd, rn, rm);
5050   void Uqadd16(Register rd, Register rn, Register rm) {
5051     Uqadd16(al, rd, rn, rm);
5054   void Uqadd8(Condition cond, Register rd, Register rn, Register rm) {
5055     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5062     uqadd8(cond, rd, rn, rm);
5064   void Uqadd8(Register rd, Register rn, Register rm) { Uqadd8(al, rd, rn, rm); }
5066   void Uqasx(Condition cond, Register rd, Register rn, Register rm) {
5067     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5074     uqasx(cond, rd, rn, rm);
5076   void Uqasx(Register rd, Register rn, Register rm) { Uqasx(al, rd, rn, rm); }
5078   void Uqsax(Condition cond, Register rd, Register rn, Register rm) {
5079     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5086     uqsax(cond, rd, rn, rm);
5088   void Uqsax(Register rd, Register rn, Register rm) { Uqsax(al, rd, rn, rm); }
5090   void Uqsub16(Condition cond, Register rd, Register rn, Register rm) {
5091     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5098     uqsub16(cond, rd, rn, rm);
5100   void Uqsub16(Register rd, Register rn, Register rm) {
5101     Uqsub16(al, rd, rn, rm);
5104   void Uqsub8(Condition cond, Register rd, Register rn, Register rm) {
5105     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5112     uqsub8(cond, rd, rn, rm);
5114   void Uqsub8(Register rd, Register rn, Register rm) { Uqsub8(al, rd, rn, rm); }
5116   void Usad8(Condition cond, Register rd, Register rn, Register rm) {
5117     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5124     usad8(cond, rd, rn, rm);
5126   void Usad8(Register rd, Register rn, Register rm) { Usad8(al, rd, rn, rm); }
5129       Condition cond, Register rd, Register rn, Register rm, Register ra) {
5130     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5138     usada8(cond, rd, rn, rm, ra);
5140   void Usada8(Register rd, Register rn, Register rm, Register ra) {
5141     Usada8(al, rd, rn, rm, ra);
5144   void Usat(Condition cond, Register rd, uint32_t imm, const Operand& operand) {
5145     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5151     usat(cond, rd, imm, operand);
5153   void Usat(Register rd, uint32_t imm, const Operand& operand) {
5154     Usat(al, rd, imm, operand);
5157   void Usat16(Condition cond, Register rd, uint32_t imm, Register rn) {
5158     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5164     usat16(cond, rd, imm, rn);
5166   void Usat16(Register rd, uint32_t imm, Register rn) {
5167     Usat16(al, rd, imm, rn);
5170   void Usax(Condition cond, Register rd, Register rn, Register rm) {
5171     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5178     usax(cond, rd, rn, rm);
5180   void Usax(Register rd, Register rn, Register rm) { Usax(al, rd, rn, rm); }
5182   void Usub16(Condition cond, Register rd, Register rn, Register rm) {
5183     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5190 rd, rn, rm);
5192   void Usub16(Register rd, Register rn, Register rm) { Usub16(al, rd, rn, rm); }
5194   void Usub8(Condition cond, Register rd, Register rn, Register rm) {
5195     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5202     usub8(cond, rd, rn, rm);
5204   void Usub8(Register rd, Register rn, Register rm) { Usub8(al, rd, rn, rm); }
5206   void Uxtab(Condition cond, Register rd, Register rn, const Operand& operand) {
5207     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5214     uxtab(cond, rd, rn, operand);
5216   void Uxtab(Register rd, Register rn, const Operand& operand) {
5217     Uxtab(al, rd, rn, operand);
5221                Register rd,
5224     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5231     uxtab16(cond, rd, rn, operand);
5233   void Uxtab16(Register rd, Register rn, const Operand& operand) {
5234     Uxtab16(al, rd, rn, operand);
5237   void Uxtah(Condition cond, Register rd, Register rn, const Operand& operand) {
5238     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5245     uxtah(cond, rd, rn, operand);
5247   void Uxtah(Register rd, Register rn, const Operand& operand) {
5248     Uxtah(al, rd, rn, operand);
5251   void Uxtb(Condition cond, Register rd, const Operand& operand) {
5252     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5258     uxtb(cond, rd, operand);
5260   void Uxtb(Register rd, const Operand& operand) { Uxtb(al, rd, operand); }
5262   void Uxtb16(Condition cond, Register rd, const Operand& operand) {
5263     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5269     uxtb16(cond, rd, operand);
5271   void Uxtb16(Register rd, const Operand& operand) { Uxtb16(al, rd, operand); }
5273   void Uxth(Condition cond, Register rd, const Operand& operand) {
5274     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5280     uxth(cond, rd, operand);
5282   void Uxth(Register rd, const Operand& operand) { Uxth(al, rd, operand); }
5285       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5286     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5293     vaba(cond, dt, rd, rn, rm);
5295   void Vaba(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5296     Vaba(al, dt, rd, rn, rm);
5300       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5301     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5308     vaba(cond, dt, rd, rn, rm);
5310   void Vaba(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5311     Vaba(al, dt, rd, rn, rm);
5315       Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
5316     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5323     vabal(cond, dt, rd, rn, rm);
5325   void Vabal(DataType dt, QRegister rd, DRegister rn, DRegister rm) {
5326     Vabal(al, dt, rd, rn, rm);
5330       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5331     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5338     vabd(cond, dt, rd, rn, rm);
5340   void Vabd(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5341     Vabd(al, dt, rd, rn, rm);
5345       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5346     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5353     vabd(cond, dt, rd, rn, rm);
5355   void Vabd(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5356     Vabd(al, dt, rd, rn, rm);
5360       Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
5361     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5368     vabdl(cond, dt, rd, rn, rm);
5370   void Vabdl(DataType dt, QRegister rd, DRegister rn, DRegister rm) {
5371     Vabdl(al, dt, rd, rn, rm);
5374   void Vabs(Condition cond, DataType dt, DRegister rd, DRegister rm) {
5375     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5381     vabs(cond, dt, rd, rm);
5383   void Vabs(DataType dt, DRegister rd, DRegister rm) { Vabs(al, dt, rd, rm); }
5385   void Vabs(Condition cond, DataType dt, QRegister rd, QRegister rm) {
5386     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5392     vabs(cond, dt, rd, rm);
5394   void Vabs(DataType dt, QRegister rd, QRegister rm) { Vabs(al, dt, rd, rm); }
5396   void Vabs(Condition cond, DataType dt, SRegister rd, SRegister rm) {
5397     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5403     vabs(cond, dt, rd, rm);
5405   void Vabs(DataType dt, SRegister rd, SRegister rm) { Vabs(al, dt, rd, rm); }
5408       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5409     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5416     vacge(cond, dt, rd, rn, rm);
5418   void Vacge(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5419     Vacge(al, dt, rd, rn, rm);
5423       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5424     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5431     vacge(cond, dt, rd, rn, rm);
5433   void Vacge(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5434     Vacge(al, dt, rd, rn, rm);
5438       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5439     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5446     vacgt(cond, dt, rd, rn, rm);
5448   void Vacgt(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5449     Vacgt(al, dt, rd, rn, rm);
5453       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5454     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5461     vacgt(cond, dt, rd, rn, rm);
5463   void Vacgt(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5464     Vacgt(al, dt, rd, rn, rm);
5468       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5469     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5476     vacle(cond, dt, rd, rn, rm);
5478   void Vacle(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5479     Vacle(al, dt, rd, rn, rm);
5483       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5484     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5491     vacle(cond, dt, rd, rn, rm);
5493   void Vacle(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5494     Vacle(al, dt, rd, rn, rm);
5498       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5499     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5506     vaclt(cond, dt, rd, rn, rm);
5508   void Vaclt(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5509     Vaclt(al, dt, rd, rn, rm);
5513       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5514     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5521     vaclt(cond, dt, rd, rn, rm);
5523   void Vaclt(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5524     Vaclt(al, dt, rd, rn, rm);
5528       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5529     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5536     vadd(cond, dt, rd, rn, rm);
5538   void Vadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5539     Vadd(al, dt, rd, rn, rm);
5543       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5544     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5551     vadd(cond, dt, rd, rn, rm);
5553   void Vadd(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5554     Vadd(al, dt, rd, rn, rm);
5558       Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
5559     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5566     vadd(cond, dt, rd, rn, rm);
5568   void Vadd(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
5569     Vadd(al, dt, rd, rn, rm);
5573       Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) {
5574     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5581     vaddhn(cond, dt, rd, rn, rm);
5583   void Vaddhn(DataType dt, DRegister rd, QRegister rn, QRegister rm) {
5584     Vaddhn(al, dt, rd, rn, rm);
5588       Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
5589     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5596     vaddl(cond, dt, rd, rn, rm);
5598   void Vaddl(DataType dt, QRegister rd, DRegister rn, DRegister rm) {
5599     Vaddl(al, dt, rd, rn, rm);
5603       Condition cond, DataType dt, QRegister rd, QRegister rn, DRegister rm) {
5604     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5611     vaddw(cond, dt, rd, rn, rm);
5613   void Vaddw(DataType dt, QRegister rd, QRegister rn, DRegister rm) {
5614     Vaddw(al, dt, rd, rn, rm);
5619             DRegister rd,
5622     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5629     vand(cond, dt, rd, rn, operand);
5631   void Vand(DataType dt, DRegister rd, DRegister rn, const DOperand& operand) {
5632     Vand(al, dt, rd, rn, operand);
5637             QRegister rd,
5640     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5647     vand(cond, dt, rd, rn, operand);
5649   void Vand(DataType dt, QRegister rd, QRegister rn, const QOperand& operand) {
5650     Vand(al, dt, rd, rn, operand);
5655             DRegister rd,
5658     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5665     vbic(cond, dt, rd, rn, operand);
5667   void Vbic(DataType dt, DRegister rd, DRegister rn, const DOperand& operand) {
5668     Vbic(al, dt, rd, rn, operand);
5673             QRegister rd,
5676     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5683     vbic(cond, dt, rd, rn, operand);
5685   void Vbic(DataType dt, QRegister rd, QRegister rn, const QOperand& operand) {
5686     Vbic(al, dt, rd, rn, operand);
5690       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5691     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5698     vbif(cond, dt, rd, rn, rm);
5700   void Vbif(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5701     Vbif(al, dt, rd, rn, rm);
5703   void Vbif(Condition cond, DRegister rd, DRegister rn, DRegister rm) {
5704     Vbif(cond, kDataTypeValueNone, rd, rn, rm);
5706   void Vbif(DRegister rd, DRegister rn, DRegister rm) {
5707     Vbif(al, kDataTypeValueNone, rd, rn, rm);
5711       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5712     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5719     vbif(cond, dt, rd, rn, rm);
5721   void Vbif(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5722     Vbif(al, dt, rd, rn, rm);
5724   void Vbif(Condition cond, QRegister rd, QRegister rn, QRegister rm) {
5725     Vbif(cond, kDataTypeValueNone, rd, rn, rm);
5727   void Vbif(QRegister rd, QRegister rn, QRegister rm) {
5728     Vbif(al, kDataTypeValueNone, rd, rn, rm);
5732       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5733     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5740     vbit(cond, dt, rd, rn, rm);
5742   void Vbit(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5743     Vbit(al, dt, rd, rn, rm);
5745   void Vbit(Condition cond, DRegister rd, DRegister rn, DRegister rm) {
5746     Vbit(cond, kDataTypeValueNone, rd, rn, rm);
5748   void Vbit(DRegister rd, DRegister rn, DRegister rm) {
5749     Vbit(al, kDataTypeValueNone, rd, rn, rm);
5753       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5754     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5761     vbit(cond, dt, rd, rn, rm);
5763   void Vbit(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5764     Vbit(al, dt, rd, rn, rm);
5766   void Vbit(Condition cond, QRegister rd, QRegister rn, QRegister rm) {
5767     Vbit(cond, kDataTypeValueNone, rd, rn, rm);
5769   void Vbit(QRegister rd, QRegister rn, QRegister rm) {
5770     Vbit(al, kDataTypeValueNone, rd, rn, rm);
5774       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5775     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5782     vbsl(cond, dt, rd, rn, rm);
5784   void Vbsl(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5785     Vbsl(al, dt, rd, rn, rm);
5787   void Vbsl(Condition cond, DRegister rd, DRegister rn, DRegister rm) {
5788     Vbsl(cond, kDataTypeValueNone, rd, rn, rm);
5790   void Vbsl(DRegister rd, DRegister rn, DRegister rm) {
5791     Vbsl(al, kDataTypeValueNone, rd, rn, rm);
5795       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5796     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5803     vbsl(cond, dt, rd, rn, rm);
5805   void Vbsl(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5806     Vbsl(al, dt, rd, rn, rm);
5808   void Vbsl(Condition cond, QRegister rd, QRegister rn, QRegister rm) {
5809     Vbsl(cond, kDataTypeValueNone, rd, rn, rm);
5811   void Vbsl(QRegister rd, QRegister rn, QRegister rm) {
5812     Vbsl(al, kDataTypeValueNone, rd, rn, rm);
5817             DRegister rd,
5820     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5827     vceq(cond, dt, rd, rm, operand);
5829   void Vceq(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
5830     Vceq(al, dt, rd, rm, operand);
5835             QRegister rd,
5838     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5845     vceq(cond, dt, rd, rm, operand);
5847   void Vceq(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
5848     Vceq(al, dt, rd, rm, operand);
5852       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5853     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5860     vceq(cond, dt, rd, rn, rm);
5862   void Vceq(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5863     Vceq(al, dt, rd, rn, rm);
5867       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5868     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5875     vceq(cond, dt, rd, rn, rm);
5877   void Vceq(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5878     Vceq(al, dt, rd, rn, rm);
5883             DRegister rd,
5886     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5893     vcge(cond, dt, rd, rm, operand);
5895   void Vcge(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
5896     Vcge(al, dt, rd, rm, operand);
5901             QRegister rd,
5904     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5911     vcge(cond, dt, rd, rm, operand);
5913   void Vcge(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
5914     Vcge(al, dt, rd, rm, operand);
5918       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5919     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5926     vcge(cond, dt, rd, rn, rm);
5928   void Vcge(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5929     Vcge(al, dt, rd, rn, rm);
5933       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5934     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5941     vcge(cond, dt, rd, rn, rm);
5943   void Vcge(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
5944     Vcge(al, dt, rd, rn, rm);
5949             DRegister rd,
5952     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5959     vcgt(cond, dt, rd, rm, operand);
5961   void Vcgt(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
5962     Vcgt(al, dt, rd, rm, operand);
5967             QRegister rd,
5970     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5977     vcgt(cond, dt, rd, rm, operand);
5979   void Vcgt(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
5980     Vcgt(al, dt, rd, rm, operand);
5984       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5985     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5992     vcgt(cond, dt, rd, rn, rm);
5994   void Vcgt(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
5995     Vcgt(al, dt, rd, rn, rm);
5999       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
6000     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6007     vcgt(cond, dt, rd, rn, rm);
6009   void Vcgt(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
6010     Vcgt(al, dt, rd, rn, rm);
6015             DRegister rd,
6018     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6025     vcle(cond, dt, rd, rm, operand);
6027   void Vcle(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
6028     Vcle(al, dt, rd, rm, operand);
6033             QRegister rd,
6036     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6043     vcle(cond, dt, rd, rm, operand);
6045   void Vcle(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
6046     Vcle(al, dt, rd, rm, operand);
6050       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6051     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6058     vcle(cond, dt, rd, rn, rm);
6060   void Vcle(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6061     Vcle(al, dt, rd, rn, rm);
6065       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
6066     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6073     vcle(cond, dt, rd, rn, rm);
6075   void Vcle(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
6076     Vcle(al, dt, rd, rn, rm);
6079   void Vcls(Condition cond, DataType dt, DRegister rd, DRegister rm) {
6080     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6086     vcls(cond, dt, rd, rm);
6088   void Vcls(DataType dt, DRegister rd, DRegister rm) { Vcls(al, dt, rd, rm); }
6090   void Vcls(Condition cond, DataType dt, QRegister rd, QRegister rm) {
6091     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6097     vcls(cond, dt, rd, rm);
6099   void Vcls(DataType dt, QRegister rd, QRegister rm) { Vcls(al, dt, rd, rm); }
6103             DRegister rd,
6106     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6113     vclt(cond, dt, rd, rm, operand);
6115   void Vclt(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
6116     Vclt(al, dt, rd, rm, operand);
6121             QRegister rd,
6124     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6131     vclt(cond, dt, rd, rm, operand);
6133   void Vclt(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
6134     Vclt(al, dt, rd, rm, operand);
6138       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6139     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6146     vclt(cond, dt, rd, rn, rm);
6148   void Vclt(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6149     Vclt(al, dt, rd, rn, rm);
6153       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
6154     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6161     vclt(cond, dt, rd, rn, rm);
6163   void Vclt(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
6164     Vclt(al, dt, rd, rn, rm);
6167   void Vclz(Condition cond, DataType dt, DRegister rd, DRegister rm) {
6168     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6174     vclz(cond, dt, rd, rm);
6176   void Vclz(DataType dt, DRegister rd, DRegister rm) { Vclz(al, dt, rd, rm); }
6178   void Vclz(Condition cond, DataType dt, QRegister rd, QRegister rm) {
6179     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6185     vclz(cond, dt, rd, rm);
6187   void Vclz(DataType dt, QRegister rd, QRegister rm) { Vclz(al, dt, rd, rm); }
6191             SRegister rd,
6193     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6199     vcmp(cond, dt, rd, operand);
6201   void Vcmp(DataType dt, SRegister rd, const SOperand& operand) {
6202     Vcmp(al, dt, rd, operand);
6207             DRegister rd,
6209     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6215     vcmp(cond, dt, rd, operand);
6217   void Vcmp(DataType dt, DRegister rd, const DOperand& operand) {
6218     Vcmp(al, dt, rd, operand);
6223              SRegister rd,
6225     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6231     vcmpe(cond, dt, rd, operand);
6233   void Vcmpe(DataType dt, SRegister rd, const SOperand& operand) {
6234     Vcmpe(al, dt, rd, operand);
6239              DRegister rd,
6241     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6247     vcmpe(cond, dt, rd, operand);
6249   void Vcmpe(DataType dt, DRegister rd, const DOperand& operand) {
6250     Vcmpe(al, dt, rd, operand);
6253   void Vcnt(Condition cond, DataType dt, DRegister rd, DRegister rm) {
6254     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6260     vcnt(cond, dt, rd, rm);
6262   void Vcnt(DataType dt, DRegister rd, DRegister rm) { Vcnt(al, dt, rd, rm); }
6264   void Vcnt(Condition cond, DataType dt, QRegister rd, QRegister rm) {
6265     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6271     vcnt(cond, dt, rd, rm);
6273   void Vcnt(DataType dt, QRegister rd, QRegister rm) { Vcnt(al, dt, rd, rm); }
6276       Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm) {
6277     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6283     vcvt(cond, dt1, dt2, rd, rm);
6285   void Vcvt(DataType dt1, DataType dt2, DRegister rd, SRegister rm) {
6286     Vcvt(al, dt1, dt2, rd, rm);
6290       Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
6291     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6297     vcvt(cond, dt1, dt2, rd, rm);
6299   void Vcvt(DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
6300     Vcvt(al, dt1, dt2, rd, rm);
6306             DRegister rd,
6309     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6315     vcvt(cond, dt1, dt2, rd, rm, fbits);
6318       DataType dt1, DataType dt2, DRegister rd, DRegister rm, int32_t fbits) {
6319     Vcvt(al, dt1, dt2, rd, rm, fbits);
6325             QRegister rd,
6328     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6334     vcvt(cond, dt1, dt2, rd, rm, fbits);
6337       DataType dt1, DataType dt2, QRegister rd, QRegister rm, int32_t fbits) {
6338     Vcvt(al, dt1, dt2, rd, rm, fbits);
6344             SRegister rd,
6347     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6353     vcvt(cond, dt1, dt2, rd, rm, fbits);
6356       DataType dt1, DataType dt2, SRegister rd, SRegister rm, int32_t fbits) {
6357     Vcvt(al, dt1, dt2, rd, rm, fbits);
6361       Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
6362     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6368     vcvt(cond, dt1, dt2, rd, rm);
6370   void Vcvt(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
6371     Vcvt(al, dt1, dt2, rd, rm);
6375       Condition cond, DataType dt1, DataType dt2, QRegister rd, QRegister rm) {
6376     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6382     vcvt(cond, dt1, dt2, rd, rm);
6384   void Vcvt(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {
6385     Vcvt(al, dt1, dt2, rd, rm);
6389       Condition cond, DataType dt1, DataType dt2, DRegister rd, QRegister rm) {
6390     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6396     vcvt(cond, dt1, dt2, rd, rm);
6398   void Vcvt(DataType dt1, DataType dt2, DRegister rd, QRegister rm) {
6399     Vcvt(al, dt1, dt2, rd, rm);
6403       Condition cond, DataType dt1, DataType dt2, QRegister rd, DRegister rm) {
6404     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6410     vcvt(cond, dt1, dt2, rd, rm);
6412   void Vcvt(DataType dt1, DataType dt2, QRegister rd, DRegister rm) {
6413     Vcvt(al, dt1, dt2, rd, rm);
6417       Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
6418     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6424     vcvt(cond, dt1, dt2, rd, rm);
6426   void Vcvt(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
6427     Vcvt(al, dt1, dt2, rd, rm);
6430   void Vcvta(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
6431     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6436     vcvta(dt1, dt2, rd, rm);
6439   void Vcvta(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {
6440     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6445     vcvta(dt1, dt2, rd, rm);
6448   void Vcvta(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
6449     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6454     vcvta(dt1, dt2, rd, rm);
6457   void Vcvta(DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
6458     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6463     vcvta(dt1, dt2, rd, rm);
6467       Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
6468     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6474     vcvtb(cond, dt1, dt2, rd, rm);
6476   void Vcvtb(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
6477     Vcvtb(al, dt1, dt2, rd, rm);
6481       Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm) {
6482     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6488     vcvtb(cond, dt1, dt2, rd, rm);
6490   void Vcvtb(DataType dt1, DataType dt2, DRegister rd, SRegister rm) {
6491     Vcvtb(al, dt1, dt2, rd, rm);
6495       Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
6496     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6502     vcvtb(cond, dt1, dt2, rd, rm);
6504   void Vcvtb(DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
6505     Vcvtb(al, dt1, dt2, rd, rm);
6508   void Vcvtm(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
6509     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6514     vcvtm(dt1, dt2, rd, rm);
6517   void Vcvtm(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {
6518 rd));
6523     vcvtm(dt1, dt2, rd, rm);
6526   void Vcvtm(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
6527     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6532     vcvtm(dt1, dt2, rd, rm);
6535   void Vcvtm(DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
6536     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6541     vcvtm(dt1, dt2, rd, rm);
6544   void Vcvtn(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
6545     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6550     vcvtn(dt1, dt2, rd, rm);
6553   void Vcvtn(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {
6554     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6559     vcvtn(dt1, dt2, rd, rm);
6562   void Vcvtn(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
6563     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6568     vcvtn(dt1, dt2, rd, rm);
6571   void Vcvtn(DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
6572     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6577     vcvtn(dt1, dt2, rd, rm);
6580   void Vcvtp(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
6581     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6586     vcvtp(dt1, dt2, rd, rm);
6589   void Vcvtp(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {
6590     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6595     vcvtp(dt1, dt2, rd, rm);
6598   void Vcvtp(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
6599     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6604     vcvtp(dt1, dt2, rd, rm);
6607   void Vcvtp(DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
6608     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6613     vcvtp(dt1, dt2, rd, rm);
6617       Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
6618     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6624     vcvtr(cond, dt1, dt2, rd, rm);
6626   void Vcvtr(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
6627     Vcvtr(al, dt1, dt2, rd, rm);
6631       Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
6632     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6638     vcvtr(cond, dt1, dt2, rd, rm);
6640   void Vcvtr(DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
6641     Vcvtr(al, dt1, dt2, rd, rm);
6645       Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
6646     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6652     vcvtt(cond, dt1, dt2, rd, rm);
6654   void Vcvtt(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
6655     Vcvtt(al, dt1, dt2, rd, rm);
6659       Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm) {
6660     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6666     vcvtt(cond, dt1, dt2, rd, rm);
6668   void Vcvtt(DataType dt1, DataType dt2, DRegister rd, SRegister rm) {
6669     Vcvtt(al, dt1, dt2, rd, rm);
6673       Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
6674     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6680     vcvtt(cond, dt1, dt2, rd, rm);
6682   void Vcvtt(DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
6683     Vcvtt(al, dt1, dt2, rd, rm);
6687       Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
6688     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6695     vdiv(cond, dt, rd, rn, rm);
6697   void Vdiv(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
6698     Vdiv(al, dt, rd, rn, rm);
6702       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6703     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6710     vdiv(cond, dt, rd, rn, rm);
6712   void Vdiv(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6713     Vdiv(al, dt, rd, rn, rm);
6716   void Vdup(Condition cond, DataType dt, QRegister rd, Register rt) {
6717     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6723     vdup(cond, dt, rd, rt);
6725   void Vdup(DataType dt, QRegister rd, Register rt) { Vdup(al, dt, rd, rt); }
6727   void Vdup(Condition cond, DataType dt, DRegister rd, Register rt) {
6728     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6734     vdup(cond, dt, rd, rt);
6736   void Vdup(DataType dt, DRegister rd, Register rt) { Vdup(al, dt, rd, rt); }
6738   void Vdup(Condition cond, DataType dt, DRegister rd, DRegisterLane rm) {
6739     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6745     vdup(cond, dt, rd, rm);
6747   void Vdup(DataType dt, DRegister rd, DRegisterLane rm) {
6748     Vdup(al, dt, rd, rm);
6751   void Vdup(Condition cond, DataType dt, QRegister rd, DRegisterLane rm) {
6752     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6758     vdup(cond, dt, rd, rm);
6760   void Vdup(DataType dt, QRegister rd, DRegisterLane rm) {
6761     Vdup(al, dt, rd, rm);
6765       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6766     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6773     veor(cond, dt, rd, rn, rm);
6775   void Veor(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6776     Veor(al, dt, rd, rn, rm);
6778   void Veor(Condition cond, DRegister rd, DRegister rn, DRegister rm) {
6779     Veor(cond, kDataTypeValueNone, rd, rn, rm);
6781   void Veor(DRegister rd, DRegister rn, DRegister rm) {
6782     Veor(al, kDataTypeValueNone, rd, rn, rm);
6786       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
6787     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6794     veor(cond, dt, rd, rn, rm);
6796   void Veor(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
6797     Veor(al, dt, rd, rn, rm);
6799   void Veor(Condition cond, QRegister rd, QRegister rn, QRegister rm) {
6800     Veor(cond, kDataTypeValueNone, rd, rn, rm);
6802   void Veor(QRegister rd, QRegister rn, QRegister rm) {
6803     Veor(al, kDataTypeValueNone, rd, rn, rm);
6808             DRegister rd,
6812     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6820     vext(cond, dt, rd, rn, rm, operand);
6823             DRegister rd,
6827     Vext(al, dt, rd, rn, rm, operand);
6832             QRegister rd,
6836     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6844     vext(cond, dt, rd, rn, rm, operand);
6847             QRegister rd,
6851     Vext(al, dt, rd, rn, rm, operand);
6855       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6856     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6863     vfma(cond, dt, rd, rn, rm);
6865   void Vfma(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6866     Vfma(al, dt, rd, rn, rm);
6870       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
6871     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6878     vfma(cond, dt, rd, rn, rm);
6880   void Vfma(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
6881     Vfma(al, dt, rd, rn, rm);
6885       Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
6886     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6893     vfma(cond, dt, rd, rn, rm);
6895   void Vfma(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
6896     Vfma(al, dt, rd, rn, rm);
6900       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6901     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6908     vfms(cond, dt, rd, rn, rm);
6910   void Vfms(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6911     Vfms(al, dt, rd, rn, rm);
6915       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
6916     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6923     vfms(cond, dt, rd, rn, rm);
6925   void Vfms(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
6926     Vfms(al, dt, rd, rn, rm);
6930       Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
6931     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6938     vfms(cond, dt, rd, rn, rm);
6940   void Vfms(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
6941     Vfms(al, dt, rd, rn, rm);
6945       Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
6946     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6953     vfnma(cond, dt, rd, rn, rm);
6955   void Vfnma(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
6956     Vfnma(al, dt, rd, rn, rm);
6960       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6961     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6968     vfnma(cond, dt, rd, rn, rm);
6970   void Vfnma(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6971     Vfnma(al, dt, rd, rn, rm);
6975       Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
6976     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6983     vfnms(cond, dt, rd, rn, rm);
6985   void Vfnms(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
6986     Vfnms(al, dt, rd, rn, rm);
6990       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6991     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6998     vfnms(cond, dt, rd, rn, rm);
7000   void Vfnms(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
7001     Vfnms(al, dt, rd, rn, rm);
7005       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
7006     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7013     vhadd(cond, dt, rd, rn, rm);
7015   void Vhadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
7016     Vhadd(al, dt, rd, rn, rm);
7020       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
7021     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7028     vhadd(cond, dt, rd, rn, rm);
7030   void Vhadd(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
7031     Vhadd(al, dt, rd, rn, rm);
7035       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
7036     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7043     vhsub(cond, dt, rd, rn, rm);
7045   void Vhsub(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
7046     Vhsub(al, dt, rd, rn, rm);
7050       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
7051     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7058     vhsub(cond, dt, rd, rn, rm);
7060   void Vhsub(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
7061     Vhsub(al, dt, rd, rn, rm);
7331             DRegister rd,
7333     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7339     vldr(cond, dt, rd, operand);
7341   void Vldr(DataType dt, DRegister rd, const MemOperand& operand) {
7342     Vldr(al, dt, rd, operand);
7344   void Vldr(Condition cond, DRegister rd, const MemOperand& operand) {
7345     Vldr(cond, Untyped64, rd, operand);
7347   void Vldr(DRegister rd, const MemOperand& operand) {
7348     Vldr(al, Untyped64, rd, operand);
7354             SRegister rd,
7356     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7362     vldr(cond, dt, rd, operand);
7364   void Vldr(DataType dt, SRegister rd, const MemOperand& operand) {
7365     Vldr(al, dt, rd, operand);
7367   void Vldr(Condition cond, SRegister rd, const MemOperand& operand) {
7368     Vldr(cond, Untyped32, rd, operand);
7370   void Vldr(SRegister rd, const MemOperand& operand) {
7371     Vldr(al, Untyped32, rd, operand);
7375       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
7376     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7383     vmax(cond, dt, rd, rn, rm);
7385   void Vmax(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
7386     Vmax(al, dt, rd, rn, rm);
7390       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
7391     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7398     vmax(cond, dt, rd, rn, rm);
7400   void Vmax(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
7401     Vmax(al, dt, rd, rn, rm);
7404   void Vmaxnm(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
7405     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7411     vmaxnm(dt, rd, rn, rm);
7414   void Vmaxnm(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
7415     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7421     vmaxnm(dt, rd, rn, rm);
7424   void Vmaxnm(DataType dt, SRegister rd
7425     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7431     vmaxnm(dt, rd, rn, rm);
7435       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
7436     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7443     vmin(cond, dt, rd, rn, rm);
7445   void Vmin(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
7446     Vmin(al, dt, rd, rn, rm);
7450       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
7451     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7458     vmin(cond, dt, rd, rn, rm);
7460   void Vmin(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
7461     Vmin(al, dt, rd, rn, rm);
7464   void Vminnm(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
7465     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7471     vminnm(dt, rd, rn, rm);
7474   void Vminnm(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
7475     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7481     vminnm(dt, rd, rn, rm);
7484   void Vminnm(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
7485     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7491     vminnm(dt, rd, rn, rm);
7496             DRegister rd,
7499     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7506     vmla(cond, dt, rd, rn, rm);
7508   void Vmla(DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) {
7509     Vmla(al, dt, rd, rn, rm);
7514             QRegister rd,
7517     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7524     vmla(cond, dt, rd, rn, rm);
7526   void Vmla(DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) {
7527     Vmla(al, dt, rd, rn, rm);
7531       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
7532     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7539     vmla(cond, dt, rd, rn, rm);
7541   void Vmla(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
7542     Vmla(al, dt, rd, rn, rm);
7546       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
7547     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7554     vmla(cond, dt, rd, rn, rm);
7556   void Vmla(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
7557     Vmla(al, dt, rd, rn, rm);
7561       Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
7562     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7569     vmla(cond, dt, rd, rn, rm);
7571   void Vmla(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
7572     Vmla(al, dt, rd, rn, rm);
7577              QRegister rd,
7580     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7587     vmlal(cond, dt, rd, rn, rm);
7589   void Vmlal(DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) {
7590     Vmlal(al, dt, rd, rn, rm);
7594       Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
7595     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7602     vmlal(cond, dt, rd, rn, rm);
7604   void Vmlal(DataType dt, QRegister rd, DRegister rn, DRegister rm) {
7605     Vmlal(al, dt, rd, rn, rm);
7610             DRegister rd,
7613     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7620     vmls(cond, dt, rd, rn, rm);
7622   void Vmls(DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) {
7623     Vmls(al, dt, rd, rn, rm);
7628             QRegister rd,
7631     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7638     vmls(cond, dt, rd, rn, rm);
7640   void Vmls(DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) {
7641     Vmls(al, dt, rd, rn, rm);
7645       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
7646     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7653     vmls(cond, dt, rd, rn, rm);
7655   void Vmls(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
7656     Vmls(al, dt, rd, rn, rm);
7660       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
7661     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7668     vmls(cond, dt, rd, rn, rm);
7670   void Vmls(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
7671     Vmls(al, dt, rd, rn, rm);
7675       Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
7676     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7683     vmls(cond, dt, rd, rn, rm);
7685   void Vmls(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
7686     Vmls(al, dt, rd, rn, rm);
7691              QRegister rd,
7694     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7701     vmlsl(cond, dt, rd, rn, rm);
7703   void Vmlsl(DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) {
7704     Vmlsl(al, dt, rd, rn, rm);
7708       Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
7709     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7716     vmlsl(cond, dt, rd, rn, rm);
7718   void Vmlsl(DataType dt, QRegister rd, DRegister rn, DRegister rm) {
7719     Vmlsl(al, dt, rd, rn, rm);
7800   void Vmov(Condition cond, DataType dt, DRegisterLane rd, Register rt) {
7801     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7807     vmov(cond, dt, rd, rt);
7809   void Vmov(DataType dt, DRegisterLane rd, Register rt) {
7810     Vmov(al, dt, rd, rt);
7812   void Vmov(Condition cond, DRegisterLane rd, Register rt) {
7813     Vmov(cond, kDataTypeValueNone, rd, rt);
7815   void Vmov(DRegisterLane rd, Register rt) {
7816     Vmov(al, kDataTypeValueNone, rd, rt);
7821             DRegister rd,
7823     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7829     vmov(cond, dt, rd, operand);
7831   void Vmov(DataType dt, DRegister rd, const DOperand& operand) {
7832     Vmov(al, dt, rd, operand);
7837             QRegister rd,
7839     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7845     vmov(cond, dt, rd, operand);
7847   void Vmov(DataType dt, QRegister rd, const QOperand& operand) {
7848     Vmov(al, dt, rd, operand);
7853             SRegister rd,
7855     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7861     vmov(cond, dt, rd, operand);
7863   void Vmov(DataType dt, SRegister rd, const SOperand& operand) {
7864     Vmov(al, dt, rd, operand);
7886   void Vmovl(Condition cond, DataType dt, QRegister rd, DRegister rm) {
7887     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7893     vmovl(cond, dt, rd, rm);
7895   void Vmovl(DataType dt, QRegister rd, DRegister rm) { Vmovl(al, dt, rd, rm); }
7897   void Vmovn(Condition cond, DataType dt, DRegister rd, QRegister rm) {
7898     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7904     vmovn(cond, dt, rd, rm);
7906   void Vmovn(DataType dt, DRegister rd, QRegister rm) { Vmovn(al, dt, rd, rm); }
7934             DRegister rd,
7938     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7945     vmul(cond, dt, rd, rn, dm, index);
7948       DataType dt, DRegister rd, DRegister rn, DRegister dm, unsigned index) {
7949     Vmul(al, dt, rd, rn, dm, index);
7954             QRegister rd,
7958     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7965     vmul(cond, dt, rd, rn, dm, index);
7968       DataType dt, QRegister rd, QRegister rn, DRegister dm, unsigned index) {
7969     Vmul(al, dt, rd, rn, dm, index);
7973       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
7974     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7981     vmul(cond, dt, rd, rn, rm);
7983   void Vmul(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
7984     Vmul(al, dt, rd, rn, rm);
7988       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
7989     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7996     vmul(cond, dt, rd, rn, rm);
7998   void Vmul(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
7999     Vmul(al, dt, rd, rn, rm);
8003       Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
8004     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8011     vmul(cond, dt, rd, rn, rm);
8013   void Vmul(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
8014     Vmul(al, dt, rd, rn, rm);
8019              QRegister rd,
8023     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8030     vmull(cond, dt, rd, rn, dm, index);
8033       DataType dt, QRegister rd, DRegister rn, DRegister dm, unsigned index) {
8034     Vmull(al, dt, rd, rn, dm, index);
8038       Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
8039     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8046     vmull(cond, dt, rd, rn, rm);
8048   void Vmull(DataType dt, QRegister rd, DRegister rn, DRegister rm) {
8049     Vmull(al, dt, rd, rn, rm);
8054             DRegister rd,
8056     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8062     vmvn(cond, dt, rd, operand);
8064   void Vmvn(DataType dt, DRegister rd, const DOperand& operand) {
8065     Vmvn(al, dt, rd, operand);
8070             QRegister rd,
8072     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8078     vmvn(cond, dt, rd, operand);
8080   void Vmvn(DataType dt, QRegister rd, const QOperand& operand) {
8081     Vmvn(al, dt, rd, operand);
8084   void Vneg(Condition cond, DataType dt, DRegister rd, DRegister rm) {
8085     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8091     vneg(cond, dt, rd, rm);
8093   void Vneg(DataType dt, DRegister rd, DRegister rm) { Vneg(al, dt, rd, rm); }
8095   void Vneg(Condition cond, DataType dt, QRegister rd, QRegister rm) {
8096     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8102     vneg(cond, dt, rd, rm);
8104   void Vneg(DataType dt, QRegister rd, QRegister rm) { Vneg(al, dt, rd, rm); }
8106   void Vneg(Condition cond, DataType dt, SRegister rd, SRegister rm) {
8107     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8113     vneg(cond, dt, rd, rm);
8115   void Vneg(DataType dt, SRegister rd, SRegister rm) { Vneg(al, dt, rd, rm); }
8118       Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
8119     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8126     vnmla(cond, dt, rd, rn, rm);
8128   void Vnmla(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
8129     Vnmla(al, dt, rd, rn, rm);
8133       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
8134     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8141     vnmla(cond, dt, rd, rn, rm);
8143   void Vnmla(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
8144     Vnmla(al, dt, rd, rn, rm);
8148       Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
8149     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8156     vnmls(cond, dt, rd, rn, rm);
8158   void Vnmls(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
8159     Vnmls(al, dt, rd, rn, rm);
8163       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
8164     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8171     vnmls(cond, dt, rd, rn, rm);
8173   void Vnmls(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
8174     Vnmls(al, dt, rd, rn, rm);
8178       Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
8179     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8186     vnmul(cond, dt, rd, rn, rm);
8188   void Vnmul(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
8189     Vnmul(al, dt, rd, rn, rm);
8193       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
8194     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8201     vnmul(cond, dt, rd, rn, rm);
8203   void Vnmul(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
8204     Vnmul(al, dt, rd, rn, rm);
8209             DRegister rd,
8212     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8219     vorn(cond, dt, rd, rn, operand);
8221   void Vorn(DataType dt, DRegister rd, DRegister rn, const DOperand& operand) {
8222     Vorn(al, dt, rd, rn, operand);
8227             QRegister rd,
8230     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8237     vorn(cond, dt, rd, rn, operand);
8239   void Vorn(DataType dt, QRegister rd, QRegister rn, const QOperand& operand) {
8240     Vorn(al, dt, rd, rn, operand);
8245             DRegister rd,
8248     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8255     vorr(cond, dt, rd, rn, operand);
8257   void Vorr(DataType dt, DRegister rd, DRegister rn, const DOperand& operand) {
8258     Vorr(al, dt, rd, rn, operand);
8261             DRegister rd,
8264     Vorr(cond, kDataTypeValueNone, rd, rn, operand);
8266   void Vorr(DRegister rd, DRegister rn, const DOperand& operand) {
8267     Vorr(al, kDataTypeValueNone, rd, rn, operand);
8272             QRegister rd,
8275     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8282     vorr(cond, dt, rd, rn, operand);
8284   void Vorr(DataType dt, QRegister rd, QRegister rn, const QOperand& operand) {
8285     Vorr(al, dt, rd, rn, operand);
8288             QRegister rd,
8291     Vorr(cond, kDataTypeValueNone, rd, rn, operand);
8293   void Vorr(QRegister rd, QRegister rn, const QOperand& operand) {
8294     Vorr(al, kDataTypeValueNone, rd, rn, operand);
8297   void Vpadal(Condition cond, DataType dt, DRegister rd, DRegister rm) {
8298     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8304     vpadal(cond, dt, rd, rm);
8306   void Vpadal(DataType dt, DRegister rd, DRegister rm) {
8307     Vpadal(al, dt, rd, rm);
8310   void Vpadal(Condition cond, DataType dt, QRegister rd, QRegister rm) {
8311     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8317     vpadal(cond, dt, rd, rm);
8319   void Vpadal(DataType dt, QRegister rd, QRegister rm) {
8320     Vpadal(al, dt, rd, rm);
8324 rd, DRegister rn, DRegister rm) {
8325     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8332     vpadd(cond, dt, rd, rn, rm);
8334   void Vpadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
8335     Vpadd(al, dt, rd, rn, rm);
8338   void Vpaddl(Condition cond, DataType dt, DRegister rd, DRegister rm) {
8339     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8345     vpaddl(cond, dt, rd, rm);
8347   void Vpaddl(DataType dt, DRegister rd, DRegister rm) {
8348     Vpaddl(al, dt, rd, rm);
8351   void Vpaddl(Condition cond, DataType dt, QRegister rd, QRegister rm) {
8352     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8358     vpaddl(cond, dt, rd, rm);
8360   void Vpaddl(DataType dt, QRegister rd, QRegister rm) {
8361     Vpaddl(al, dt, rd, rm);
8365       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
8366     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8373     vpmax(cond, dt, rd, rn, rm);
8375   void Vpmax(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
8376     Vpmax(al, dt, rd, rn, rm);
8380       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
8381     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8388     vpmin(cond, dt, rd, rn, rm);
8390   void Vpmin(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
8391     Vpmin(al, dt, rd, rn, rm);
8454   void Vqabs(Condition cond, DataType dt, DRegister rd, DRegister rm) {
8455     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8461     vqabs(cond, dt, rd, rm);
8463   void Vqabs(DataType dt, DRegister rd, DRegister rm) { Vqabs(al, dt, rd, rm); }
8465   void Vqabs(Condition cond, DataType dt, QRegister rd, QRegister rm) {
8466     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8472     vqabs(cond, dt, rd, rm);
8474   void Vqabs(DataType dt, QRegister rd, QRegister rm) { Vqabs(al, dt, rd, rm); }
8477       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
8478     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8485     vqadd(cond, dt, rd, rn, rm);
8487   void Vqadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
8488     Vqadd(al, dt, rd, rn, rm);
8492       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
8493     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8500     vqadd(cond, dt, rd, rn, rm);
8502   void Vqadd(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
8503     Vqadd(al, dt, rd, rn, rm);
8507       Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
8508     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8515     vqdmlal(cond, dt, rd, rn, rm);
8517   void Vqdmlal(DataType dt, QRegister rd, DRegister rn, DRegister rm) {
8518     Vqdmlal(al, dt, rd, rn, rm);
8523                QRegister rd,
8527     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8534     vqdmlal(cond, dt, rd, rn, dm, index);
8537       DataType dt, QRegister rd, DRegister rn, DRegister dm, unsigned index) {
8538     Vqdmlal(al, dt, rd, rn, dm, index);
8542       Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
8543     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8550     vqdmlsl(cond, dt, rd, rn, rm);
8552   void Vqdmlsl(DataType dt, QRegister rd, DRegister rn, DRegister rm) {
8553     Vqdmlsl(al, dt, rd, rn, rm);
8558                QRegister rd,
8562     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8569     vqdmlsl(cond, dt, rd, rn, dm, index);
8572       DataType dt, QRegister rd, DRegister rn, DRegister dm, unsigned index) {
8573     Vqdmlsl(al, dt, rd, rn, dm, index);
8577       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
8578     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8585     vqdmulh(cond, dt, rd, rn, rm);
8587   void Vqdmulh(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
8588     Vqdmulh(al, dt, rd, rn, rm);
8592       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
8593     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8600     vqdmulh(cond, dt, rd, rn, rm);
8602   void Vqdmulh(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
8603     Vqdmulh(al, dt, rd, rn, rm);
8608                DRegister rd,
8611     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8618     vqdmulh(cond, dt, rd, rn, rm);
8620   void Vqdmulh(DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) {
8621     Vqdmulh(al, dt, rd, rn, rm);
8626                QRegister rd,
8629     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8636     vqdmulh(cond, dt, rd, rn, rm);
8638   void Vqdmulh(DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) {
8639     Vqdmulh(al, dt, rd, rn, rm);
8643       Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
8644     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8651     vqdmull(cond, dt, rd, rn, rm);
8653   void Vqdmull(DataType dt, QRegister rd, DRegister rn, DRegister rm) {
8654     Vqdmull(al, dt, rd, rn, rm);
8659                QRegister rd,
8662     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8669     vqdmull(cond, dt, rd, rn, rm);
8671   void Vqdmull(DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) {
8672     Vqdmull(al, dt, rd, rn, rm);
8675   void Vqmovn(Condition cond, DataType dt, DRegister rd, QRegister rm) {
8676     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8682     vqmovn(cond, dt, rd, rm);
8684   void Vqmovn(DataType dt, DRegister rd, QRegister rm) {
8685     Vqmovn(al, dt, rd, rm);
8688   void Vqmovun(Condition cond, DataType dt, DRegister rd, QRegister rm) {
8689     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8695     vqmovun(cond, dt, rd, rm);
8697   void Vqmovun(DataType dt, DRegister rd, QRegister rm) {
8698     Vqmovun(al, dt, rd, rm);
8701   void Vqneg(Condition cond, DataType dt, DRegister rd, DRegister rm) {
8702     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8708     vqneg(cond, dt, rd, rm);
8710   void Vqneg(DataType dt, DRegister rd, DRegister rm) { Vqneg(al, dt, rd, rm); }
8712   void Vqneg(Condition cond, DataType dt, QRegister rd, QRegister rm) {
8713     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8719     vqneg(cond, dt, rd, rm);
8721   void Vqneg(DataType dt, QRegister rd, QRegister rm) { Vqneg(al, dt, rd, rm); }
8724       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
8725     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8732     vqrdmulh(cond, dt, rd, rn, rm);
8734   void Vqrdmulh(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
8735     Vqrdmulh(al, dt, rd, rn, rm);
8739       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
8740     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8747     vqrdmulh(cond, dt, rd, rn, rm);
8749   void Vqrdmulh(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
8750     Vqrdmulh(al, dt, rd, rn, rm);
8755                 DRegister rd,
8758     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8765     vqrdmulh(cond, dt, rd, rn, rm);
8767   void Vqrdmulh(DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) {
8768     Vqrdmulh(al, dt, rd, rn, rm);
8773                 QRegister rd,
8776     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8783     vqrdmulh(cond, dt, rd, rn, rm);
8785   void Vqrdmulh(DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) {
8786     Vqrdmulh(al, dt, rd, rn, rm);
8790       Condition cond, DataType dt, DRegister rd, DRegister rm, DRegister rn) {
8791     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8798     vqrshl(cond, dt, rd, rm, rn);
8800   void Vqrshl(DataType dt, DRegister rd, DRegister rm, DRegister rn) {
8801     Vqrshl(al, dt, rd, rm, rn);
8805       Condition cond, DataType dt, QRegister rd, QRegister rm, QRegister rn) {
8806     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8813     vqrshl(cond, dt, rd, rm, rn);
8815   void Vqrshl(DataType dt, QRegister rd, QRegister rm, QRegister rn) {
8816     Vqrshl(al, dt, rd, rm, rn);
8821                DRegister rd,
8824     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8831     vqrshrn(cond, dt, rd, rm, operand);
8834                DRegister rd,
8837     Vqrshrn(al, dt, rd, rm, operand);
8842                 DRegister rd,
8845     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8852     vqrshrun(cond, dt, rd, rm, operand);
8855                 DRegister rd,
8858     Vqrshrun(al, dt, rd, rm, operand);
8863              DRegister rd,
8866     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8873     vqshl(cond, dt, rd, rm, operand);
8875   void Vqshl(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
8876     Vqshl(al, dt, rd, rm, operand);
8881              QRegister rd,
8884     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8891     vqshl(cond, dt, rd, rm, operand);
8893   void Vqshl(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
8894     Vqshl(al, dt, rd, rm, operand);
8899               DRegister rd,
8902     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8909     vqshlu(cond, dt, rd, rm, operand);
8912               DRegister rd,
8915     Vqshlu(al, dt, rd, rm, operand);
8920               QRegister rd,
8923     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8930     vqshlu(cond, dt, rd, rm, operand);
8933               QRegister rd,
8936     Vqshlu(al, dt, rd, rm, operand);
8941               DRegister rd,
8944     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8951     vqshrn(cond, dt, rd, rm, operand);
8954               DRegister rd,
8957     Vqshrn(al, dt, rd, rm, operand);
8962                DRegister rd,
8965     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8972     vqshrun(cond, dt, rd, rm, operand);
8975                DRegister rd,
8978     Vqshrun(al, dt, rd, rm, operand);
8982       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
8983     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8990     vqsub(cond, dt, rd, rn, rm);
8992   void Vqsub(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
8993     Vqsub(al, dt, rd, rn, rm);
8997       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
8998     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9005     vqsub(cond, dt, rd, rn, rm);
9007   void Vqsub(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
9008     Vqsub(al, dt, rd, rn, rm);
9012       Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) {
9013     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9020     vraddhn(cond, dt, rd, rn, rm);
9022   void Vraddhn(DataType dt, DRegister rd, QRegister rn, QRegister rm) {
9023     Vraddhn(al, dt, rd, rn, rm);
9026   void Vrecpe(Condition cond, DataType dt, DRegister rd, DRegister rm) {
9027     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9033     vrecpe(cond, dt, rd, rm);
9035   void Vrecpe(DataType dt, DRegister rd, DRegister rm) {
9036     Vrecpe(al, dt, rd, rm);
9039   void Vrecpe(Condition cond, DataType dt, QRegister rd, QRegister rm) {
9040     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9046     vrecpe(cond, dt, rd, rm);
9048   void Vrecpe(DataType dt, QRegister rd, QRegister rm) {
9049     Vrecpe(al, dt, rd, rm);
9053       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
9054     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9061     vrecps(cond, dt, rd, rn, rm);
9063   void Vrecps(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
9064     Vrecps(al, dt, rd, rn, rm);
9068       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
9069     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9076     vrecps(cond, dt, rd, rn, rm);
9078   void Vrecps(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
9079     Vrecps(al, dt, rd, rn, rm);
9082   void Vrev16(Condition cond, DataType dt, DRegister rd, DRegister rm) {
9083     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9089     vrev16(cond, dt, rd, rm);
9091   void Vrev16(DataType dt, DRegister rd, DRegister rm) {
9092     Vrev16(al, dt, rd, rm);
9095   void Vrev16(Condition cond, DataType dt, QRegister rd, QRegister rm) {
9096     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9102     vrev16(cond, dt, rd, rm);
9104   void Vrev16(DataType dt, QRegister rd, QRegister rm) {
9105     Vrev16(al, dt, rd, rm);
9108   void Vrev32(Condition cond, DataType dt, DRegister rd, DRegister rm) {
9109     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9115     vrev32(cond, dt, rd, rm);
9117   void Vrev32(DataType dt, DRegister rd, DRegister rm) {
9118     Vrev32(al, dt, rd, rm);
9121   void Vrev32(Condition cond, DataType dt, QRegister rd, QRegister rm) {
9122     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9128     vrev32(cond, dt, rd, rm);
9130   void Vrev32(DataType dt, QRegister rd, QRegister rm) {
9131     Vrev32(al, dt, rd, rm);
9134   void Vrev64(Condition cond, DataType dt, DRegister rd, DRegister rm) {
9135     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9141     vrev64(cond, dt, rd, rm);
9143   void Vrev64(DataType dt, DRegister rd, DRegister rm) {
9144     Vrev64(al, dt, rd, rm);
9147   void Vrev64(Condition cond, DataType dt, QRegister rd, QRegister rm) {
9148     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9154     vrev64(cond, dt, rd, rm);
9156   void Vrev64(DataType dt, QRegister rd, QRegister rm) {
9157     Vrev64(al, dt, rd, rm);
9161       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
9162     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9169     vrhadd(cond, dt, rd, rn, rm);
9171   void Vrhadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
9172     Vrhadd(al, dt, rd, rn, rm);
9176       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
9177     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9184     vrhadd(cond, dt, rd, rn, rm);
9186   void Vrhadd(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
9187     Vrhadd(al, dt, rd, rn, rm);
9190   void Vrinta(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
9191     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9196     vrinta(dt1, dt2, rd, rm);
9199   void Vrinta(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {
9200     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9205     vrinta(dt1, dt2, rd, rm);
9208   void Vrinta(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
9209     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9214     vrinta(dt1, dt2, rd, rm);
9217   void Vrintm(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
9218     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9223     vrintm(dt1, dt2, rd, rm);
9226   void Vrintm(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {
9227     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9232     vrintm(dt1, dt2, rd, rm);
9235   void Vrintm(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
9236     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9241     vrintm(dt1, dt2, rd, rm);
9244   void Vrintn(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
9245     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9250     vrintn(dt1, dt2, rd, rm);
9253   void Vrintn(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {
9254     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9259     vrintn(dt1, dt2, rd, rm);
9262   void Vrintn(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
9263     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9268     vrintn(dt1, dt2, rd, rm);
9271   void Vrintp(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
9272     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9277     vrintp(dt1, dt2, rd, rm);
9280   void Vrintp(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {
9281     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9286     vrintp(dt1, dt2, rd, rm);
9289   void Vrintp(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
9290     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9295     vrintp(dt1, dt2, rd, rm);
9299       Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
9300     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9306     vrintr(cond, dt1, dt2, rd, rm);
9308   void Vrintr(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
9309     Vrintr(al, dt1, dt2, rd, rm);
9313       Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
9314     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9320     vrintr(cond, dt1, dt2, rd, rm);
9322   void Vrintr(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
9323     Vrintr(al, dt1, dt2, rd, rm);
9327       Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
9328     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9334     vrintx(cond, dt1, dt2, rd, rm);
9336   void Vrintx(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
9337     Vrintx(al, dt1, dt2, rd, rm);
9340   void Vrintx(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {
9341     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9346     vrintx(dt1, dt2, rd, rm);
9350       Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
9351     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9357     vrintx(cond, dt1, dt2, rd, rm);
9359   void Vrintx(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
9360     Vrintx(al, dt1, dt2, rd, rm);
9364       Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
9365     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9371     vrintz(cond, dt1, dt2, rd, rm);
9373   void Vrintz(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
9374     Vrintz(al, dt1, dt2, rd, rm);
9377   void Vrintz(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {
9378     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9383     vrintz(dt1, dt2, rd, rm);
9387       Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
9388     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9394     vrintz(cond, dt1, dt2, rd, rm);
9396   void Vrintz(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
9397     Vrintz(al, dt1, dt2, rd, rm);
9401       Condition cond, DataType dt, DRegister rd, DRegister rm, DRegister rn) {
9402     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9409     vrshl(cond, dt, rd, rm, rn);
9411   void Vrshl(DataType dt, DRegister rd, DRegister rm, DRegister rn) {
9412     Vrshl(al, dt, rd, rm, rn);
9416       Condition cond, DataType dt, QRegister rd, QRegister rm, QRegister rn) {
9417     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9424     vrshl(cond, dt, rd, rm, rn);
9426   void Vrshl(DataType dt, QRegister rd, QRegister rm, QRegister rn) {
9427     Vrshl(al, dt, rd, rm, rn);
9432              DRegister rd,
9435     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9442     vrshr(cond, dt, rd, rm, operand);
9444   void Vrshr(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
9445     Vrshr(al, dt, rd, rm, operand);
9450              QRegister rd,
9453     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9460     vrshr(cond, dt, rd, rm, operand);
9462   void Vrshr(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
9463     Vrshr(al, dt, rd, rm, operand);
9468               DRegister rd,
9471     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9478     vrshrn(cond, dt, rd, rm, operand);
9481               DRegister rd,
9484     Vrshrn(al, dt, rd, rm, operand);
9487   void Vrsqrte(Condition cond, DataType dt, DRegister rd, DRegister rm) {
9488     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9494     vrsqrte(cond, dt, rd, rm);
9496   void Vrsqrte(DataType dt, DRegister rd, DRegister rm) {
9497     Vrsqrte(al, dt, rd, rm);
9500   void Vrsqrte(Condition cond, DataType dt, QRegister rd, QRegister rm) {
9501     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9507     vrsqrte(cond, dt, rd, rm);
9509   void Vrsqrte(DataType dt, QRegister rd, QRegister rm) {
9510     Vrsqrte(al, dt, rd, rm);
9514       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
9515     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9522     vrsqrts(cond, dt, rd, rn, rm);
9524   void Vrsqrts(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
9525     Vrsqrts(al, dt, rd, rn, rm);
9529       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
9530     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9537     vrsqrts(cond, dt, rd, rn, rm);
9539   void Vrsqrts(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
9540     Vrsqrts(al, dt, rd, rn, rm);
9545              DRegister rd,
9548     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9555     vrsra(cond, dt, rd, rm, operand);
9557   void Vrsra(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
9558     Vrsra(al, dt, rd, rm, operand);
9563              QRegister rd,
9566     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9573     vrsra(cond, dt, rd, rm, operand);
9575   void Vrsra(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
9576     Vrsra(al, dt, rd, rm, operand);
9580       Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) {
9581     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9588     vrsubhn(cond, dt, rd, rn, rm);
9590   void Vrsubhn(DataType dt, DRegister rd, QRegister rn, QRegister rm) {
9591     Vrsubhn(al, dt, rd, rn, rm);
9594   void Vseleq(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
9595     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9601     vseleq(dt, rd, rn, rm);
9604   void Vseleq(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
9605     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9611     vseleq(dt, rd, rn, rm);
9614   void Vselge(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
9615     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9621     vselge(dt, rd, rn, rm);
9624   void Vselge(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
9625     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9631     vselge(dt, rd, rn, rm);
9634   void Vselgt(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
9635     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9641     vselgt(dt, rd, rn, rm);
9644   void Vselgt(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
9645     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9651     vselgt(dt, rd, rn, rm);
9654   void Vselvs(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
9655     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9661     vselvs(dt, rd, rn, rm);
9664   void Vselvs(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
9665     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9671     vselvs(dt, rd, rn, rm);
9676             DRegister rd,
9679     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9686     vshl(cond, dt, rd, rm, operand);
9688   void Vshl(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
9689     Vshl(al, dt, rd, rm, operand);
9694             QRegister rd,
9697     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9704     vshl(cond, dt, rd, rm, operand);
9706   void Vshl(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
9707     Vshl(al, dt, rd, rm, operand);
9712              QRegister rd,
9715     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9722     vshll(cond, dt, rd, rm, operand);
9724   void Vshll(DataType dt, QRegister rd, DRegister rm, const DOperand& operand) {
9725     Vshll(al, dt, rd, rm, operand);
9730             DRegister rd,
9733     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9740     vshr(cond, dt, rd, rm, operand);
9742   void Vshr(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
9743     Vshr(al, dt, rd, rm, operand);
9748             QRegister rd,
9751     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9758     vshr(cond, dt, rd, rm, operand);
9760   void Vshr(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
9761     Vshr(al, dt, rd, rm, operand);
9766              DRegister rd,
9769     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9776     vshrn(cond, dt, rd, rm, operand);
9778   void Vshrn(DataType dt, DRegister rd, QRegister rm, const QOperand& operand) {
9779     Vshrn(al, dt, rd, rm, operand);
9784             DRegister rd,
9787     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9794     vsli(cond, dt, rd, rm, operand);
9796   void Vsli(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
9797     Vsli(al, dt, rd, rm, operand);
9802             QRegister rd,
9805     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9812     vsli(cond, dt, rd, rm, operand);
9814   void Vsli(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
9815     Vsli(al, dt, rd, rm, operand);
9818   void Vsqrt(Condition cond, DataType dt, SRegister rd, SRegister rm) {
9819     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9825     vsqrt(cond, dt, rd, rm);
9827   void Vsqrt(DataType dt, SRegister rd, SRegister rm) { Vsqrt(al, dt, rd, rm); }
9829   void Vsqrt(Condition cond, DataType dt, DRegister rd, DRegister rm) {
9830     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9836     vsqrt(cond, dt, rd, rm);
9838   void Vsqrt(DataType dt, DRegister rd, DRegister rm) { Vsqrt(al, dt, rd, rm); }
9842             DRegister rd,
9845     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9852     vsra(cond, dt, rd, rm, operand);
9854   void Vsra(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
9855     Vsra(al, dt, rd, rm, operand);
9860             QRegister rd,
9863     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9870     vsra(cond, dt, rd, rm, operand);
9872   void Vsra(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
9873     Vsra(al, dt, rd, rm, operand);
9878             DRegister rd,
9881     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9888     vsri(cond, dt, rd, rm, operand);
9890   void Vsri(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
9891     Vsri(al, dt, rd, rm, operand);
9896             QRegister rd,
9899     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9906     vsri(cond, dt, rd, rm, operand);
9908   void Vsri(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
9909     Vsri(al, dt, rd, rm, operand);
10178             DRegister rd,
10180     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10186     vstr(cond, dt, rd, operand);
10188   void Vstr(DataType dt, DRegister rd, const MemOperand& operand) {
10189     Vstr(al, dt, rd, operand);
10191   void Vstr(Condition cond, DRegister rd, const MemOperand& operand) {
10192     Vstr(cond, Untyped64, rd, operand);
10194   void Vstr(DRegister rd, const MemOperand& operand) {
10195     Vstr(al, Untyped64, rd, operand);
10200             SRegister rd,
10202     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10208     vstr(cond, dt, rd, operand);
10210   void Vstr(DataType dt, SRegister rd, const MemOperand& operand) {
10211     Vstr(al, dt, rd, operand);
10213   void Vstr(Condition cond, SRegister rd, const MemOperand& operand) {
10214     Vstr(cond, Untyped32, rd, operand);
10216   void Vstr(SRegister rd, const MemOperand& operand) {
10217     Vstr(al, Untyped32, rd, operand);
10221       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
10222     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10229     vsub(cond, dt, rd, rn, rm);
10231   void Vsub(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
10232     Vsub(al, dt, rd, rn, rm);
10236       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
10237     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10244     vsub(cond, dt, rd, rn, rm);
10246   void Vsub(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
10247     Vsub(al, dt, rd, rn, rm);
10251       Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
10252     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10259     vsub(cond, dt, rd, rn, rm);
10261   void Vsub(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
10262     Vsub(al, dt, rd, rn, rm);
10266       Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) {
10267     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10274     vsubhn(cond, dt, rd, rn, rm);
10276   void Vsubhn(DataType dt, DRegister rd, QRegister rn, QRegister rm) {
10277     Vsubhn(al, dt, rd, rn, rm);
10281       Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
10282     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10289     vsubl(cond, dt, rd, rn, rm);
10291   void Vsubl(DataType dt, QRegister rd, DRegister rn, DRegister rm) {
10292     Vsubl(al, dt, rd, rn, rm);
10296       Condition cond, DataType dt, QRegister rd, QRegister rn, DRegister rm) {
10297     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10304     vsubw(cond, dt, rd, rn, rm);
10306   void Vsubw(DataType dt, QRegister rd, QRegister rn, DRegister rm) {
10307     Vsubw(al, dt, rd, rn, rm);
10310   void Vswp(Condition cond, DataType dt, DRegister rd, DRegister rm) {
10311     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10317     vswp(cond, dt, rd, rm);
10319   void Vswp(DataType dt, DRegister rd, DRegister rm) { Vswp(al, dt, rd, rm); }
10320   void Vswp(Condition cond, DRegister rd, DRegister rm) {
10321     Vswp(cond, kDataTypeValueNone, rd, rm);
10323   void Vswp(DRegister rd, DRegister rm) {
10324     Vswp(al, kDataTypeValueNone, rd, rm);
10327   void Vswp(Condition cond, DataType dt, QRegister rd, QRegister rm) {
10328     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10334     vswp(cond, dt, rd, rm);
10336   void Vswp(DataType dt, QRegister rd, QRegister rm) { Vswp(al, dt, rd, rm); }
10337   void Vswp(Condition cond, QRegister rd, QRegister rm) {
10338     Vswp(cond, kDataTypeValueNone, rd, rm);
10340   void Vswp(QRegister rd, QRegister rm) {
10341     Vswp(al, kDataTypeValueNone, rd, rm);
10346             DRegister rd,
10349     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10356     vtbl(cond, dt, rd, nreglist, rm);
10359             DRegister rd,
10362     Vtbl(al, dt, rd, nreglist, rm);
10367             DRegister rd,
10370     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10377     vtbx(cond, dt, rd, nreglist, rm);
10380             DRegister rd,
10383     Vtbx(al, dt, rd, nreglist, rm);
10386   void Vtrn(Condition cond, DataType dt, DRegister rd, DRegister rm) {
10387     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10393     vtrn(cond, dt, rd, rm);
10395   void Vtrn(DataType dt, DRegister rd, DRegister rm) { Vtrn(al, dt, rd, rm); }
10397   void Vtrn(Condition cond, DataType dt, QRegister rd, QRegister rm) {
10398     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10404     vtrn(cond, dt, rd, rm);
10406   void Vtrn(DataType dt, QRegister rd, QRegister rm) { Vtrn(al, dt, rd, rm); }
10409       Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
10410     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10417     vtst(cond, dt, rd, rn, rm);
10419   void Vtst(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
10420     Vtst(al, dt, rd, rn, rm);
10424       Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
10425     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10432     vtst(cond, dt, rd, rn, rm);
10434   void Vtst(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
10435     Vtst(al, dt, rd, rn, rm);
10438   void Vuzp(Condition cond, DataType dt, DRegister rd, DRegister rm) {
10439     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10445     vuzp(cond, dt, rd, rm);
10447   void Vuzp(DataType dt, DRegister rd, DRegister rm) { Vuzp(al, dt, rd, rm); }
10449   void Vuzp(Condition cond, DataType dt, QRegister rd, QRegister rm) {
10450     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10456     vuzp(cond, dt, rd, rm);
10458   void Vuzp(DataType dt, QRegister rd, QRegister rm) { Vuzp(al, dt, rd, rm); }
10460   void Vzip(Condition cond, DataType dt, DRegister rd, DRegister rm) {
10461     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10467     vzip(cond, dt, rd, rm);
10469   void Vzip(DataType dt, DRegister rd, DRegister rm) { Vzip(al, dt, rd, rm); }
10471   void Vzip(Condition cond, DataType dt, QRegister rd, QRegister rm) {
10472     VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10478     vzip(cond, dt, rd, rm);
10480   void Vzip(DataType dt, QRegister rd, QRegister rm) { Vzip(al, dt, rd, rm); }
10490   void Vabs(Condition cond, VRegister rd, VRegister rm) {
10491     VIXL_ASSERT(rd.IsS() || rd.IsD());
10492     VIXL_ASSERT(rd.GetType() == rm.GetType());
10493     if (rd.IsS()) {
10494       Vabs(cond, F32, rd.S(), rm.S());
10496       Vabs(cond, F64, rd.D(), rm.D());
10499   void Vabs(VRegister rd, VRegister rm) { Vabs(al, rd, rm); }
10500   void Vadd(Condition cond, VRegister rd, VRegister rn, VRegister rm) {
10501     VIXL_ASSERT(rd.IsS() || rd.IsD());
10502     VIXL_ASSERT(rd.GetType() == rn.GetType());
10503     VIXL_ASSERT(rd.GetType() == rm.GetType());
10504     if (rd.IsS()) {
10505       Vadd(cond, F32, rd.S(), rn.S(), rm.S());
10507       Vadd(cond, F64, rd.D(), rn.D(), rm.D());
10510   void Vadd(VRegister rd, VRegister rn, VRegister rm) { Vadd(al, rd, rn, rm); }
10511   void Vcmp(Condition cond, VRegister rd, VRegister rm) {
10512     VIXL_ASSERT(rd.IsS() || rd.IsD());
10513     VIXL_ASSERT(rd.GetType() == rm.GetType());
10514     if (rd.IsS()) {
10515       Vcmp(cond, F32, rd.S(), rm.S());
10517       Vcmp(cond, F64, rd.D(), rm.D());
10520   void Vcmp(VRegister rd, VRegister rm) { Vcmp(al, rd, rm); }
10521   void Vcmpe(Condition cond, VRegister rd, VRegister rm) {
10522     VIXL_ASSERT(rd.IsS() || rd.IsD());
10523     VIXL_ASSERT(rd.GetType() == rm.GetType());
10524     if (rd.IsS()) {
10525       Vcmpe(cond, F32, rd.S(), rm.S());
10527       Vcmpe(cond, F64, rd.D(), rm.D());
10530   void Vcmpe(VRegister rd, VRegister rm) { Vcmpe(al, rd, rm); }
10531   void Vdiv(Condition cond, VRegister rd, VRegister rn, VRegister rm) {
10532     VIXL_ASSERT(rd.IsS() || rd.IsD());
10533     VIXL_ASSERT(rd.GetType() == rn.GetType());
10534     VIXL_ASSERT(rd.GetType() == rm.GetType());
10535     if (rd.IsS()) {
10536       Vdiv(cond, F32, rd.S(), rn.S(), rm.S());
10538       Vdiv(cond, F64, rd.D(), rn.D(), rm.D());
10541   void Vdiv(VRegister rd, VRegister rn, VRegister rm) { Vdiv(al, rd, rn, rm); }
10542   void Vfma(Condition cond, VRegister rd, VRegister rn, VRegister rm) {
10543     VIXL_ASSERT(rd.IsS() || rd.IsD());
10544     VIXL_ASSERT(rd.GetType() == rn.GetType());
10545     VIXL_ASSERT(rd.GetType() == rm.GetType());
10546     if (rd.IsS()) {
10547       Vfma(cond, F32, rd.S(), rn.S(), rm.S());
10549       Vfma(cond, F64, rd.D(), rn.D(), rm.D());
10552   void Vfma(VRegister rd, VRegister rn, VRegister rm) { Vfma(al, rd, rn, rm); }
10553   void Vfms(Condition cond, VRegister rd, VRegister rn, VRegister rm) {
10554     VIXL_ASSERT(rd.IsS() || rd.IsD());
10555     VIXL_ASSERT(rd.GetType() == rn.GetType());
10556     VIXL_ASSERT(rd.GetType() == rm.GetType());
10557     if (rd.IsS()) {
10558       Vfms(cond, F32, rd.S(), rn.S(), rm.S());
10560       Vfms(cond, F64, rd.D(), rn.D(), rm.D());
10563   void Vfms(VRegister rd, VRegister rn, VRegister rm) { Vfms(al, rd, rn, rm); }
10564   void Vfnma(Condition cond, VRegister rd
10565     VIXL_ASSERT(rd.IsS() || rd.IsD());
10566     VIXL_ASSERT(rd.GetType() == rn.GetType());
10567     VIXL_ASSERT(rd.GetType() == rm.GetType());
10568     if (rd.IsS()) {
10569       Vfnma(cond, F32, rd.S(), rn.S(), rm.S());
10571       Vfnma(cond, F64, rd.D(), rn.D(), rm.D());
10574   void Vfnma(VRegister rd, VRegister rn, VRegister rm) {
10575     Vfnma(al, rd, rn, rm);
10577   void Vfnms(Condition cond, VRegister rd, VRegister rn, VRegister rm) {
10578     VIXL_ASSERT(rd.IsS() || rd.IsD());
10579     VIXL_ASSERT(rd.GetType() == rn.GetType());
10580     VIXL_ASSERT(rd.GetType() == rm.GetType());
10581     if (rd.IsS()) {
10582       Vfnms(cond, F32, rd.S(), rn.S(), rm.S());
10584       Vfnms(cond, F64, rd.D(), rn.D(), rm.D());
10587   void Vfnms(VRegister rd, VRegister rn, VRegister rm) {
10588     Vfnms(al, rd, rn, rm);
10590   void Vmaxnm(VRegister rd, VRegister rn, VRegister rm) {
10591     VIXL_ASSERT(rd.IsS() || rd.IsD());
10592     VIXL_ASSERT(rd.GetType() == rn.GetType());
10593     VIXL_ASSERT(rd.GetType() == rm.GetType());
10594     if (rd.IsS()) {
10595       Vmaxnm(F32, rd.S(), rn.S(), rm.S());
10597       Vmaxnm(F64, rd.D(), rn.D(), rm.D());
10600   void Vminnm(VRegister rd, VRegister rn, VRegister rm) {
10601     VIXL_ASSERT(rd.IsS() || rd.IsD());
10602     VIXL_ASSERT(rd.GetType() == rn.GetType());
10603     VIXL_ASSERT(rd.GetType() == rm.GetType());
10604     if (rd.IsS()) {
10605       Vminnm(F32, rd.S(), rn.S(), rm.S());
10607       Vminnm(F64, rd.D(), rn.D(), rm.D());
10610   void Vmla(Condition cond, VRegister rd, VRegister rn, VRegister rm) {
10611     VIXL_ASSERT(rd.IsS() || rd.IsD());
10612     VIXL_ASSERT(rd.GetType() == rn.GetType());
10613     VIXL_ASSERT(rd.GetType() == rm.GetType());
10614     if (rd.IsS()) {
10615       Vmla(cond, F32, rd.S(), rn.S(), rm.S());
10617       Vmla(cond, F64, rd.D(), rn.D(), rm.D());
10620   void Vmla(VRegister rd, VRegister rn, VRegister rm) { Vmla(al, rd, rn, rm); }
10621   void Vmls(Condition cond, VRegister rd, VRegister rn, VRegister rm) {
10622     VIXL_ASSERT(rd.IsS() || rd.IsD());
10623     VIXL_ASSERT(rd.GetType() == rn.GetType());
10624     VIXL_ASSERT(rd.GetType() == rm.GetType());
10625     if (rd.IsS()) {
10626       Vmls(cond, F32, rd.S(), rn.S(), rm.S());
10628       Vmls(cond, F64, rd.D(), rn.D(), rm.D());
10631   void Vmls(VRegister rd, VRegister rn, VRegister rm) { Vmls(al, rd, rn, rm); }
10632   void Vmov(Condition cond, VRegister rd, VRegister rm) {
10633     VIXL_ASSERT(rd.IsS() || rd.IsD());
10634     VIXL_ASSERT(rd.GetType() == rm.GetType());
10635     if (rd.IsS()) {
10636       Vmov(cond, F32, rd.S(), rm.S());
10638       Vmov(cond, F64, rd.D(), rm.D());
10641   void Vmov(VRegister rd, VRegister rm) { Vmov(al, rd, rm); }
10642   void Vmul(Condition cond, VRegister rd, VRegister rn, VRegister rm) {
10643     VIXL_ASSERT(rd.IsS() || rd.IsD());
10644     VIXL_ASSERT(rd.GetType() == rn.GetType());
10645     VIXL_ASSERT(rd.GetType() == rm.GetType());
10646     if (rd.IsS()) {
10647       Vmul(cond, F32, rd.S(), rn.S(), rm.S());
10649       Vmul(cond, F64, rd.D(), rn.D(), rm.D());
10652   void Vmul(VRegister rd, VRegister rn, VRegister rm) { Vmul(al, rd, rn, rm); }
10653   void Vneg(Condition cond, VRegister rd, VRegister rm) {
10654     VIXL_ASSERT(rd.IsS() || rd.IsD());
10655     VIXL_ASSERT(rd.GetType() == rm.GetType());
10656     if (rd.IsS()) {
10657       Vneg(cond, F32, rd.S(), rm.S());
10659       Vneg(cond, F64, rd.D(), rm.D());
10662   void Vneg(VRegister rd, VRegister rm) { Vneg(al, rd, rm); }
10663   void Vnmla(Condition cond, VRegister rd, VRegister rn, VRegister rm) {
10664     VIXL_ASSERT(rd.IsS() || rd.IsD());
10665     VIXL_ASSERT(rd.GetType() == rn.GetType());
10666     VIXL_ASSERT(rd.GetType() == rm.GetType());
10667     if (rd.IsS()) {
10668       Vnmla(cond, F32, rd.S(), rn.S(), rm.S());
10670       Vnmla(cond, F64, rd.D(), rn.D(), rm.D());
10673   void Vnmla(VRegister rd, VRegister rn, VRegister rm) {
10674     Vnmla(al, rd, rn, rm);
10676   void Vnmls(Condition cond, VRegister rd, VRegister rn, VRegister rm) {
10677     VIXL_ASSERT(rd.IsS() || rd.IsD());
10678     VIXL_ASSERT(rd.GetType() == rn.GetType());
10679     VIXL_ASSERT(rd.GetType() == rm.GetType());
10680     if (rd.IsS()) {
10681       Vnmls(cond, F32, rd.S(), rn.S(), rm.S());
10683       Vnmls(cond, F64, rd.D(), rn.D(), rm.D());
10686   void Vnmls(VRegister rd, VRegister rn, VRegister rm) {
10687     Vnmls(al, rd, rn, rm);
10689   void Vnmul(Condition cond, VRegister rd, VRegister rn, VRegister rm) {
10690     VIXL_ASSERT(rd.IsS() || rd.IsD());
10691     VIXL_ASSERT(rd.GetType() == rn.GetType());
10692     VIXL_ASSERT(rd.GetType() == rm.GetType());
10693     if (rd.IsS()) {
10694       Vnmul(cond, F32, rd.S(), rn.S(), rm.S());
10696       Vnmul(cond, F64, rd.D(), rn.D(), rm.D());
10699   void Vnmul(VRegister rd, VRegister rn, VRegister rm) {
10700     Vnmul(al, rd, rn, rm);
10702   void Vseleq(VRegister rd, VRegister rn, VRegister rm) {
10703     VIXL_ASSERT(rd.IsS() || rd.IsD());
10704     VIXL_ASSERT(rd.GetType() == rn.GetType());
10705     VIXL_ASSERT(rd.GetType() == rm.GetType());
10706     if (rd.IsS()) {
10707       Vseleq(F32, rd.S(), rn.S(), rm.S());
10709       Vseleq(F64, rd.D(), rn.D(), rm.D());
10712   void Vselge(VRegister rd, VRegister rn, VRegister rm) {
10713     VIXL_ASSERT(rd.IsS() || rd.IsD());
10714     VIXL_ASSERT(rd.GetType() == rn.GetType());
10715     VIXL_ASSERT(rd.GetType() == rm.GetType());
10716     if (rd.IsS()) {
10717       Vselge(F32, rd.S(), rn.S(), rm.S());
10719       Vselge(F64, rd.D(), rn.D(), rm.D());
10722   void Vselgt(VRegister rd, VRegister rn, VRegister rm) {
10723     VIXL_ASSERT(rd.IsS() || rd.IsD());
10724     VIXL_ASSERT(rd.GetType() == rn.GetType());
10725     VIXL_ASSERT(rd.GetType() == rm.GetType());
10726     if (rd.IsS()) {
10727       Vselgt(F32, rd.S(), rn.S(), rm.S());
10729       Vselgt(F64, rd.D(), rn.D(), rm.D());
10732   void Vselvs(VRegister rd, VRegister rn, VRegister rm) {
10733     VIXL_ASSERT(rd.IsS() || rd.IsD());
10734     VIXL_ASSERT(rd.GetType() == rn.GetType());
10735     VIXL_ASSERT(rd.GetType() == rm.GetType());
10736     if (rd.IsS()) {
10737       Vselvs(F32, rd.S(), rn.S(), rm.S());
10739       Vselvs(F64, rd.D(), rn.D(), rm.D());
10742   void Vsqrt(Condition cond, VRegister rd, VRegister rm) {
10743     VIXL_ASSERT(rd.IsS() || rd.IsD());
10744     VIXL_ASSERT(rd.GetType() == rm.GetType());
10745     if (rd.IsS()) {
10746       Vsqrt(cond, F32, rd.S(), rm.S());
10748       Vsqrt(cond, F64, rd.D(), rm.D());
10751   void Vsqrt(VRegister rd, VRegister rm) { Vsqrt(al, rd, rm); }
10752   void Vsub(Condition cond, VRegister rd, VRegister rn, VRegister rm) {
10753     VIXL_ASSERT(rd.IsS() || rd.IsD());
10754     VIXL_ASSERT(rd.GetType() == rn.GetType());
10755     VIXL_ASSERT(rd.GetType() == rm.GetType());
10756     if (rd.IsS()) {
10757       Vsub(cond, F32, rd.S(), rn.S(), rm.S());
10759       Vsub(cond, F64, rd.D(), rn.D(), rm.D());
10762   void Vsub(VRegister rd, VRegister rn, VRegister rm) { Vsub(al, rd, rn, rm); }
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