Home | History | Annotate | Download | only in aarch64

Lines Matching full:shiftreg

1644   LogicVRegister shiftreg = dup_immediate(vform, temp, shift);
1645   return ushl(vform, dst, src, shiftreg);
1655   LogicVRegister shiftreg = dup_immediate(vform, temp1, shift);
1657   return sshl(vform, dst, extendedreg, shiftreg);
1667   LogicVRegister shiftreg = dup_immediate(vform, temp1, shift);
1669   return sshl(vform, dst, extendedreg, shiftreg);
1695   LogicVRegister shiftreg = dup_immediate(vform, temp1, shift);
1697   return ushl(vform, dst, extendedreg, shiftreg);
1707   LogicVRegister shiftreg = dup_immediate(vform, temp1, shift);
1709   return ushl(vform, dst, extendedreg, shiftreg);
1736   LogicVRegister shiftreg = dup_immediate(vform, temp, shift);
1737   return sshl(vform, dst, src, shiftreg).SignedSaturate(vform);
1747   LogicVRegister shiftreg = dup_immediate(vform, temp, shift);
1748   return ushl(vform, dst, src, shiftreg).UnsignedSaturate(vform);
1758   LogicVRegister shiftreg = dup_immediate(vform, temp, shift);
1759   return sshl(vform, dst, src, shiftreg).UnsignedSaturate(vform);
1795   LogicVRegister shiftreg = dup_immediate(vform, temp, -shift);
1796   return ushl(vform, dst, src, shiftreg);
1806   LogicVRegister shiftreg = dup_immediate(vform, temp, -shift);
1807   return sshl(vform, dst, src, shiftreg);