Lines Matching full:shift_amount
300 Operand::Operand(Register reg, Shift shift, unsigned shift_amount)
304 shift_amount_(shift_amount) {
306 VIXL_ASSERT(reg.Is64Bits() || (shift_amount < kWRegSize));
307 VIXL_ASSERT(reg.Is32Bits() || (shift_amount < kXRegSize));
312 Operand::Operand(Register reg, Extend extend, unsigned shift_amount)
316 shift_amount_(shift_amount) {
318 VIXL_ASSERT(shift_amount <= 4);
397 unsigned shift_amount)
404 shift_amount_(shift_amount) {
417 unsigned shift_amount)
424 shift_amount_(shift_amount) {
