Lines Matching refs:u32
82 u32 timestamp;
91 u32 timestamp;
92 u32 reserved;
97 u32 first_mpdu : 1; //[0]
98 u32 last_mpdu : 1; //[1]
99 u32 reserved1 : 6; //[7:2]
100 u32 mgmt_type : 1; //[8]
101 u32 ctrl_type : 1; //[9]
102 u32 reserved2 : 6; //[15:10]
103 u32 overflow_err : 1; //[16]
104 u32 msdu_length_err : 1; //[17]
105 u32 tcp_udp_chksum_fail : 1; //[18]
106 u32 ip_chksum_fail : 1; //[19]
107 u32 reserved3 : 7; //[26:20]
108 u32 mpdu_length_err : 1; //[27]
109 u32 tkip_mic_err : 1; //[28]
110 u32 decrypt_err : 1; //[29]
111 u32 fcs_err : 1; //[30]
112 u32 msdu_done : 1; //[31]
116 u32 reserved1 : 13; //[12:0]
117 u32 encrypted : 1; //[13]
118 u32 retry : 1; //[14]
119 u32 reserved2 : 1; //[15]
120 u32 seq_num : 12; //[27:16]
121 u32 reserved3 : 4; //[31:28]
122 u32 reserved4;
123 u32 reserved5 : 28; //[27:0]
124 u32 tid : 4; //[31:28]
136 u32 reserved1[2];
137 u32 reserved2 : 8; //[7:0]
138 u32 decap_format : 2; //[9:8]
139 u32 reserved3 : 22; //[31:10]
143 u32 reserved1[4];
144 u32 reserved2 : 15;
145 u32 last_msdu : 1; //[15]
146 u32 reserved3 : 16; //[31:16]
150 u32 reserved1 : 13; //[12:0]
151 u32 overflow_err : 1; //[13]
152 u32 last_mpdu : 1; //[14]
153 u32 post_delim_err : 1; //[15]
154 u32 reserved2 : 12; //[27:16]
155 u32 mpdu_length_err : 1; //[28]
156 u32 tkip_mic_err : 1; //[29]
157 u32 decrypt_err : 1; //[30]
158 u32 fcs_err : 1; //[31]
178 u32 reserved1[4];
179 u32 rssi_comb : 8; //[7:0]
180 u32 reserved2 : 24; //[31:8]
181 u32 l_sig_rate : 4; //[3:0]
182 u32 l_sig_rate_select : 1; //[4]
183 u32 reserved3 : 19; //[23:5]
184 u32 preamble_type : 8; //[31:24]
185 u32 ht_sig_vht_sig_a_1 : 24; //[23:0]
186 u32 reserved4 : 8; //[31:24]
187 u32 ht_sig_vht_sig_a_2 : 24; //[23:0]
188 u32 reserved5 : 8; //[31:25]
189 u32 reserved6[2];
193 u32 reserved1[16];
194 u32 tsf_timestamp;
195 u32 reserved2[5];
203 u32 reserved1;
215 u32 ba_start_seq_num : 12; //[11:0]
216 u32 reserved1 : 3; //[14:12]
217 u32 ba_status : 1; //[15]
218 u32 reserved2 : 15; //[30:16]
219 u32 tx_ok : 1; //[31]
220 u32 ba_bitmap_31_0 : 32; //[31:0]
221 u32 ba_bitmap_63_32 : 32; //[31:0]
222 u32 reserved3[8];
223 u32 ack_rssi_ave : 8; //[7:0]
224 u32 reserved4 : 16; //[23:8]
225 u32 total_tries : 5; //[28:24]
226 u32 reserved5 : 3; //[31:29]
227 u32 reserved6[4];
232 u32 timestamp : 23; //[22:0]
233 u32 reserved1 : 1; //[23]
234 u32 series : 1; //[24]
235 u32 reserved2 : 3; //[27:25]
236 u32 packet_bw : 2; //[29:28]
237 u32 reserved3 : 1; //[30]
238 u32 tx_packet : 1; //[31]
253 u32 reserved1 : 28; //[27:0]
254 u32 short_gi : 1; //[28]
255 u32 reserved2 : 3; //[31:29]
256 u32 reserved3 : 24; //[23:21]
257 u32 rate : 4; //[27:24]
258 u32 nss : 2; //[29:28]
259 u32 preamble_type : 2; //[31:30]
260 u32 reserved4[2];
272 u32 reserved1[2];
273 u32 start_seq_num : 12; //[11:0]
274 u32 reserved2 : 20; //[31:12]
275 u32 seqnum_bitmap_31_0 : 32; //[31:0]
276 u32 seqnum_bitmap_63_32 : 32; //[31:0]
277 u32 reserved3[8];
278 u32 reserved4 : 15; //[14:0]
279 u32 ampdu : 1; //[15]
280 u32 no_ack : 1; //[16]
281 u32 reserved5 : 15; //[31:17]
282 u32 reserved6 : 16; //[15:0]
283 u32 frame_control : 16; //[31:16]
284 u32 reserved7 : 16; //[23:21]
285 u32 qos_ctl : 16; //[31:16]
286 u32 reserved8[4];
287 u32 reserved9 : 24; //[23:21]
288 u32 valid_s0_bw20 : 1; //[24]
289 u32 valid_s0_bw40 : 1; //[25]
290 u32 valid_s0_bw80 : 1; //[26]
291 u32 valid_s0_bw160 : 1; //[27]
292 u32 valid_s1_bw20 : 1; //[28]
293 u32 valid_s1_bw40 : 1; //[29]
294 u32 valid_s1_bw80 : 1; //[30]
295 u32 valid_s1_bw160 : 1; //[31]
304 u32 reserved10[3];
309 u32 reserved1[3];
311 u32 txdesc_ctl[PKTLOG_MAX_TXCTL_WORDS];
338 u32 ba_bitmap_31_0;
339 u32 ba_bitmap_63_32;
340 u32 tx_seqnum_bitmap_31_0;
341 u32 tx_seqnum_bitmap_63_32;
342 u32 shifted_bitmap_31_0;
343 u32 shifted_bitmap_63_32;
365 u32 timestamp;
374 u32 timestamp_low;
375 u32 timestamp_high;
378 u32 version;
379 u32 msg_seq_no;
380 u32 payload_len;
398 u32 driver_ts;
404 u32 driver_timestamp_usec;
405 u32 firmware_timestamp_usec;
