Lines Matching refs:pe
80 struct perf_event_attr pe;
81 memset(&pe, 0, sizeof(struct perf_event_attr));
82 pe.type = PERF_TYPE_HARDWARE;
83 pe.size = sizeof(struct perf_event_attr);
84 pe.config = PERF_COUNT_HW_INSTRUCTIONS;
85 pe.disabled = 1;
86 pe.exclude_kernel = 1;
87 pe.exclude_hv = 1;
88 pe.read_format = PERF_FORMAT_GROUP |
94 int fd = perf_event_open(&pe, 0, -1, -1, 0);
100 pe.read_format = PERF_FORMAT_GROUP | PERF_FORMAT_ID;
103 pe.type = PERF_TYPE_HARDWARE;
104 pe.config = PERF_COUNT_HW_CPU_CYCLES;
105 mCountersFd[CPU_CYCLES] = perf_event_open(&pe, 0, -1, groupFd, 0);
113 pe.type = PERF_TYPE_HARDWARE;
114 pe.config = PERF_COUNT_HW_CACHE_REFERENCES;
115 mCountersFd[DCACHE_REFS] = perf_event_open(&pe, 0, -1, groupFd, 0);
123 pe.type = PERF_TYPE_HARDWARE;
124 pe.config = PERF_COUNT_HW_CACHE_MISSES;
125 mCountersFd[DCACHE_MISSES] = perf_event_open(&pe, 0, -1, groupFd, 0);
133 pe.type = PERF_TYPE_HARDWARE;
134 pe.config = PERF_COUNT_HW_BRANCH_INSTRUCTIONS;
135 mCountersFd[BRANCHES] = perf_event_open(&pe, 0, -1, groupFd, 0);
143 pe.type = PERF_TYPE_HARDWARE;
144 pe.config = PERF_COUNT_HW_BRANCH_MISSES;
145 mCountersFd[BRANCH_MISSES] = perf_event_open(&pe, 0, -1, groupFd, 0);
154 pe.type = PERF_TYPE_RAW;
155 pe.config = ARMV8_PMUV3_PERFCTR_L1_ICACHE_ACCESS;
156 mCountersFd[ICACHE_REFS] = perf_event_open(&pe, 0, -1, groupFd, 0);
164 pe.type = PERF_TYPE_RAW;
165 pe.config = ARMV8_PMUV3_PERFCTR_L1_ICACHE_REFILL;
166 mCountersFd[ICACHE_MISSES] = perf_event_open(&pe, 0, -1, groupFd, 0);
174 pe.type = PERF_TYPE_HW_CACHE;
175 pe.config = PERF_COUNT_HW_CACHE_L1I |
177 mCountersFd[ICACHE_REFS] = perf_event_open(&pe, 0, -1, groupFd, 0);
185 pe.type = PERF_TYPE_HW_CACHE;
186 pe.config = PERF_COUNT_HW_CACHE_L1I |
188 mCountersFd[ICACHE_MISSES] = perf_event_open(&pe, 0, -1, groupFd, 0);
