Lines Matching defs:sequence
956 them in variant frags. In position-dependent code, the first sequence
957 will be the GP-relative one and the second sequence will be the
958 absolute one. In SVR4 PIC, the first sequence will be for global
968 sequence instead of the first.
997 Relaxable macros are generated using a sequence such as:
1063 It would be possible to generate a shorter sequence by losing the
1158 branches to a sequence of instructions is enabled, and whether the
1243 int sequence;
1253 /* The symbol on which the choice of sequence depends. */
2343 if (mips_relax.sequence != 2)
4337 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
4343 gas_assert (mips_relax.sequence == 0);
4344 mips_relax.sequence = 1;
4348 /* Start generating the second version of a relaxable sequence.
4354 gas_assert (mips_relax.sequence == 1);
4355 mips_relax.sequence = 2;
4358 /* End the current relaxable sequence. */
4363 gas_assert (mips_relax.sequence == 2);
4365 mips_relax.sequence = 0;
6378 * A sequence of four stores occurs in consecutive cycles around the
6387 is being filled. The fourth instruction in the sequence above permits
6389 the cache. In the sequence above, the stores may be either integer
6393 running in 1:2 mode, it is not possible to create the sequence above
6399 cycle sequence shown above.
6528 would be needed after the extended sequence, ignoring hazards
6702 /* Check for conflicts between the swapped sequence and the
6817 /* The relaxed version of a macro sequence must be inherently
6819 if (mips_relax.sequence == 2)
7164 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
7211 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
7254 should refer to the start of the branch sequence. Using the
7309 gas_assert (!mips_relax.sequence);
7363 if (mips_relax.sequence)
7370 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
7373 if (mips_relax.sequence != 2)
7380 if (mips_relax.sequence != 1)
7454 if (mips_relax.sequence)
7513 if (mips_relax.sequence)
7514 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop);
8747 /* Generate a sequence of instructions to do a load or store from a constant
9163 the same sequence as in 32bit address space. */
9197 if (mips_relax.sequence)
9213 if (mips_relax.sequence)
9252 if (mips_relax.sequence)
9383 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
9395 a sequence to add a 32-bit offset using a scratch register. */
9458 /* Emit a sequence of instructions to emulate a branch likely operation.
10448 the same sequence as in 32bit address space. */
10488 if (mips_relax.sequence)
10506 if (mips_relax.sequence)
10530 sequence, but we output a BFD_RELOC_LO16 reloc on the
10540 sequence, but we output a BFD_RELOC_LO16 reloc on the
11778 the same sequence as in 32bit address space. */
11833 if (mips_relax.sequence)
11851 if (mips_relax.sequence)
11871 if (mips_relax.sequence)
12413 if (mips_relax.sequence)
15195 without turning it into a longer sequence. */
15989 the default instruction sequence. */
16885 /* Compute the length of a branch sequence, and adjust the
16914 we emit the long sequence. */
16948 /* Compute the length of a branch sequence, and adjust the
16982 we emit the long sequence. */
17687 /* Relax 32-bit branches to a sequence of instructions. */
17976 /* Go through all the fixups for the first sequence. Disable them
17978 sequence instead. */
17988 /* Go through the fixups for the second sequence. Disable them if
17989 we're going to use the first sequence, otherwise adjust their
