Lines Matching full:precision
144 Enable use of floating-point operations on odd-numbered single-precision
436 Disable or enable double-precision floating-point operations. Note
437 that by default double-precision floating-point operations are always
839 @item 1 - Double-precision
840 This variant indicates that double-precision support is used. For 64-bit
843 required and double-precision operations use pairs of registers.
845 @item 2 - Single-precision
846 This variant indicates that single-precision support is used. Double
847 precision operations will be supported via soft-float routines.
859 @item 5 - Double-precision 32-bit CPU, 32-bit or 64-bit FPU
862 32-bit wide or 64-bit wide floating-point registers. Double-precision
866 @item 6 - Double-precision 32-bit FPU, 64-bit FPU
869 Double-precision support is used. Only O32 currently supports this
872 @item 7 - Double-precision compat 32-bit FPU, 64-bit FPU
875 Double-precision support is used. This differs from the previous ABI
876 as it restricts use of odd-numbered single-precision registers. Only
894 single-precision. The remaining ABIs are then selected based
895 on the FP register width. Double-precision is selected if the width
896 of GP and FP registers match and the special double-precision variants
906 double-precision FP ABI variants. The @samp{-mfpxx} FP ABI is specifically
907 designed to be compatible with the standard double-precision ABI and the
911 be linked together are the standard double-precision ABI and the full
1080 @cindex Disable single-precision floating-point operations
1084 provide finer control of disabling and enabling double-precision
1086 (that double-precision operations are accepted) or the command-line
