Lines Matching refs:to2
10 vaddpd (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
15 vaddpd 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
16 vaddpd 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
17 vaddpd -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
18 vaddpd -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
90 vblendmpd (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
95 vblendmpd 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
96 vblendmpd 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
97 vblendmpd -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
98 vblendmpd -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
183 vcmppd $123, (%eax){1to2}, %xmm5, %k5{%k7} # AVX512{F,VL}
188 vcmppd $123, 1016(%edx){1to2}, %xmm5, %k5{%k7} # AVX512{F,VL} Disp8
189 vcmppd $123, 1024(%edx){1to2}, %xmm5, %k5{%k7} # AVX512{F,VL}
190 vcmppd $123, -1024(%edx){1to2}, %xmm5, %k5{%k7} # AVX512{F,VL} Disp8
191 vcmppd $123, -1032(%edx){1to2}, %xmm5, %k5{%k7} # AVX512{F,VL}
267 vcvtdq2pd (%eax){1to2}, %xmm6{%k7} # AVX512{F,VL}
272 vcvtdq2pd 508(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL} Disp8
273 vcvtdq2pd 512(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL}
274 vcvtdq2pd -512(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL} Disp8
275 vcvtdq2pd -516(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL}
319 vcvtpd2dq (%eax){1to2}, %xmm6{%k7} # AVX512{F,VL}
324 vcvtpd2dqx 1016(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL} Disp8
325 vcvtpd2dqx 1024(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL}
326 vcvtpd2dqx -1024(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL} Disp8
327 vcvtpd2dqx -1032(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL}
345 vcvtpd2ps (%eax){1to2}, %xmm6{%k7} # AVX512{F,VL}
350 vcvtpd2psx 1016(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL} Disp8
351 vcvtpd2psx 1024(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL}
352 vcvtpd2psx -1024(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL} Disp8
353 vcvtpd2psx -1032(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL}
371 vcvtpd2udq (%eax){1to2}, %xmm6{%k7} # AVX512{F,VL}
376 vcvtpd2udqx 1016(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL} Disp8
377 vcvtpd2udqx 1024(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL}
378 vcvtpd2udqx -1024(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL} Disp8
379 vcvtpd2udqx -1032(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL}
439 vcvtps2pd (%eax){1to2}, %xmm6{%k7} # AVX512{F,VL}
444 vcvtps2pd 508(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL} Disp8
445 vcvtps2pd 512(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL}
446 vcvtps2pd -512(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL} Disp8
447 vcvtps2pd -516(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL}
497 vcvttpd2dq (%eax){1to2}, %xmm6{%k7} # AVX512{F,VL}
502 vcvttpd2dqx 1016(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL} Disp8
503 vcvttpd2dqx 1024(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL}
504 vcvttpd2dqx -1024(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL} Disp8
505 vcvttpd2dqx -1032(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL}
549 vcvtudq2pd (%eax){1to2}, %xmm6{%k7} # AVX512{F,VL}
554 vcvtudq2pd 508(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL} Disp8
555 vcvtudq2pd 512(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL}
556 vcvtudq2pd -512(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL} Disp8
557 vcvtudq2pd -516(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL}
601 vdivpd (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
606 vdivpd 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
607 vdivpd 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
608 vdivpd -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
609 vdivpd -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
695 vfmadd132pd (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
700 vfmadd132pd 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
701 vfmadd132pd 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
702 vfmadd132pd -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
703 vfmadd132pd -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
747 vfmadd213pd (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
752 vfmadd213pd 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
753 vfmadd213pd 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
754 vfmadd213pd -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
755 vfmadd213pd -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
799 vfmadd231pd (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
804 vfmadd231pd 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
805 vfmadd231pd 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
806 vfmadd231pd -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
807 vfmadd231pd -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
851 vfmaddsub132pd (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
856 vfmaddsub132pd 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
857 vfmaddsub132pd 1024(%edx){1to2
858 vfmaddsub132pd -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
859 vfmaddsub132pd -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
903 vfmaddsub213pd (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
908 vfmaddsub213pd 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
909 vfmaddsub213pd 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
910 vfmaddsub213pd -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
911 vfmaddsub213pd -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
955 vfmaddsub231pd (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
960 vfmaddsub231pd 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
961 vfmaddsub231pd 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
962 vfmaddsub231pd -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
963 vfmaddsub231pd -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
1007 vfmsub132pd (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
1012 vfmsub132pd 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
1013 vfmsub132pd 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
1014 vfmsub132pd -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
1015 vfmsub132pd -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
1059 vfmsub213pd (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
1064 vfmsub213pd 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
1065 vfmsub213pd 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
1066 vfmsub213pd -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
1067 vfmsub213pd -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
1111 to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
1116 vfmsub231pd 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
1117 vfmsub231pd 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
1118 vfmsub231pd -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
1119 vfmsub231pd -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
1163 vfmsubadd132pd (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
1168 vfmsubadd132pd 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
1169 vfmsubadd132pd 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
1170 vfmsubadd132pd -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
1171 vfmsubadd132pd -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
1215 vfmsubadd213pd (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
1220 vfmsubadd213pd 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
1221 vfmsubadd213pd 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
1222 vfmsubadd213pd -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
1223 vfmsubadd213pd -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
1267 vfmsubadd231pd (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
1272 vfmsubadd231pd 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
1273 vfmsubadd231pd 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
1274 vfmsubadd231pd -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
1275 vfmsubadd231pd -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
1319 vfnmadd132pd (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
1324 vfnmadd132pd 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
1325 vfnmadd132pd 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
1326 vfnmadd132pd -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
1327 vfnmadd132pd -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
1371 vfnmadd213pd (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
1376 vfnmadd213pd 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
1377 vfnmadd213pd 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
1378 vfnmadd213pd -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
1379 vfnmadd213pd -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
1423 vfnmadd231pd (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
1428 vfnmadd231pd 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
1429 vfnmadd231pd 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
1430 vfnmadd231pd -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
1431 vfnmadd231pd -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
1475 vfnmsub132pd (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
1480 vfnmsub132pd 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
1481 vfnmsub132pd 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
1482 vfnmsub132pd -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
1483 vfnmsub132pd -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
1527 vfnmsub213pd (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
1532 vfnmsub213pd 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
1533 vfnmsub213pd 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
1534 vfnmsub213pd -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
1535 vfnmsub213pd -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
1579 vfnmsub231pd (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
1584 vfnmsub231pd 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
1585 vfnmsub231pd 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
1586 vfnmsub231pd -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
1587 vfnmsub231pd -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
1655 vgetexppd (%eax){1to2}, %xmm6{%k7} # AVX512{F,VL}
1660 vgetexppd 1016(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL} Disp8
1661 vgetexppd 1024(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL}
1662 vgetexppd -1024(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL} Disp8
1663 vgetexppd -1032(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL}
1708 vgetmantpd $123, (%eax){1to2}, %xmm6{%k7} # AVX512{F,VL}
1713 vgetmantpd $123, 1016(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL} Disp8
1714 vgetmantpd $123, 1024(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL}
1715 vgetmantpd $123, -1024(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL} Disp8
1716 vgetmantpd $123, -1032(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL}
1781 vmaxpd (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
1786 vmaxpd 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
1787 vmaxpd 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
1788 vmaxpd -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
1789 vmaxpd -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
1833 vminpd (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
1838 vminpd 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
1839 vminpd 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
1840 vminpd -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
1841 vminpd -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
2061 vmulpd (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
2066 vmulpd 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
2067 vmulpd 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
2068 vmulpd -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
2069 vmulpd -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
2139 vpabsq (%eax){1to2}, %xmm6{%k7} # AVX512{F,VL}
2144 vpabsq 1016(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL} Disp8
2145 vpabsq 1024(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL}
2146 vpabsq -1024(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL} Disp8
2147 vpabsq -1032(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL}
2191 vpaddq (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
2196 vpaddq 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
2197 vpaddq 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
2198 vpaddq -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
2199 vpaddq -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
2269 vpandnq (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
2274 vpandnq 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
2275 vpandnq 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
2276 vpandnq -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
2277 vpandnq -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
2295 vpandq (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
2300 vpandq 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
2301 vpandq 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
2302 vpandq -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
2303 vpandq -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
2438 vpcmpeqq (%eax){1to2}, %xmm6, %k5{%k7} # AVX512{F,VL}
2443 vpcmpeqq 1016(%edx){1to2}, %xmm6, %k5{%k7} # AVX512{F,VL} Disp8
2444 vpcmpeqq 1024(%edx){1to2}, %xmm6, %k5{%k7} # AVX512{F,VL}
2445 vpcmpeqq -1024(%edx){1to2}, %xmm6, %k5{%k7} # AVX512{F,VL} Disp8
2446 vpcmpeqq -1032(%edx){1to2}, %xmm6, %k5{%k7} # AVX512{F,VL}
2486 vpcmpgtq (%eax){1to2}, %xmm6, %k5{%k7} # AVX512{F,VL}
2491 vpcmpgtq 1016(%edx){1to2}, %xmm6, %k5{%k7} # AVX512{F,VL} Disp8
2492 vpcmpgtq 1024(%edx){1to2
2493 vpcmpgtq -1024(%edx){1to2}, %xmm6, %k5{%k7} # AVX512{F,VL} Disp8
2494 vpcmpgtq -1032(%edx){1to2}, %xmm6, %k5{%k7} # AVX512{F,VL}
2511 vpcmpq $123, (%eax){1to2}, %xmm6, %k5{%k7} # AVX512{F,VL}
2516 vpcmpq $123, 1016(%edx){1to2}, %xmm6, %k5{%k7} # AVX512{F,VL} Disp8
2517 vpcmpq $123, 1024(%edx){1to2}, %xmm6, %k5{%k7} # AVX512{F,VL}
2518 vpcmpq $123, -1024(%edx){1to2}, %xmm6, %k5{%k7} # AVX512{F,VL} Disp8
2519 vpcmpq $123, -1032(%edx){1to2}, %xmm6, %k5{%k7} # AVX512{F,VL}
2563 vpcmpuq $123, (%eax){1to2}, %xmm6, %k5{%k7} # AVX512{F,VL}
2568 vpcmpuq $123, 1016(%edx){1to2}, %xmm6, %k5{%k7} # AVX512{F,VL} Disp8
2569 vpcmpuq $123, 1024(%edx){1to2}, %xmm6, %k5{%k7} # AVX512{F,VL}
2570 vpcmpuq $123, -1024(%edx){1to2}, %xmm6, %k5{%k7} # AVX512{F,VL} Disp8
2571 vpcmpuq $123, -1032(%edx){1to2}, %xmm6, %k5{%k7} # AVX512{F,VL}
2589 vpblendmq (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
2594 vpblendmq 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
2595 vpblendmq 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
2596 vpblendmq -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
2597 vpblendmq -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
2645 vpermilpd $123, (%eax){1to2}, %xmm6{%k7} # AVX512{F,VL}
2650 vpermilpd $123, 1016(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL} Disp8
2651 vpermilpd $123, 1024(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL}
2652 vpermilpd $123, -1024(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL} Disp8
2653 vpermilpd $123, -1032(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL}
2672 vpermilpd (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
2677 vpermilpd 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
2678 vpermilpd 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
2679 vpermilpd -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
2680 vpermilpd -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
2879 vpmaxsq (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
2884 vpmaxsq 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
2885 vpmaxsq 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
2886 vpmaxsq -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
2887 vpmaxsq -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
2931 vpmaxuq (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
2936 vpmaxuq 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
2937 vpmaxuq 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
2938 vpmaxuq -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
2939 vpmaxuq -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
2983 vpminsq (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
2988 vpminsq 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
2989 vpminsq 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
2990 vpminsq -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
2991 vpminsq -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
3035 vpminuq (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
3040 vpminuq 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
3041 vpminuq 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
3042 vpminuq -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
3043 vpminuq -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
3221 vpmuldq (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
3226 vpmuldq 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
3227 vpmuldq 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
3228 vpmuldq -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
3229 vpmuldq -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
3273 vpmuludq (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
3278 vpmuludq 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
3279 vpmuludq 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
3280 vpmuludq -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
3281 vpmuludq -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
3325 vporq (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
3330 vporq 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
3331 vporq 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
3332 vporq -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
3333 vporq -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
3461 vpsllvq (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
3466 vpsllvq 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
3467 vpsllvq 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
3468 vpsllvq -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
3469 vpsllvq -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
3545 vpsravq (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
3550 vpsravq 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
3551 vpsravq 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
3552 vpsravq -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
3553 vpsravq -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
3629 vpsrlvq (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
3634 vpsrlvq 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
3635 vpsrlvq 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
3636 vpsrlvq -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
3637 vpsrlvq -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
3684 vpsrlq $123, (%eax){1to2}, %xmm6{%k7} # AVX512{F,VL}
3689 vpsrlq $123, 1016(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL} Disp8
3690 vpsrlq $123, 1024(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL}
3691 vpsrlq $123, -1024(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL} Disp8
3692 vpsrlq $123, -1032(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL}
3737 vpsubq (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
3742 vpsubq 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
3743 vpsubq 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
3744 vpsubq -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
3745 vpsubq -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
3786 vptestmq (%eax){1to2}, %xmm6, %k5{%k7} # AVX512{F,VL}
3791 vptestmq 1016(%edx){1to2}, %xmm6, %k5{%k7} # AVX512{F,VL} Disp8
3792 vptestmq 1024(%edx){1to2}, %xmm6, %k5{%k7} # AVX512{F,VL}
3793 vptestmq -1024(%edx){1to2}, %xmm6, %k5{%k7} # AVX512{F,VL} Disp8
3794 vptestmq -1032(%edx){1to2}, %xmm6, %k5{%k7} # AVX512{F,VL}
3837 vpunpckhqdq (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
3842 vpunpckhqdq 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
3843 vpunpckhqdq 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
3844 vpunpckhqdq -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
3845 vpunpckhqdq -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
3889 vpunpcklqdq (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
3894 vpunpcklqdq 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
3895 vpunpcklqdq 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
3896 vpunpcklqdq -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
3897 vpunpcklqdq -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
3941 vpxorq (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
3946 vpxorq 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
3947 vpxorq 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
3948 vpxorq -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
3949 vpxorq -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
3967 vrcp14pd (%eax){1to2}, %xmm6{%k7} # AVX512{F,VL}
3972 vrcp14pd 1016(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL} Disp8
3973 vrcp14pd 1024(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL}
3974 vrcp14pd -1024(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL} Disp8
3975 vrcp14pd -1032(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL}
4019 vrsqrt14pd (%eax){1to2}, %xmm6{%k7} # AVX512{F,VL}
4024 vrsqrt14pd 1016(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL} Disp8
4025 vrsqrt14pd 1024(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL}
4026 vrsqrt14pd -1024(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL} Disp8
4027 vrsqrt14pd -1032(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL}
4096 vshufpd $123, (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
4101 vshufpd $123, 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
4102 vshufpd $123, 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
4103 vshufpd $123, -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
4104 vshufpd $123, -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
4151 vsqrtpd (%eax){1to2}, %xmm6{%k7} # AVX512{F,VL}
4156 vsqrtpd 1016(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL} Disp8
4157 vsqrtpd 1024(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL}
4158 vsqrtpd -1024(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL} Disp8
4159 vsqrtpd -1032(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL}
4203 vsubpd (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
4208 vsubpd 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
4209 vsubpd 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
4210 vsubpd -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
4211 vsubpd -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
4255 vunpckhpd (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
4260 vunpckhpd 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
4261 vunpckhpd 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
4262 vunpckhpd -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
4263 vunpckhpd -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
4307 vunpcklpd (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
4312 vunpcklpd 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
4313 vunpcklpd 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
4314 vunpcklpd -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
4315 vunpcklpd -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
4388 vpternlogq $123, (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
4393 vpternlogq $123, 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
4394 vpternlogq $123, 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
4395 vpternlogq $123, -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
4396 vpternlogq $123, -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
4583 vpermt2q (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
4588 vpermt2q 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
4589 vpermt2q 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
4590 vpermt2q -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
4591 vpermt2q -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
4635 vpermt2pd (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
4640 vpermt2pd 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
4641 vpermt2pd 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
4642 vpermt2pd -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
4643 vpermt2pd -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
4662 valignq $123, (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
4667 valignq $123, 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
4668 valignq $123, 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
4669 valignq $123, -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
4670 valignq $123, -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
4689 vscalefpd (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
4694 vscalefpd 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
4695 vscalefpd 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
4696 vscalefpd -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
4697 vscalefpd -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
4742 vfixupimmpd $123, (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
4747 vfixupimmpd $123, 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
4748 vfixupimmpd $123, 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
4749 vfixupimmpd $123, -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
4750 vfixupimmpd $123, -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
4826 vpsllq $123, (%eax){1to2}, %xmm6{%k7} # AVX512{F,VL}
4831 vpsllq $123, 1016(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL} Disp8
4832 vpsllq $123, 1024(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL}
4833 vpsllq $123, -1024(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL} Disp8
4834 vpsllq $123, -1032(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL}
4882 vpsraq $123, (%eax){1to2}, %xmm6{%k7} # AVX512{F,VL}
4887 vpsraq $123, 1016(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL} Disp8
4888 vpsraq $123, 1024(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL}
4889 vpsraq $123, -1024(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL} Disp8
4890 vpsraq $123, -1032(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL}
4963 vprolvq (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
4968 vprolvq 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
4969 vprolvq 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
4970 vprolvq -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
4971 vprolvq -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
4990 vprolq $123, (%eax){1to2}, %xmm6{%k7} # AVX512{F,VL}
4995 vprolq $123, 1016(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL} Disp8
4996 vprolq $123, 1024(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL}
4997 vprolq $123, -1024(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL} Disp8
4998 vprolq $123, -1032(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL}
5071 vprorvq (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
5076 vprorvq 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
5077 vprorvq 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
5078 vprorvq -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
5079 vprorvq -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
5098 vprorq $123, (%eax){1to2}, %xmm6{%k7} # AVX512{F,VL}
5103 vprorq $123, 1016(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL} Disp8
5104 vprorq $123, 1024(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL}
5105 vprorq $123, -1024(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL} Disp8
5106 vprorq $123, -1032(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL}
5126 vrndscalepd $123, (%eax){1to2}, %xmm6{%k7} # AVX512{F,VL}
5131 vrndscalepd $123, 1016(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL} Disp8
5132 vrndscalepd $123, 1024(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL}
5133 vrndscalepd $123, -1024(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL} Disp8
5134 vrndscalepd $123, -1032(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL}
5501 vcvttpd2udq (%eax){1to2}, %xmm6{%k7} # AVX512{F,VL}
5506 vcvttpd2udqx 1016(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL} Disp8
5507 vcvttpd2udqx 1024(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL}
5508 vcvttpd2udqx -1024(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL} Disp8
5509 vcvttpd2udqx -1032(%edx){1to2}, %xmm6{%k7} # AVX512{F,VL}
5579 vpermi2q (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
5584 vpermi2q 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
5585 vpermi2q 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
5586 vpermi2q -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
5587 vpermi2q -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
5631 vpermi2pd (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
5636 vpermi2pd 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
5637 vpermi2pd 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
5638 vpermi2pd -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL} Disp8
5639 vpermi2pd -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{F,VL}
5680 vptestnmq (%eax){1to2}, %xmm5, %k5{%k7} # AVX512{F,VL}
5685 vptestnmq 1016(%edx){1to2}, %xmm5, %k5{%k7} # AVX512{F,VL} Disp8
5686 vptestnmq 1024(%edx){1to2}, %xmm5, %k5{%k7} # AVX512{F,VL}
5687 vptestnmq -1024(%edx){1to2}, %xmm5, %k5{%k7} # AVX512{F,VL} Disp8
5688 vptestnmq -1032(%edx){1to2}, %xmm5, %k5{%k7} # AVX512{F,VL}
5707 vaddpd xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
5712 vaddpd xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
5713 vaddpd xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
5714 vaddpd xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
5715 vaddpd xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
5787 vblendmpd xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
5792 vblendmpd xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
5793 vblendmpd xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
5794 vblendmpd xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
5795 vblendmpd xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
5880 vcmppd k5{k7}, xmm5, [eax]{1to2}, 123 # AVX512{F,VL}
5885 vcmppd k5{k7}, xmm5, [edx+1016]{1to2}, 123 # AVX512{F,VL} Disp8
5886 vcmppd k5{k7}, xmm5, [edx+1024]{1to2}, 123 # AVX512{F,VL}
5887 vcmppd k5{k7}, xmm5, [edx-1024]{1to2}, 123 # AVX512{F,VL} Disp8
5888 vcmppd k5{k7}, xmm5, [edx-1032]{1to2}, 123 # AVX512{F,VL}
5964 vcvtdq2pd xmm6{k7}, [eax]{1to2} # AVX512{F,VL}
5969 vcvtdq2pd xmm6{k7}, [edx+508]{1to2} # AVX512{F,VL} Disp8
5970 vcvtdq2pd xmm6{k7}, [edx+512]{1to2} # AVX512{F,VL}
5971 vcvtdq2pd xmm6{k7}, [edx-512]{1to2} # AVX512{F,VL} Disp8
5972 vcvtdq2pd xmm6{k7}, [edx-516]{1to2} # AVX512{F,VL}
6016 vcvtpd2dq xmm6{k7}, [eax]{1to2} # AVX512{F,VL}
6021 vcvtpd2dq xmm6{k7}, QWORD PTR [edx+1016]{1to2} # AVX512{F,VL} Disp8
6022 vcvtpd2dq xmm6{k7}, QWORD PTR [edx+1024]{1to2} # AVX512{F,VL}
6023 vcvtpd2dq xmm6{k7}, QWORD PTR [edx-1024]{1to2} # AVX512{F,VL} Disp8
6024 vcvtpd2dq xmm6{k7}, QWORD PTR [edx-1032]{1to2} # AVX512{F,VL}
6042 vcvtpd2ps xmm6{k7}, [eax]{1to2} # AVX512{F,VL}
6047 vcvtpd2ps xmm6{k7}, QWORD PTR [edx+1016]{1to2} # AVX512{F,VL} Disp8
6048 vcvtpd2ps xmm6{k7}, QWORD PTR [edx+1024]{1to2} # AVX512{F,VL}
6049 vcvtpd2ps xmm6{k7}, QWORD PTR [edx-1024]{1to2} # AVX512{F,VL} Disp8
6050 vcvtpd2ps xmm6{k7}, QWORD PTR [edx-1032]{1to2} # AVX512{F,VL}
6068 vcvtpd2udq xmm6{k7}, [eax]{1to2} # AVX512{F,VL}
6073 vcvtpd2udq xmm6{k7}, QWORD PTR [edx+1016]{1to2} # AVX512{F,VL} Disp8
6074 vcvtpd2udq xmm6{k7}, QWORD PTR [edx+1024]{1to2} # AVX512{F,VL}
6075 vcvtpd2udq xmm6{k7}, QWORD PTR [edx-1024]{1to2} # AVX512{F,VL} Disp8
6076 vcvtpd2udq xmm6{k7}, QWORD PTR [edx-1032]{1to2} # AVX512{F,VL}
6136 vcvtps2pd xmm6{k7}, [eax]{1to2} # AVX512{F,VL}
6141 vcvtps2pd xmm6{k7}, [edx+508]{1to2} # AVX512{F,VL} Disp8
6142 vcvtps2pd xmm6{k7}, [edx+512]{1to2} # AVX512{F,VL}
6143 vcvtps2pd xmm6{k7}, [edx-512]{1to2} # AVX512{F,VL} Disp8
6144 vcvtps2pd xmm6{k7}, [edx-516]{1to2} # AVX512{F,VL}
6194 vcvttpd2dq xmm6{k7}, [eax]{1to2} # AVX512{F,VL}
6199 vcvttpd2dq xmm6{k7}, QWORD PTR [edx+1016]{1to2} # AVX512{F,VL} Disp8
6200 vcvttpd2dq xmm6{k7}, QWORD PTR [edx+1024]{1to2} # AVX512{F,VL}
6201 vcvttpd2dq xmm6{k7}, QWORD PTR [edx-1024]{1to2} # AVX512{F,VL} Disp8
6202 vcvttpd2dq xmm6{k7}, QWORD PTR [edx-1032]{1to2} # AVX512{F,VL}
6246 vcvtudq2pd xmm6{k7}, [eax]{1to2} # AVX512{F,VL}
6251 vcvtudq2pd xmm6{k7}, [edx+508]{1to2} # AVX512{F,VL} Disp8
6252 vcvtudq2pd xmm6{k7}, [edx+512]{1to2} # AVX512{F,VL}
6253 vcvtudq2pd xmm6{k7}, [edx-512]{1to2} # AVX512{F,VL} Disp8
6254 vcvtudq2pd xmm6{k7}, [edx-516]{1to2} # AVX512{F,VL}
6298 vdivpd xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
6303 vdivpd xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
6304 vdivpd xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
6305 vdivpd xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
6306 vdivpd xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
6392 vfmadd132pd xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
6397 vfmadd132pd xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
6398 vfmadd132pd xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
6399 vfmadd132pd xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
6400 vfmadd132pd xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
6444 vfmadd213pd xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
6449 vfmadd213pd xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
6450 vfmadd213pd xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
6451 vfmadd213pd xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
6452 vfmadd213pd xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
6496 vfmadd231pd xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
6501 vfmadd231pd xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
6502 vfmadd231pd xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
6503 vfmadd231pd xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
6504 vfmadd231pd xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
6548 vfmaddsub132pd xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
6553 vfmaddsub132pd xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
6554 vfmaddsub132pd xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
6555 vfmaddsub132pd xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
6556 vfmaddsub132pd xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
6600 vfmaddsub213pd xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
6605 vfmaddsub213pd xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
6606 vfmaddsub213pd xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
6607 vfmaddsub213pd xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
6608 vfmaddsub213pd xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
6652 vfmaddsub231pd xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
6657 vfmaddsub231pd xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
6658 vfmaddsub231pd xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
6659 vfmaddsub231pd xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
6660 vfmaddsub231pd xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
6704 vfmsub132pd xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
6709 vfmsub132pd xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
6710 vfmsub132pd xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
6711 vfmsub132pd xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
6712 vfmsub132pd xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
6756 vfmsub213pd xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
6761 vfmsub213pd xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
6762 vfmsub213pd xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
6763 vfmsub213pd xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
6764 vfmsub213pd xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
6808 vfmsub231pd xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
6813 vfmsub231pd xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
6814 vfmsub231pd xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
6815 vfmsub231pd xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
6816 vfmsub231pd xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
6860 vfmsubadd132pd xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
6865 vfmsubadd132pd xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
6866 vfmsubadd132pd xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
6867 vfmsubadd132pd xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
6868 vfmsubadd132pd xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
6912 vfmsubadd213pd xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
6917 vfmsubadd213pd xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
6918 vfmsubadd213pd xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
6919 vfmsubadd213pd xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
6920 vfmsubadd213pd xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
6964 vfmsubadd231pd xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
6969 vfmsubadd231pd xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
6970 vfmsubadd231pd xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
6971 vfmsubadd231pd xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
6972 vfmsubadd231pd xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
7016 vfnmadd132pd xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
7021 vfnmadd132pd xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
7022 vfnmadd132pd xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
7023 vfnmadd132pd xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
7024 vfnmadd132pd xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
7068 vfnmadd213pd xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
7073 vfnmadd213pd xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
7074 vfnmadd213pd xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
7075 vfnmadd213pd xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
7076 vfnmadd213pd xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
7120 vfnmadd231pd xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
7125 vfnmadd231pd xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
7126 vfnmadd231pd xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
7127 vfnmadd231pd xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
7128 vfnmadd231pd xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
7172 vfnmsub132pd xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
7177 vfnmsub132pd xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
7178 vfnmsub132pd xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
7179 vfnmsub132pd xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
7180 vfnmsub132pd xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
7224 vfnmsub213pd xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
7229 vfnmsub213pd xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
7230 vfnmsub213pd xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
7231 vfnmsub213pd xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
7232 vfnmsub213pd xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
7276 vfnmsub231pd xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
7281 vfnmsub231pd xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
7282 vfnmsub231pd xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
7283 vfnmsub231pd xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
7284 vfnmsub231pd xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
7352 vgetexppd xmm6{k7}, [eax]{1to2} # AVX512{F,VL}
7357 vgetexppd xmm6{k7}, [edx+1016]{1to2} # AVX512{F,VL} Disp8
7358 vgetexppd xmm6{k7}, [edx+1024]{1to2} # AVX512{F,VL}
7359 vgetexppd xmm6{k7}, [edx-1024]{1to2} # AVX512{F,VL} Disp8
7360 vgetexppd xmm6{k7}, [edx-1032]{1to2} # AVX512{F,VL}
7405 vgetmantpd xmm6{k7}, [eax]{1to2}, 123 # AVX512{F,VL}
7410 vgetmantpd xmm6{k7}, [edx+1016]{1to2}, 123 # AVX512{F,VL} Disp8
7411 vgetmantpd xmm6{k7}, [edx+1024]{1to2}, 123 # AVX512{F,VL}
7412 vgetmantpd xmm6{k7}, [edx-1024]{1to2}, 123 # AVX512{F,VL} Disp8
7413 vgetmantpd xmm6{k7}, [edx-1032]{1to2}, 123 # AVX512{F,VL}
7478 vmaxpd xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
7483 vmaxpd xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
7484 vmaxpd xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
7485 vmaxpd xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
7486 vmaxpd xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
7530 vminpd xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
7535 vminpd xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
7536 vminpd xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
7537 vminpd xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
7538 vminpd xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
7758 vmulpd xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
7763 vmulpd xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
7764 vmulpd xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
7765 vmulpd xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
7766 vmulpd xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
7836 vpabsq xmm6{k7}, [eax]{1to2} # AVX512{F,VL}
7841 vpabsq xmm6{k7}, [edx+1016]{1to2} # AVX512{F,VL} Disp8
7842 vpabsq xmm6{k7}, [edx+1024]{1to2} # AVX512{F,VL}
7843 vpabsq xmm6{k7}, [edx-1024]{1to2} # AVX512{F,VL} Disp8
7844 vpabsq xmm6{k7}, [edx-1032]{1to2} # AVX512{F,VL}
7888 vpaddq xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
7893 vpaddq xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
7894 vpaddq xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
7895 vpaddq xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
7896 vpaddq xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
7966 vpandnq xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
7971 vpandnq xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
7972 vpandnq xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
7973 vpandnq xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
7974 vpandnq xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
7992 vpandq xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
7997 vpandq xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
7998 vpandq xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
7999 vpandq xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
8000 vpandq xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
8135 vpcmpeqq k5{k7}, xmm6, [eax]{1to2} # AVX512{F,VL}
8140 vpcmpeqq k5{k7}, xmm6, [edx+1016]{1to2} # AVX512{F,VL} Disp8
8141 vpcmpeqq k5{k7}, xmm6, [edx+1024]{1to2} # AVX512{F,VL}
8142 vpcmpeqq k5{k7}, xmm6, [edx-1024]{1to2} # AVX512{F,VL} Disp8
8143 vpcmpeqq k5{k7}, xmm6, [edx-1032]{1to2} # AVX512{F,VL}
8183 vpcmpgtq k5{k7}, xmm6, [eax]{1to2} # AVX512{F,VL}
8188 vpcmpgtq k5{k7}, xmm6, [edx+1016]{1to2} # AVX512{F,VL} Disp8
8189 vpcmpgtq k5{k7}, xmm6, [edx+1024]{1to2} # AVX512{F,VL}
8190 vpcmpgtq k5{k7}, xmm6, [edx-1024]{1to2} # AVX512{F,VL} Disp8
8191 vpcmpgtq k5{k7}, xmm6, [edx-1032]{1to2} # AVX512{F,VL}
8208 vpcmpq k5{k7}, xmm6, [eax]{1to2}, 123 # AVX512{F,VL}
8213 vpcmpq k5{k7}, xmm6, [edx+1016]{1to2}, 123 # AVX512{F,VL} Disp8
8214 vpcmpq k5{k7}, xmm6, [edx+1024]{1to2}, 123 # AVX512{F,VL}
8215 vpcmpq k5{k7}, xmm6, [edx-1024]{1to2}, 123 # AVX512{F,VL} Disp8
8216 vpcmpq k5{k7}, xmm6, [edx-1032]{1to2}, 123 # AVX512{F,VL}
8260 vpcmpuq k5{k7}, xmm6, [eax]{1to2}, 123 # AVX512{F,VL}
8265 vpcmpuq k5{k7}, xmm6, [edx+1016]{1to2}, 123 # AVX512{F,VL} Disp8
8266 vpcmpuq k5{k7}, xmm6, [edx+1024]{1to2}, 123 # AVX512{F,VL}
8267 vpcmpuq k5{k7}, xmm6, [edx-1024]{1to2}, 123 # AVX512{F,VL} Disp8
8268 vpcmpuq k5{k7}, xmm6, [edx-1032]{1to2}, 123 # AVX512{F,VL}
8286 vpblendmq xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
8291 vpblendmq xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
8292 vpblendmq xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
8293 vpblendmq xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
8294 vpblendmq xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
8342 vpermilpd xmm6{k7}, [eax]{1to2}, 123 # AVX512{F,VL}
8347 vpermilpd xmm6{k7}, [edx+1016]{1to2}, 123 # AVX512{F,VL} Disp8
8348 vpermilpd xmm6{k7}, [edx+1024]{1to2}, 123 # AVX512{F,VL}
8349 vpermilpd xmm6{k7}, [edx-1024]{1to2}, 123 # AVX512{F,VL} Disp8
8350 vpermilpd xmm6{k7}, [edx-1032]{1to2}, 123 # AVX512{F,VL}
8369 vpermilpd xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
8374 vpermilpd xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
8375 vpermilpd xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
8376 vpermilpd xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
8377 vpermilpd xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
8576 vpmaxsq xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
8581 vpmaxsq xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
8582 vpmaxsq xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
8583 vpmaxsq xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
8584 vpmaxsq xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
8628 vpmaxuq xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
8633 vpmaxuq xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
8634 vpmaxuq xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
8635 vpmaxuq xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
8636 vpmaxuq xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
8680 vpminsq xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
8685 vpminsq xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
8686 vpminsq xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
8687 vpminsq xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
8688 vpminsq xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
8732 vpminuq xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
8737 vpminuq xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
8738 vpminuq xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
8739 vpminuq xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
8740 vpminuq xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
8918 vpmuldq xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
8923 vpmuldq xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
8924 vpmuldq xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
8925 vpmuldq xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
8926 vpmuldq xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
8970 vpmuludq xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
8975 vpmuludq xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
8976 vpmuludq xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
8977 vpmuludq xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
8978 vpmuludq xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
9022 vporq xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
9027 vporq xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
9028 vporq xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
9029 vporq xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
9030 vporq xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
9158 vpsllvq xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
9163 vpsllvq xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
9164 vpsllvq xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
9165 vpsllvq xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
9166 vpsllvq xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
9242 vpsravq xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
9247 vpsravq xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
9248 vpsravq xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
9249 vpsravq xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
9250 vpsravq xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
9326 vpsrlvq xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
9331 vpsrlvq xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
9332 vpsrlvq xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
9333 vpsrlvq xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
9334 vpsrlvq xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
9381 vpsrlq xmm6{k7}, [eax]{1to2}, 123 # AVX512{F,VL}
9386 vpsrlq xmm6{k7}, [edx+1016]{1to2}, 123 # AVX512{F,VL} Disp8
9387 vpsrlq xmm6{k7}, [edx+1024]{1to2}, 123 # AVX512{F,VL}
9388 vpsrlq xmm6{k7}, [edx-1024]{1to2}, 123 # AVX512{F,VL} Disp8
9389 vpsrlq xmm6{k7}, [edx-1032]{1to2}, 123 # AVX512{F,VL}
9434 vpsubq xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
9439 vpsubq xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
9440 vpsubq xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
9441 vpsubq xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
9442 vpsubq xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
9483 vptestmq k5{k7}, xmm6, [eax]{1to2} # AVX512{F,VL}
9488 vptestmq k5{k7}, xmm6, [edx+1016]{1to2} # AVX512{F,VL} Disp8
9489 vptestmq k5{k7}, xmm6, [edx+1024]{1to2} # AVX512{F,VL}
9490 vptestmq k5{k7}, xmm6, [edx-1024]{1to2} # AVX512{F,VL} Disp8
9491 vptestmq k5{k7}, xmm6, [edx-1032]{1to2} # AVX512{F,VL}
9534 vpunpckhqdq xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
9539 vpunpckhqdq xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
9540 vpunpckhqdq xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
9541 vpunpckhqdq xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
9542 vpunpckhqdq xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
9586 vpunpcklqdq xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
9591 vpunpcklqdq xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
9592 vpunpcklqdq xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
9593 vpunpcklqdq xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
9594 vpunpcklqdq xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
9638 vpxorq xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
9643 vpxorq xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
9644 vpxorq xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
9645 vpxorq xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
9646 vpxorq xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
9664 vrcp14pd xmm6{k7}, [eax]{1to2} # AVX512{F,VL}
9669 vrcp14pd xmm6{k7}, [edx+1016]{1to2} # AVX512{F,VL} Disp8
9670 vrcp14pd xmm6{k7}, [edx+1024]{1to2} # AVX512{F,VL}
9671 vrcp14pd xmm6{k7}, [edx-1024]{1to2} # AVX512{F,VL} Disp8
9672 vrcp14pd xmm6{k7}, [edx-1032]{1to2} # AVX512{F,VL}
9716 vrsqrt14pd xmm6{k7}, [eax]{1to2} # AVX512{F,VL}
9721 vrsqrt14pd xmm6{k7}, [edx+1016]{1to2} # AVX512{F,VL} Disp8
9722 vrsqrt14pd xmm6{k7}, [edx+1024]{1to2} # AVX512{F,VL}
9723 vrsqrt14pd xmm6{k7}, [edx-1024]{1to2} # AVX512{F,VL} Disp8
9724 vrsqrt14pd xmm6{k7}, [edx-1032]{1to2} # AVX512{F,VL}
9793 vshufpd xmm6{k7}, xmm5, [eax]{1to2}, 123 # AVX512{F,VL}
9798 vshufpd xmm6{k7}, xmm5, [edx+1016]{1to2}, 123 # AVX512{F,VL} Disp8
9799 vshufpd xmm6{k7}, xmm5, [edx+1024]{1to2}, 123 # AVX512{F,VL}
9800 vshufpd xmm6{k7}, xmm5, [edx-1024]{1to2}, 123 # AVX512{F,VL} Disp8
9801 vshufpd xmm6{k7}, xmm5, [edx-1032]{1to2}, 123 # AVX512{F,VL}
9848 vsqrtpd xmm6{k7}, [eax]{1to2} # AVX512{F,VL}
9853 vsqrtpd xmm6{k7}, [edx+1016]{1to2} # AVX512{F,VL} Disp8
9854 vsqrtpd xmm6{k7}, [edx+1024]{1to2} # AVX512{F,VL}
9855 vsqrtpd xmm6{k7}, [edx-1024]{1to2} # AVX512{F,VL} Disp8
9856 vsqrtpd xmm6{k7}, [edx-1032]{1to2} # AVX512{F,VL}
9900 vsubpd xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
9905 vsubpd xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
9906 vsubpd xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
9907 vsubpd xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
9908 vsubpd xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
9952 vunpckhpd xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
9957 vunpckhpd xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
9958 vunpckhpd xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
9959 vunpckhpd xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
9960 vunpckhpd xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
10004 vunpcklpd xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
10009 vunpcklpd xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
10010 vunpcklpd xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
10011 vunpcklpd xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
10012 vunpcklpd xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
10085 vpternlogq xmm6{k7}, xmm5, [eax]{1to2}, 123 # AVX512{F,VL}
10090 vpternlogq xmm6{k7}, xmm5, [edx+1016]{1to2}, 123 # AVX512{F,VL} Disp8
10091 vpternlogq xmm6{k7}, xmm5, [edx+1024]{1to2}, 123 # AVX512{F,VL}
10092 vpternlogq xmm6{k7}, xmm5, [edx-1024]{1to2}, 123 # AVX512{F,VL} Disp8
10093 vpternlogq xmm6{k7}, xmm5, [edx-1032]{1to2}, 123 # AVX512{F,VL}
10280 vpermt2q xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
10285 vpermt2q xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
10286 vpermt2q xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
10287 vpermt2q xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
10288 vpermt2q xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
10332 vpermt2pd xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
10337 vpermt2pd xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
10338 vpermt2pd xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
10339 vpermt2pd xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
10340 vpermt2pd xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
10359 valignq xmm6{k7}, xmm5, [eax]{1to2}, 123 # AVX512{F,VL}
10364 valignq xmm6{k7}, xmm5, [edx+1016]{1to2}, 123 # AVX512{F,VL} Disp8
10365 valignq xmm6{k7}, xmm5, [edx+1024]{1to2}, 123 # AVX512{F,VL}
10366 valignq xmm6{k7}, xmm5, [edx-1024]{1to2}, 123 # AVX512{F,VL} Disp8
10367 valignq xmm6{k7}, xmm5, [edx-1032]{1to2}, 123 # AVX512{F,VL}
10386 vscalefpd xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
10391 vscalefpd xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
10392 vscalefpd xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
10393 vscalefpd xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
10394 vscalefpd xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
10439 vfixupimmpd xmm6{k7}, xmm5, [eax]{1to2}, 123 # AVX512{F,VL}
10444 vfixupimmpd xmm6{k7}, xmm5, [edx+1016]{1to2}, 123 # AVX512{F,VL} Disp8
10445 vfixupimmpd xmm6{k7}, xmm5, [edx+1024]{1to2}, 123 # AVX512{F,VL}
10446 vfixupimmpd xmm6{k7}, xmm5, [edx-1024]{1to2}, 123 # AVX512{F,VL} Disp8
10447 vfixupimmpd xmm6{k7}, xmm5, [edx-1032]{1to2}, 123 # AVX512{F,VL}
10523 vpsllq xmm6{k7}, [eax]{1to2}, 123 # AVX512{F,VL}
10528 vpsllq xmm6{k7}, [edx+1016]{1to2}, 123 # AVX512{F,VL} Disp8
10529 vpsllq xmm6{k7}, [edx+1024]{1to2}, 123 # AVX512{F,VL}
10530 vpsllq xmm6{k7}, [edx-1024]{1to2}, 123 # AVX512{F,VL} Disp8
10531 vpsllq xmm6{k7}, [edx-1032]{1to2}, 123 # AVX512{F,VL}
10579 vpsraq xmm6{k7}, [eax]{1to2}, 123 # AVX512{F,VL}
10584 vpsraq xmm6{k7}, [edx+1016]{1to2}, 123 # AVX512{F,VL} Disp8
10585 vpsraq xmm6{k7}, [edx+1024]{1to2}, 123 # AVX512{F,VL}
10586 vpsraq xmm6{k7}, [edx-1024]{1to2}, 123 # AVX512{F,VL} Disp8
10587 vpsraq xmm6{k7}, [edx-1032]{1to2}, 123 # AVX512{F,VL}
10660 vprolvq xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
10665 vprolvq xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
10666 vprolvq xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
10667 vprolvq xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
10668 vprolvq xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
10687 vprolq xmm6{k7}, [eax]{1to2}, 123 # AVX512{F,VL}
10692 vprolq xmm6{k7}, [edx+1016]{1to2}, 123 # AVX512{F,VL} Disp8
10693 vprolq xmm6{k7}, [edx+1024]{1to2}, 123 # AVX512{F,VL}
10694 vprolq xmm6{k7}, [edx-1024]{1to2}, 123 # AVX512{F,VL} Disp8
10695 vprolq xmm6{k7}, [edx-1032]{1to2}, 123 # AVX512{F,VL}
10768 vprorvq xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
10773 vprorvq xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
10774 vprorvq xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
10775 vprorvq xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
10776 vprorvq xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
10795 vprorq xmm6{k7}, [eax]{1to2}, 123 # AVX512{F,VL}
10800 vprorq xmm6{k7}, [edx+1016]{1to2}, 123 # AVX512{F,VL} Disp8
10801 vprorq xmm6{k7}, [edx+1024]{1to2}, 123 # AVX512{F,VL}
10802 vprorq xmm6{k7}, [edx-1024]{1to2}, 123 # AVX512{F,VL} Disp8
10803 vprorq xmm6{k7}, [edx-1032]{1to2}, 123 # AVX512{F,VL}
10823 vrndscalepd xmm6{k7}, [eax]{1to2}, 123 # AVX512{F,VL}
10828 vrndscalepd xmm6{k7}, [edx+1016]{1to2}, 123 # AVX512{F,VL} Disp8
10829 vrndscalepd xmm6{k7}, [edx+1024]{1to2}, 123 # AVX512{F,VL}
10830 vrndscalepd xmm6{k7}, [edx-1024]{1to2}, 123 # AVX512{F,VL} Disp8
10831 vrndscalepd xmm6{k7}, [edx-1032]{1to2}, 123 # AVX512{F,VL}
11198 vcvttpd2udq xmm6{k7}, [eax]{1to2} # AVX512{F,VL}
11203 vcvttpd2udq xmm6{k7}, QWORD PTR [edx+1016]{1to2} # AVX512{F,VL} Disp8
11204 vcvttpd2udq xmm6{k7}, QWORD PTR [edx+1024]{1to2} # AVX512{F,VL}
11205 vcvttpd2udq xmm6{k7}, QWORD PTR [edx-1024]{1to2} # AVX512{F,VL} Disp8
11206 vcvttpd2udq xmm6{k7}, QWORD PTR [edx-1032]{1to2} # AVX512{F,VL}
11276 vpermi2q xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
11281 vpermi2q xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
11282 vpermi2q xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
11283 vpermi2q xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
11284 vpermi2q xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
11328 vpermi2pd xmm6{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
11333 vpermi2pd xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
11334 vpermi2pd xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
11335 vpermi2pd xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
11336 vpermi2pd xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
11377 vptestnmq k5{k7}, xmm5, [eax]{1to2} # AVX512{F,VL}
11382 vptestnmq k5{k7}, xmm5, [edx+1016]{1to2} # AVX512{F,VL} Disp8
11383 vptestnmq k5{k7}, xmm5, [edx+1024]{1to2} # AVX512{F,VL}
11384 vptestnmq k5{k7}, xmm5, [edx-1024]{1to2} # AVX512{F,VL} Disp8
11385 vptestnmq k5{k7}, xmm5, [edx-1032]{1to2} # AVX512{F,VL}
