Lines Matching refs:to2
36 vcvtpd2qq (%rcx){1to2}, %xmm30 # AVX512{DQ,VL}
41 vcvtpd2qq 1016(%rdx){1to2}, %xmm30 # AVX512{DQ,VL} Disp8
42 vcvtpd2qq 1024(%rdx){1to2}, %xmm30 # AVX512{DQ,VL}
43 vcvtpd2qq -1024(%rdx){1to2}, %xmm30 # AVX512{DQ,VL} Disp8
44 vcvtpd2qq -1032(%rdx){1to2}, %xmm30 # AVX512{DQ,VL}
64 vcvtpd2uqq (%rcx){1to2}, %xmm30 # AVX512{DQ,VL}
69 vcvtpd2uqq 1016(%rdx){1to2}, %xmm30 # AVX512{DQ,VL} Disp8
70 vcvtpd2uqq 1024(%rdx){1to2}, %xmm30 # AVX512{DQ,VL}
71 vcvtpd2uqq -1024(%rdx){1to2}, %xmm30 # AVX512{DQ,VL} Disp8
72 vcvtpd2uqq -1032(%rdx){1to2}, %xmm30 # AVX512{DQ,VL}
92 vcvtps2qq (%rcx){1to2}, %xmm30 # AVX512{DQ,VL}
97 vcvtps2qq 508(%rdx){1to2}, %xmm30 # AVX512{DQ,VL} Disp8
98 vcvtps2qq 512(%rdx){1to2}, %xmm30 # AVX512{DQ,VL}
99 vcvtps2qq -512(%rdx){1to2}, %xmm30 # AVX512{DQ,VL} Disp8
100 vcvtps2qq -516(%rdx){1to2}, %xmm30 # AVX512{DQ,VL}
120 vcvtps2uqq (%rcx){1to2}, %xmm30 # AVX512{DQ,VL}
125 vcvtps2uqq 508(%rdx){1to2}, %xmm30 # AVX512{DQ,VL} Disp8
126 vcvtps2uqq 512(%rdx){1to2}, %xmm30 # AVX512{DQ,VL}
127 vcvtps2uqq -512(%rdx){1to2}, %xmm30 # AVX512{DQ,VL} Disp8
128 vcvtps2uqq -516(%rdx){1to2}, %xmm30 # AVX512{DQ,VL}
148 vcvtqq2pd (%rcx){1to2}, %xmm30 # AVX512{DQ,VL}
153 vcvtqq2pd 1016(%rdx){1to2}, %xmm30 # AVX512{DQ,VL} Disp8
154 vcvtqq2pd 1024(%rdx){1to2}, %xmm30 # AVX512{DQ,VL}
155 vcvtqq2pd -1024(%rdx){1to2}, %xmm30 # AVX512{DQ,VL} Disp8
156 vcvtqq2pd -1032(%rdx){1to2}, %xmm30 # AVX512{DQ,VL}
176 vcvtqq2ps (%rcx){1to2}, %xmm30 # AVX512{DQ,VL}
181 vcvtqq2psx 1016(%rdx){1to2}, %xmm30 # AVX512{DQ,VL} Disp8
182 vcvtqq2psx 1024(%rdx){1to2}, %xmm30 # AVX512{DQ,VL}
183 vcvtqq2psx -1024(%rdx){1to2}, %xmm30 # AVX512{DQ,VL} Disp8
184 vcvtqq2psx -1032(%rdx){1to2}, %xmm30 # AVX512{DQ,VL}
204 vcvtuqq2pd (%rcx){1to2}, %xmm30 # AVX512{DQ,VL}
209 vcvtuqq2pd 1016(%rdx){1to2}, %xmm30 # AVX512{DQ,VL} Disp8
210 vcvtuqq2pd 1024(%rdx){1to2}, %xmm30 # AVX512{DQ,VL}
211 vcvtuqq2pd -1024(%rdx){1to2}, %xmm30 # AVX512{DQ,VL} Disp8
212 vcvtuqq2pd -1032(%rdx){1to2}, %xmm30 # AVX512{DQ,VL}
232 vcvtuqq2ps (%rcx){1to2}, %xmm30 # AVX512{DQ,VL}
237 vcvtuqq2psx 1016(%rdx){1to2}, %xmm30 # AVX512{DQ,VL} Disp8
238 vcvtuqq2psx 1024(%rdx){1to2}, %xmm30 # AVX512{DQ,VL}
239 vcvtuqq2psx -1024(%rdx){1to2}, %xmm30 # AVX512{DQ,VL} Disp8
240 vcvtuqq2psx -1032(%rdx){1to2}, %xmm30 # AVX512{DQ,VL}
268 vfpclasspd $123, (%rcx){1to2}, %k5 # AVX512{DQ,VL}
273 vfpclasspdx $123, 1016(%rdx){1to2}, %k5 # AVX512{DQ,VL} Disp8
274 vfpclasspdx $123, 1024(%rdx){1to2}, %k5 # AVX512{DQ,VL}
275 vfpclasspdx $123, -1024(%rdx){1to2}, %k5 # AVX512{DQ,VL} Disp8
276 vfpclasspdx $123, -1032(%rdx){1to2}, %k5 # AVX512{DQ,VL}
362 vpmullq (%rcx){1to2}, %xmm29, %xmm30 # AVX512{DQ,VL}
367 vpmullq 1016(%rdx){1to2}, %xmm29, %xmm30 # AVX512{DQ,VL} Disp8
368 vpmullq 1024(%rdx){1to2}, %xmm29, %xmm30 # AVX512{DQ,VL}
369 vpmullq -1024(%rdx){1to2}, %xmm29, %xmm30 # AVX512{DQ,VL} Disp8
370 vpmullq -1032(%rdx){1to2}, %xmm29, %xmm30 # AVX512{DQ,VL}
391 vrangepd $123, (%rcx){1to2}, %xmm29, %xmm30 # AVX512{DQ,VL}
396 vrangepd $123, 1016(%rdx){1to2}, %xmm29, %xmm30 # AVX512{DQ,VL} Disp8
397 vrangepd $123, 1024(%rdx){1to2}, %xmm29, %xmm30 # AVX512{DQ,VL}
398 vrangepd $123, -1024(%rdx){1to2}, %xmm29, %xmm30 # AVX512{DQ,VL} Disp8
399 vrangepd $123, -1032(%rdx){1to2}, %xmm29, %xmm30 # AVX512{DQ,VL}
450 vandpd (%rcx){1to2}, %xmm29, %xmm30 # AVX512{DQ,VL}
455 vandpd 1016(%rdx){1to2}, %xmm29, %xmm30 # AVX512{DQ,VL} Disp8
456 vandpd 1024(%rdx){1to2}, %xmm29, %xmm30 # AVX512{DQ,VL}
457 vandpd -1024(%rdx){1to2}, %xmm29, %xmm30 # AVX512{DQ,VL} Disp8
458 vandpd -1032(%rdx){1to2}, %xmm29, %xmm30 # AVX512{DQ,VL}
506 vandnpd (%rcx){1to2}, %xmm29, %xmm30 # AVX512{DQ,VL}
511 vandnpd 1016(%rdx){1to2}, %xmm29, %xmm30 # AVX512{DQ,VL} Disp8
512 vandnpd 1024(%rdx){1to2}, %xmm29, %xmm30 # AVX512{DQ,VL}
513 vandnpd -1024(%rdx){1to2}, %xmm29, %xmm30 # AVX512{DQ,VL} Disp8
514 vandnpd -1032(%rdx){1to2}, %xmm29, %xmm30 # AVX512{DQ,VL}
562 vorpd (%rcx){1to2}, %xmm29, %xmm30 # AVX512{DQ,VL}
567 vorpd 1016(%rdx){1to2}, %xmm29, %xmm30 # AVX512{DQ,VL} Disp8
568 vorpd 1024(%rdx){1to2}, %xmm29, %xmm30 # AVX512{DQ,VL}
569 vorpd -1024(%rdx){1to2}, %xmm29, %xmm30 # AVX512{DQ,VL} Disp8
570 vorpd -1032(%rdx){1to2}, %xmm29, %xmm30 # AVX512{DQ,VL}
618 vxorpd (%rcx){1to2}, %xmm29, %xmm30 # AVX512{DQ,VL}
623 vxorpd 1016(%rdx){1to2}, %xmm29, %xmm30 # AVX512{DQ,VL} Disp8
624 vxorpd 1024(%rdx){1to2}, %xmm29, %xmm30 # AVX512{DQ,VL}
625 vxorpd -1024(%rdx){1to2}, %xmm29, %xmm30 # AVX512{DQ,VL} Disp8
626 vxorpd -1032(%rdx){1to2}, %xmm29, %xmm30 # AVX512{DQ,VL}
675 vreducepd $123, (%rcx){1to2}, %xmm30 # AVX512{DQ,VL}
680 vreducepd $123, 1016(%rdx){1to2}, %xmm30 # AVX512{DQ,VL} Disp8
681 vreducepd $123, 1024(%rdx){1to2}, %xmm30 # AVX512{DQ,VL}
682 vreducepd $123, -1024(%rdx){1to2}, %xmm30 # AVX512{DQ,VL} Disp8
683 vreducepd $123, -1032(%rdx){1to2}, %xmm30 # AVX512{DQ,VL}
750 vcvttpd2qq (%rcx){1to2}, %xmm30 # AVX512{DQ,VL}
755 vcvttpd2qq 1016(%rdx){1to2}, %xmm30 # AVX512{DQ,VL} Disp8
756 vcvttpd2qq 1024(%rdx){1to2}, %xmm30 # AVX512{DQ,VL}
757 vcvttpd2qq -1024(%rdx){1to2}, %xmm30 # AVX512{DQ,VL} Disp8
758 vcvttpd2qq -1032(%rdx){1to2}, %xmm30 # AVX512{DQ,VL}
778 vcvttpd2uqq (%rcx){1to2}, %xmm30 # AVX512{DQ,VL}
783 vcvttpd2uqq 1016(%rdx){1to2}, %xmm30 # AVX512{DQ,VL} Disp8
784 vcvttpd2uqq 1024(%rdx){1to2}, %xmm30 # AVX512{DQ,VL}
785 vcvttpd2uqq -1024(%rdx){1to2}, %xmm30 # AVX512{DQ,VL} Disp8
786 vcvttpd2uqq -1032(%rdx){1to2}, %xmm30 # AVX512{DQ,VL}
806 vcvttps2qq (%rcx){1to2}, %xmm30 # AVX512{DQ,VL}
811 vcvttps2qq 508(%rdx){1to2}, %xmm30 # AVX512{DQ,VL} Disp8
812 vcvttps2qq 512(%rdx){1to2}, %xmm30 # AVX512{DQ,VL}
813 vcvttps2qq -512(%rdx){1to2}, %xmm30 # AVX512{DQ,VL} Disp8
814 vcvttps2qq -516(%rdx){1to2}, %xmm30 # AVX512{DQ,VL}
834 vcvttps2uqq (%rcx){1to2}, %xmm30 # AVX512{DQ,VL}
839 vcvttps2uqq 508(%rdx){1to2}, %xmm30 # AVX512{DQ,VL} Disp8
840 vcvttps2uqq 512(%rdx){1to2}, %xmm30 # AVX512{DQ,VL}
841 vcvttps2uqq -512(%rdx){1to2}, %xmm30 # AVX512{DQ,VL} Disp8
842 vcvttps2uqq -516(%rdx){1to2}, %xmm30 # AVX512{DQ,VL}
897 vcvtpd2qq xmm30, [rcx]{1to2} # AVX512{DQ,VL}
902 vcvtpd2qq xmm30, [rdx+1016]{1to2} # AVX512{DQ,VL} Disp8
903 vcvtpd2qq xmm30, [rdx+1024]{1to2} # AVX512{DQ,VL}
904 vcvtpd2qq xmm30, [rdx-1024]{1to2} # AVX512{DQ,VL} Disp8
905 vcvtpd2qq xmm30, [rdx-1032]{1to2} # AVX512{DQ,VL}
925 vcvtpd2uqq xmm30, [rcx]{1to2} # AVX512{DQ,VL}
930 vcvtpd2uqq xmm30, [rdx+1016]{1to2} # AVX512{DQ,VL} Disp8
931 vcvtpd2uqq xmm30, [rdx+1024]{1to2} # AVX512{DQ,VL}
932 vcvtpd2uqq xmm30, [rdx-1024]{1to2} # AVX512{DQ,VL} Disp8
933 vcvtpd2uqq xmm30, [rdx-1032]{1to2} # AVX512{DQ,VL}
953 vcvtps2qq xmm30, [rcx]{1to2} # AVX512{DQ,VL}
958 vcvtps2qq xmm30, [rdx+508]{1to2} # AVX512{DQ,VL} Disp8
959 vcvtps2qq xmm30, [rdx+512]{1to2} # AVX512{DQ,VL}
960 vcvtps2qq xmm30, [rdx-512]{1to2} # AVX512{DQ,VL} Disp8
961 vcvtps2qq xmm30, [rdx-516]{1to2} # AVX512{DQ,VL}
962 vcvtps2qq xmm30, DWORD PTR [rdx+508]{1to2} # AVX512{DQ,VL} Disp8
983 vcvtps2uqq xmm30, [rcx]{1to2} # AVX512{DQ,VL}
988 vcvtps2uqq xmm30, [rdx+508]{1to2} # AVX512{DQ,VL} Disp8
989 vcvtps2uqq xmm30, [rdx+512]{1to2} # AVX512{DQ,VL}
990 vcvtps2uqq xmm30, [rdx-512]{1to2} # AVX512{DQ,VL} Disp8
991 vcvtps2uqq xmm30, [rdx-516]{1to2} # AVX512{DQ,VL}
992 vcvtps2uqq xmm30, DWORD PTR [rdx+508]{1to2} # AVX512{DQ,VL} Disp8
1013 vcvtqq2pd xmm30, [rcx]{1to2} # AVX512{DQ,VL}
1018 vcvtqq2pd xmm30, [rdx+1016]{1to2} # AVX512{DQ,VL} Disp8
1019 vcvtqq2pd xmm30, [rdx+1024]{1to2} # AVX512{DQ,VL}
1020 vcvtqq2pd xmm30, [rdx-1024]{1to2} # AVX512{DQ,VL} Disp8
1021 vcvtqq2pd xmm30, [rdx-1032]{1to2} # AVX512{DQ,VL}
1041 vcvtqq2ps xmm30, [rcx]{1to2} # AVX512{DQ,VL}
1046 vcvtqq2ps xmm30, QWORD PTR [rdx+1016]{1to2} # AVX512{DQ,VL} Disp8
1047 vcvtqq2ps xmm30, QWORD PTR [rdx+1024]{1to2} # AVX512{DQ,VL}
1048 vcvtqq2ps xmm30, QWORD PTR [rdx-1024]{1to2} # AVX512{DQ,VL} Disp8
1049 vcvtqq2ps xmm30, QWORD PTR [rdx-1032]{1to2} # AVX512{DQ,VL}
1069 vcvtuqq2pd xmm30, [rcx]{1to2} # AVX512{DQ,VL}
1074 vcvtuqq2pd xmm30, [rdx+1016]{1to2} # AVX512{DQ,VL} Disp8
1075 vcvtuqq2pd xmm30, [rdx+1024]{1to2} # AVX512{DQ,VL}
1076 vcvtuqq2pd xmm30, [rdx-1024]{1to2} # AVX512{DQ,VL} Disp8
1077 vcvtuqq2pd xmm30, [rdx-1032]{1to2} # AVX512{DQ,VL}
1097 vcvtuqq2ps xmm30, [rcx]{1to2} # AVX512{DQ,VL}
1102 vcvtuqq2ps xmm30, QWORD PTR [rdx+1016]{1to2} # AVX512{DQ,VL} Disp8
1103 vcvtuqq2ps xmm30, QWORD PTR [rdx+1024]{1to2} # AVX512{DQ,VL}
1104 vcvtuqq2ps xmm30, QWORD PTR [rdx-1024]{1to2} # AVX512{DQ,VL} Disp8
1105 vcvtuqq2ps xmm30, QWORD PTR [rdx-1032]{1to2} # AVX512{DQ,VL}
1133 vfpclasspd k5, [rcx]{1to2}, 123 # AVX512{DQ,VL}
1138 vfpclasspd k5, QWORD PTR [rdx+1016]{1to2}, 123 # AVX512{DQ,VL} Disp8
1139 vfpclasspd k5, QWORD PTR [rdx+1024]{1to2}, 123 # AVX512{DQ,VL}
1140 vfpclasspd k5, QWORD PTR [rdx-1024]{1to2}, 123 # AVX512{DQ,VL} Disp8
1141 vfpclasspd k5, QWORD PTR [rdx-1032]{1to2}, 123 # AVX512{DQ,VL}
1227 vpmullq xmm30, xmm29, [rcx]{1to2} # AVX512{DQ,VL}
1232 vpmullq xmm30, xmm29, [rdx+1016]{1to2} # AVX512{DQ,VL} Disp8
1233 vpmullq xmm30, xmm29, [rdx+1024]{1to2} # AVX512{DQ,VL}
1234 vpmullq xmm30, xmm29, [rdx-1024]{1to2} # AVX512{DQ,VL} Disp8
1235 vpmullq xmm30, xmm29, [rdx-1032]{1to2} # AVX512{DQ,VL}
1256 vrangepd xmm30, xmm29, [rcx]{1to2}, 123 # AVX512{DQ,VL}
1261 vrangepd xmm30, xmm29, [rdx+1016]{1to2}, 123 # AVX512{DQ,VL} Disp8
1262 vrangepd xmm30, xmm29, [rdx+1024]{1to2}, 123 # AVX512{DQ,VL}
1263 vrangepd xmm30, xmm29, [rdx-1024]{1to2}, 123 # AVX512{DQ,VL} Disp8
1264 vrangepd xmm30, xmm29, [rdx-1032]{1to2}, 123 # AVX512{DQ,VL}
1315 vandpd xmm30, xmm29, [rcx]{1to2} # AVX512{DQ,VL}
1320 vandpd xmm30, xmm29, [rdx+1016]{1to2} # AVX512{DQ,VL} Disp8
1321 vandpd xmm30, xmm29, [rdx+1024]{1to2} # AVX512{DQ,VL}
1322 vandpd xmm30, xmm29, [rdx-1024]{1to2} # AVX512{DQ,VL} Disp8
1323 vandpd xmm30, xmm29, [rdx-1032]{1to2} # AVX512{DQ,VL}
1371 vandnpd xmm30, xmm29, [rcx]{1to2} # AVX512{DQ,VL}
1376 vandnpd xmm30, xmm29, [rdx+1016]{1to2} # AVX512{DQ,VL} Disp8
1377 vandnpd xmm30, xmm29, [rdx+1024]{1to2} # AVX512{DQ,VL}
1378 vandnpd xmm30, xmm29, [rdx-1024]{1to2} # AVX512{DQ,VL} Disp8
1379 vandnpd xmm30, xmm29, [rdx-1032]{1to2} # AVX512{DQ,VL}
1427 vorpd xmm30, xmm29, [rcx]{1to2} # AVX512{DQ,VL}
1432 vorpd xmm30, xmm29, [rdx+1016]{1to2} # AVX512{DQ,VL} Disp8
1433 vorpd xmm30, xmm29, [rdx+1024]{1to2} # AVX512{DQ,VL}
1434 vorpd xmm30, xmm29, [rdx-1024]{1to2} # AVX512{DQ,VL} Disp8
1435 vorpd xmm30, xmm29, [rdx-1032]{1to2} # AVX512{DQ,VL}
1483 vxorpd xmm30, xmm29, [rcx]{1to2} # AVX512{DQ,VL}
1488 vxorpd xmm30, xmm29, [rdx+1016]{1to2} # AVX512{DQ,VL} Disp8
1489 vxorpd xmm30, xmm29, [rdx+1024]{1to2} # AVX512{DQ,VL}
1490 vxorpd xmm30, xmm29, [rdx-1024]{1to2} # AVX512{DQ,VL} Disp8
1491 vxorpd xmm30, xmm29, [rdx-1032]{1to2} # AVX512{DQ,VL}
1540 vreducepd xmm30, [rcx]{1to2}, 123 # AVX512{DQ,VL}
1545 vreducepd xmm30, [rdx+1016]{1to2}, 123 # AVX512{DQ,VL} Disp8
1546 vreducepd xmm30, [rdx+1024]{1to2}, 123 # AVX512{DQ,VL}
1547 vreducepd xmm30, [rdx-1024]{1to2}, 123 # AVX512{DQ,VL} Disp8
1548 vreducepd xmm30, [rdx-1032]{1to2}, 123 # AVX512{DQ,VL}
1615 vcvttpd2qq xmm30, [rcx]{1to2} # AVX512{DQ,VL}
1620 vcvttpd2qq xmm30, [rdx+1016]{1to2} # AVX512{DQ,VL} Disp8
1621 vcvttpd2qq xmm30, [rdx+1024]{1to2} # AVX512{DQ,VL}
1622 vcvttpd2qq xmm30, [rdx-1024]{1to2} # AVX512{DQ,VL} Disp8
1623 vcvttpd2qq xmm30, [rdx-1032]{1to2} # AVX512{DQ,VL}
1643 vcvttpd2uqq xmm30, [rcx]{1to2} # AVX512{DQ,VL}
1648 vcvttpd2uqq xmm30, [rdx+1016]{1to2} # AVX512{DQ,VL} Disp8
1649 vcvttpd2uqq xmm30, [rdx+1024]{1to2} # AVX512{DQ,VL}
1650 vcvttpd2uqq xmm30, [rdx-1024]{1to2} # AVX512{DQ,VL} Disp8
1651 vcvttpd2uqq xmm30, [rdx-1032]{1to2} # AVX512{DQ,VL}
1671 vcvttps2qq xmm30, [rcx]{1to2} # AVX512{DQ,VL}
1676 vcvttps2qq xmm30, [rdx+508]{1to2} # AVX512{DQ,VL} Disp8
1677 vcvttps2qq xmm30, [rdx+512]{1to2} # AVX512{DQ,VL}
1678 vcvttps2qq xmm30, [rdx-512]{1to2} # AVX512{DQ,VL} Disp8
1679 vcvttps2qq xmm30, [rdx-516]{1to2} # AVX512{DQ,VL}
1680 vcvttps2qq xmm30, DWORD PTR [rdx+508]{1to2} # AVX512{DQ,VL} Disp8
1701 vcvttps2uqq xmm30, [rcx]{1to2} # AVX512{DQ,VL}
1706 vcvttps2uqq xmm30, [rdx+508]{1to2} # AVX512{DQ,VL} Disp8
1707 vcvttps2uqq xmm30, [rdx+512]{1to2} # AVX512{DQ,VL}
1708 vcvttps2uqq xmm30, [rdx-512]{1to2} # AVX512{DQ,VL} Disp8
1709 vcvttps2uqq xmm30, [rdx-516]{1to2} # AVX512{DQ,VL}
1710 vcvttps2uqq xmm30, DWORD PTR [rdx+508]{1to2} # AVX512{DQ,VL} Disp8
