Lines Matching defs:REG
40 #define REG 3
50 /* Masks for the mode bits in REG format instructions */
55 /* Generate the 12-bit opcode for a REG format instruction by placing the
62 /* Generate a template for a REG format instruction: place the opcode bits
70 * The information is also useful to us because some 1-operand REG instructions
71 * use the src1 field, others the dst field; and some 2-operand REG instructions
131 /* TRUE if reg #n is properly aligned */
139 char format; /* REG, COBR, CTRL, MEMn, COJ, FBRA, or CALLJ */
284 { R_3(0x580), "notbit", I_BASE, REG, 3, { RSL,RSL,RS } },
285 { R_3(0x581), "and", I_BASE, REG, 3, { RSL,RSL,RS } },
286 { R_3(0x582), "andnot", I_BASE, REG, 3, { RSL,RSL,RS } },
287 { R_3(0x583), "setbit", I_BASE, REG, 3, { RSL,RSL,RS } },
288 { R_3(0x584), "notand", I_BASE, REG, 3, { RSL,RSL,RS } },
289 { R_3(0x586), "xor", I_BASE, REG, 3, { RSL,RSL,RS } },
290 { R_3(0x587), "or", I_BASE, REG, 3, { RSL,RSL,RS } },
291 { R_3(0x588), "nor", I_BASE, REG, 3, { RSL,RSL,RS } },
292 { R_3(0x589), "xnor", I_BASE, REG, 3, { RSL,RSL,RS } },
293 { R_2D(0x58a), "not", I_BASE, REG, 2, { RSL,RS, 0 } },
294 { R_3(0x58b), "ornot", I_BASE, REG, 3, { RSL,RSL,RS } },
295 { R_3(0x58c), "clrbit", I_BASE, REG, 3, { RSL,RSL,RS } },
296 { R_3(0x58d), "notor", I_BASE, REG, 3, { RSL,RSL,RS } },
297 { R_3(0x58e), "nand", I_BASE, REG, 3, { RSL,RSL,RS } },
298 { R_3(0x58f), "alterbit", I_BASE, REG, 3, { RSL,RSL,RS } },
299 { R_3(0x590), "addo", I_BASE, REG, 3, { RSL,RSL,RS } },
300 { R_3(0x591), "addi", I_BASE, REG, 3, { RSL,RSL,RS } },
301 { R_3(0x592), "subo", I_BASE, REG, 3, { RSL,RSL,RS } },
302 { R_3(0x593), "subi", I_BASE, REG, 3, { RSL,RSL,RS } },
303 { R_3(0x598), "shro", I_BASE, REG, 3, { RSL,RSL,RS } },
304 { R_3(0x59a), "shrdi", I_BASE, REG, 3, { RSL,RSL,RS } },
305 { R_3(0x59b), "shri", I_BASE, REG, 3, { RSL,RSL,RS } },
306 { R_3(0x59c), "shlo", I_BASE, REG, 3, { RSL,RSL,RS } },
307 { R_3(0x59d), "rotate", I_BASE, REG, 3, { RSL,RSL,RS } },
308 { R_3(0x59e), "shli", I_BASE, REG, 3, { RSL,RSL,RS } },
309 { R_2(0x5a0), "cmpo", I_BASE, REG, 2, { RSL,RSL, 0 } },
310 { R_2(0x5a1), "cmpi", I_BASE, REG, 2, { RSL,RSL, 0 } },
311 { R_2(0x5a2), "concmpo", I_BASE, REG, 2, { RSL,RSL, 0 } },
312 { R_2(0x5a3), "concmpi", I_BASE, REG, 2, { RSL,RSL, 0 } },
313 { R_3(0x5a4), "cmpinco", I_BASE, REG, 3, { RSL,RSL,RS } },
314 { R_3(0x5a5), "cmpinci", I_BASE, REG, 3, { RSL,RSL,RS } },
315 { R_3(0x5a6), "cmpdeco", I_BASE, REG, 3, { RSL,RSL,RS } },
316 { R_3(0x5a7), "cmpdeci", I_BASE, REG, 3, { RSL,RSL,RS } },
317 { R_2(0x5ac), "scanbyte", I_BASE, REG, 2, { RSL,RSL, 0 } },
318 { R_2(0x5ae), "chkbit", I_BASE, REG, 2, { RSL,RSL, 0 } },
319 { R_3(0x5b0), "addc", I_BASE, REG, 3, { RSL,RSL,RS } },
320 { R_3(0x5b2), "subc", I_BASE, REG, 3, { RSL,RSL,RS } },
321 { R_2D(0x5cc), "mov", I_BASE, REG, 2, { RSL,RS, 0 } },
322 { R_2D(0x5dc), "movl", I_BASE, REG, 2, { RL2,R2, 0 } },
323 { R_2D(0x5ec), "movt", I_BASE, REG, 2, { RL4,R4, 0 } },
324 { R_2D(0x5fc), "movq", I_BASE, REG, 2, { RL4,R4, 0 } },
325 { R_3(0x610), "atmod", I_BASE, REG, 3, { RS, RSL,R } },
326 { R_3(0x612), "atadd", I_BASE, REG, 3, { RS, RSL,RS } },
327 { R_2D(0x640), "spanbit", I_BASE, REG, 2, { RSL,RS, 0 } },
328 { R_2D(0x641), "scanbit", I_BASE, REG, 2, { RSL,RS, 0 } },
329 { R_3(0x645), "modac", I_BASE, REG, 3, { RSL,RSL,RS } },
330 { R_3(0x650), "modify", I_BASE, REG, 3, { RSL,RSL,R } },
331 { R_3(0x651), "extract", I_BASE, REG, 3, { RSL,RSL,R } },
332 { R_3(0x654), "modtc", I_BASE, REG, 3, { RSL,RSL,RS } },
333 { R_3(0x655), "modpc", I_BASE, REG, 3, { RSL,RSL,R } },
334 { R_1(0x660), "calls", I_BASE, REG, 1, { RSL, 0, 0 } },
335 { R_0(0x66b), "mark", I_BASE, REG, 0, { 0, 0, 0 } },
336 { R_0(0x66c), "fmark", I_BASE, REG, 0, { 0, 0, 0 } },
337 { R_0(0x66d), "flushreg", I_BASE, REG, 0, { 0, 0, 0 } },
338 { R_0(0x66f), "syncf", I_BASE, REG, 0, { 0, 0, 0 } },
339 { R_3(0x670), "emul", I_BASE, REG, 3, { RSL,RSL,R2 } },
340 { R_3(0x671), "ediv", I_BASE, REG, 3, { RSL,RL2,RS } },
341 { R_2D(0x672), "cvtadr", I_CASIM,REG, 2, { RL, R2, 0 } },
342 { R_3(0x701), "mulo", I_BASE, REG, 3, { RSL,RSL,RS } },
343 { R_3(0x708), "remo", I_BASE, REG, 3, { RSL,RSL,RS } },
344 { R_3(0x70b), "divo", I_BASE, REG, 3, { RSL,RSL,RS } },
345 { R_3(0x741), "muli", I_BASE, REG, 3, { RSL,RSL,RS } },
346 { R_3(0x748), "remi", I_BASE, REG, 3, { RSL,RSL,RS } },
347 { R_3(0x749), "modi", I_BASE, REG, 3, { RSL,RSL,RS } },
348 { R_3(0x74b), "divi", I_BASE, REG, 3, { RSL,RSL,RS } },
352 { R_2D(0x674), "cvtir", I_FP, REG, 2, { RL, F, 0 } },
353 REG, 2, { RL, F, 0 } },
354 { R_3(0x676), "scalerl", I_FP, REG, 3, { RL, FL2,F2 } },
355 { R_3(0x677), "scaler", I_FP, REG, 3, { RL, FL, F } },
356 { R_3(0x680), "atanr", I_FP, REG, 3, { FL, FL, F } },
357 { R_3(0x681), "logepr", I_FP, REG, 3, { FL, FL, F } },
358 { R_3(0x682), "logr", I_FP, REG, 3, { FL, FL, F } },
359 { R_3(0x683), "remr", I_FP, REG, 3, { FL, FL, F } },
360 { R_2(0x684), "cmpor", I_FP, REG, 2, { FL, FL, 0 } },
361 { R_2(0x685), "cmpr", I_FP, REG, 2, { FL, FL, 0 } },
362 { R_2D(0x688), "sqrtr", I_FP, REG, 2, { FL, F, 0 } },
363 { R_2D(0x689), "expr", I_FP, REG, 2, { FL, F, 0 } },
364 { R_2D(0x68a), "logbnr", I_FP, REG, 2, { FL, F, 0 } },
365 { R_2D(0x68b), "roundr", I_FP, REG, 2, { FL, F, 0 } },
366 { R_2D(0x68c), "sinr", I_FP, REG, 2, { FL, F, 0 } },
367 { R_2D(0x68d), "cosr", I_FP, REG, 2, { FL, F, 0 } },
368 { R_2D(0x68e), "tanr", I_FP, REG, 2, { FL, F, 0 } },
369 { R_1(0x68f), "classr", I_FP, REG, 1, { FL, 0, 0 } },
370 { R_3(0x690), "atanrl", I_FP, REG, 3, { FL2,FL2,F2 } },
371 { R_3(0x691), "logeprl", I_FP, REG, 3, { FL2,FL2,F2 } },
372 { R_3(0x692), "logrl", I_FP, REG, 3, { FL2,FL2,F2 } },
373 { R_3(0x693), "remrl", I_FP, REG, 3, { FL2,FL2,F2 } },
374 { R_2(0x694), "cmporl", I_FP, REG, 2, { FL2,FL2, 0 } },
375 { R_2(0x695), "cmprl", I_FP, REG, 2, { FL2,FL2, 0 } },
376 { R_2D(0x698), "sqrtrl", I_FP, REG, 2, { FL2,F2, 0 } },
377 { R_2D(0x699), "exprl", I_FP, REG, 2, { FL2,F2, 0 } },
378 { R_2D(0x69a), "logbnrl", I_FP, REG, 2, { FL2,F2, 0 } },
379 { R_2D(0x69b), "roundrl", I_FP, REG, 2, { FL2,F2, 0 } },
380 { R_2D(0x69c), "sinrl", I_FP, REG, 2, { FL2,F2, 0 } },
381 { R_2D(0x69d), "cosrl", I_FP, REG, 2, { FL2,F2, 0 } },
382 { R_2D(0x69e), "tanrl", I_FP, REG, 2, { FL2,F2, 0 } },
383 { R_1(0x69f), "classrl", I_FP, REG, 1, { FL2, 0, 0 } },
384 { R_2D(0x6c0), "cvtri", I_FP, REG, 2, { FL, R, 0 } },
385 { R_2D(0x6c1), "cvtril", I_FP, REG, 2, { FL, R2, 0 } },
386 { R_2D(0x6c2), "cvtzri", I_FP, REG, 2, { FL, R, 0 } },
387 { R_2D(0x6c3), "cvtzril", I_FP, REG, 2, { FL, R2, 0 } },
388 { R_2D(0x6c9), "movr", I_FP, REG, 2, { FL, F, 0 } },
389 { R_2D(0x6d9), "movrl", I_FP, REG, 2, { FL2,F2, 0 } },
390 { R_2D(0x6e1), "movre", I_FP, REG, 2, { FL4,F4, 0 } },
391 { R_3(0x6e2), "cpysre", I_FP, REG, 3, { FL4,FL4,F4 } },
392 { R_3(0x6e3), "cpyrsre", I_FP, REG, 3, { FL4,FL4,F4 } },
393 { R_3(0x78b), "divr", I_FP, REG, 3, { FL, FL, F } },
394 { R_3(0x78c), "mulr", I_FP, REG, 3, { FL, FL, F } },
395 { R_3(0x78d), "subr", I_FP, REG, 3, { FL, FL, F } },
396 { R_3(0x78f), "addr", I_FP, REG, 3, { FL, FL, F } },
397 { R_3(0x79b), "divrl", I_FP, REG, 3, { FL2,FL2,F2 } },
398 { R_3(0x79c), "mulrl", I_FP, REG, 3, { FL2,FL2,F2 } },
399 { R_3(0x79d), "subrl", I_FP, REG, 3, { FL2,FL2,F2 } },
400 { R_3(0x79f), "addrl", I_FP, REG, 3, { FL2,FL2,F2 } },
417 { R_3(0x642), "daddc", I_DEC, REG, 3, { RSL,RSL,RS } },
418 { R_3(0x643), "dsubc", I_DEC, REG, 3, { RSL,RSL,RS } },
419 { R_2D(0x644), "dmovt", I_DEC, REG, 2, { RSL,RS, 0 } },
424 { R_2(0x600), "synmov", I_KX, REG, 2, { R, R, 0 } },
425 { R_2(0x601), "synmovl", I_KX, REG, 2, { R, R, 0 } },
426 { R_2(0x602), "synmovq", I_KX, REG, 2, { R, R, 0 } },
427 { R_2D(0x615), "synld", I_KX, REG, 2, { R, R, 0 } },
432 { R_3(0x603), "cmpstr", I_MIL, REG, 3, { R, R, RL } },
433 { R_3(0x604), "movqstr", I_MIL, REG, 3, { R, R, RL } },
434 { R_3(0x605), "movstr", I_MIL, REG, 3, { R, R, RL } },
435 { R_2D(0x613), "inspacc", I_MIL, REG, 2, { R, R, 0 } },
436 { R_2D(0x614), "ldphy", I_MIL, REG, 2, { R, R, 0 } },
437 { R_3(0x617), "fill", I_MIL, REG, 3, { R, RL, RL } },
438 { R_2D(0x646), "condrec", I_MIL, REG, 2, { R, R, 0 } },
439 { R_2D(0x656), "receive", I_MIL, REG, 2, { R, R, 0 } },
440 { R_3(0x662), "send", I_MIL, REG, 3, { R, RL, R } },
441 { R_1(0x663), "sendserv", I_MIL, REG, 1, { R, 0, 0 } },
442 { R_1(0x664), "resumprcs", I_MIL, REG, 1, { R, 0, 0 } },
443 { R_1(0x665), "schedprcs", I_MIL, REG, 1, { R, 0, 0 } },
444 { R_0(0x666), "saveprcs", I_MIL, REG, 0, { 0, 0, 0 } },
445 { R_1(0x668), "condwait", I_MIL, REG, 1, { R, 0, 0 } },
446 { R_1(0x669), "wait", I_MIL, REG, 1, { R, 0, 0 } },
447 { R_1(0x66a), "signal", I_MIL, REG, 1, { R, 0, 0 } },
448 { R_1D(0x673), "ldtime", I_MIL, REG, 1, { R2, 0, 0 } },
453 { R_3(0x5d8), "eshro", I_CX2, REG, 3, { RSL,RSL,RS } },
454 { R_3(0x630), "sdma", I_CX, REG, 3, { RSL,RSL,RL } },
455 { R_3(0x631), "udma", I_CX, REG, 0, { 0, 0, 0 } },
456 { R_3(0x659), "sysctl", I_CX2, REG, 3, { RSL,RSL,RL } },
460 { R_3(0x780), "addono", I_JX, REG, 3, { RSL,RSL,RS } },
461 { R_3(0x790), "addog", I_JX, REG, 3, { RSL,RSL,RS } },
462 { R_3(0x7a0), "addoe", I_JX, REG, 3, { RSL,RSL,RS } },
463 { R_3(0x7b0), "addoge", I_JX, REG, 3, { RSL,RSL,RS } },
464 { R_3(0x7c0), "addol", I_JX, REG, 3, { RSL,RSL,RS } },
465 { R_3(0x7d0), "addone", I_JX, REG, 3, { RSL,RSL,RS } },
466 { R_3(0x7e0), "addole", I_JX, REG, 3, { RSL,RSL,RS } },
467 { R_3(0x7f0), "addoo", I_JX, REG, 3, { RSL,RSL,RS } },
468 { R_3(0x781), "addino", I_JX, REG, 3, { RSL,RSL,RS } },
469 { R_3(0x791), "addig", I_JX, REG, 3, { RSL,RSL,RS } },
470 { R_3(0x7a1), "addie", I_JX, REG, 3, { RSL,RSL,RS } },
471 { R_3(0x7b1), "addige", I_JX, REG, 3, { RSL,RSL,RS } },
472 { R_3(0x7c1), "addil", I_JX, REG, 3, { RSL,RSL,RS } },
473 { R_3(0x7d1), "addine", I_JX, REG, 3, { RSL,RSL,RS } },
474 { R_3(0x7e1), "addile", I_JX, REG, 3, { RSL,RSL,RS } },
475 { R_3(0x7f1), "addio", I_JX, REG, 3, { RSL,RSL,RS } },
477 { R_2D(0x5ad), "bswap", I_JX, REG, 2, { RSL, RS, 0 } },
479 { R_2(0x594), "cmpob", I_JX, REG, 2, { RSL,RSL, 0 } },
480 { R_2(0x595), "cmpib", I_JX, REG, 2, { RSL,RSL, 0 } },
481 { R_2(0x596), "cmpos", I_JX, REG, 2, { RSL,RSL, 0 } },
482 { R_2(0x597), "cmpis", I_JX, REG, 2, { RSL,RSL, 0 } },
484 { R_3(0x784), "selno", I_JX, REG, 3, { RSL,RSL,RS } },
485 { R_3(0x794), "selg", I_JX, REG, 3, { RSL,RSL,RS } },
486 { R_3(0x7a4), "sele", I_JX, REG, 3, { RSL,RSL,RS } },
487 { R_3(0x7b4), "selge", I_JX, REG, 3, { RSL,RSL,RS } },
488 { R_3(0x7c4), "sell", I_JX, REG, 3, { RSL,RSL,RS } },
489 { R_3(0x7d4), "selne", I_JX, REG, 3, { RSL,RSL,RS } },
490 { R_3(0x7e4), "selle", I_JX, REG, 3, { RSL,RSL,RS } },
491 { R_3(0x7f4), "selo", I_JX, REG, 3, { RSL,RSL,RS } },
493 { R_3(0x782), "subono", I_JX, REG, 3, { RSL,RSL,RS } },
494 { R_3(0x792), "subog", I_JX, REG, 3, { RSL,RSL,RS } },
495 { R_3(0x7a2), "suboe", I_JX, REG, 3, { RSL,RSL,RS } },
496 { R_3(0x7b2), "suboge", I_JX, REG, 3, { RSL,RSL,RS } },
497 { R_3(0x7c2), "subol", I_JX, REG, 3, { RSL,RSL,RS } },
498 { R_3(0x7d2), "subone", I_JX, REG, 3, { RSL,RSL,RS } },
499 { R_3(0x7e2), "subole", I_JX, REG, 3, { RSL,RSL,RS } },
500 { R_3(0x7f2), "suboo", I_JX, REG, 3, { RSL,RSL,RS } },
501 { R_3(0x783), "subino", I_JX, REG, 3, { RSL,RSL,RS } },
502 { R_3(0x793), "subig", I_JX, REG, 3, { RSL,RSL,RS } },
503 { R_3(0x7a3), "subie", I_JX, REG, 3, { RSL,RSL,RS } },
504 { R_3(0x7b3), "subige", I_JX, REG, 3, { RSL,RSL,RS } },
505 { R_3(0x7c3), "subil", I_JX, REG, 3, { RSL,RSL,RS } },
506 { R_3(0x7d3), "subine", I_JX, REG, 3, { RSL,RSL,RS } },
507 { R_3(0x7e3), "subile", I_JX, REG, 3, { RSL,RSL,RS } },
508 { R_3(0x7f3), "subio", I_JX, REG, 3, { RSL,RSL,RS } },
510 { R_3(0x65c), "dcctl", I_JX, REG, 3, { RSL,RSL,RL } },
511 { R_3(0x65b), "icctl", I_JX, REG, 3, { RSL,RSL,RS } },
512 { R_2D(0x658), "intctl", I_JX, REG, 2, { RSL, RS, 0 } },
513 { R_0(0x5b4), "intdis", I_JX, REG, 0, { 0, 0, 0 } },
514 { R_0(0x5b5), "inten", I_JX, REG, 0, { 0, 0, 0 } },
515 { R_0(0x65d), "halt", I_JX, REG, 1, { RSL, 0, 0 } },
