Lines Matching refs:code
28 these fields where the VALUE will be inserted into CODE. MASK can be zero or
38 insert_fields (aarch64_insn *code, aarch64_insn value, aarch64_insn mask, ...)
52 insert_field (kind, code, value, mask);
63 aarch64_insn *code,
66 insert_field (self->fields[0], code, info->reg.regno, 0);
75 aarch64_insn *code, const aarch64_inst *inst)
78 insert_field (self->fields[0], code, info->reglane.regno, inst->opcode->mask);
89 insert_field (FLD_imm4, code, value, 0);
101 insert_field (FLD_imm5, code, value, 0);
112 insert_fields (code, info->reglane.index, 0, 3, FLD_M, FLD_L, FLD_H);
116 insert_fields (code, info->reglane.index, 0, 2, FLD_L, FLD_H);
120 insert_field (FLD_H, code, info->reglane.index, 0);
132 aarch64_insn *code,
136 insert_field (self->fields[0], code, info->reglist.first_regno, 0);
138 insert_field (FLD_len, code, info->reglist.num_regs - 1, 0);
146 const aarch64_opnd_info *info, aarch64_insn *code,
154 insert_field (FLD_Rt, code, info->reglist.first_regno, 0);
180 insert_field (FLD_opcode, code, value, 0);
189 const aarch64_opnd_info *info, aarch64_insn *code,
198 insert_field (FLD_Rt, code, info->reglist.first_regno, 0);
205 insert_field (FLD_S, code, value, 0);
214 const aarch64_opnd_info *info, aarch64_insn *code,
224 insert_field (FLD_Rt, code, info->reglist.first_regno, 0);
251 insert_fields (code, QSsize, 0, 3, FLD_vldst_size, FLD_S, FLD_Q);
253 insert_field_2 (&field, code, opcodeh2, 0);
264 aarch64_insn *code, const aarch64_inst *inst)
283 insert_field (FLD_Q, code, Q, inst->opcode->mask);
308 insert_fields (code, imm, 0, 2, FLD_immb, FLD_immh);
317 aarch64_insn *code,
328 insert_field (self->fields[0], code, imm, 0);
331 insert_fields (code, imm, 0, 2, self->fields[1], self->fields[0]);
339 aarch64_insn *code, const aarch64_inst *inst)
342 aarch64_ins_imm (self, info, code, inst);
344 insert_field (FLD_hw, code, info->shifter.amount >> 4, 0);
353 aarch64_insn *code,
373 insert_fields (code, imm, 0, 2, FLD_defgh, FLD_abc);
401 insert_field_2 (&field, code, amount, 0);
410 aarch64_insn *code,
413 insert_field (self->fields[0], code, 64 - info->imm.value, 0);
421 aarch64_insn *code, const aarch64_inst *inst ATTRIBUTE_UNUSED)
425 insert_field (self->fields[0], code, value, 0);
427 insert_field (self->fields[1], code, info->imm.value, 0);
435 aarch64_insn *code, const aarch64_inst *inst ATTRIBUTE_UNUSED)
447 insert_fields (code, value, 0, 3, self->fields[2], self->fields[1],
456 aarch64_insn *code, const aarch64_inst *inst)
463 aarch64_ins_regno (self, info, code, inst);
477 insert_field (FLD_ldst_size, code, value, 0);
483 insert_fields (code, value, 0, 2, FLD_ldst_size, FLD_opc1);
492 const aarch64_opnd_info *info, aarch64_insn *code,
496 insert_field (FLD_Rn, code, info->addr.base_regno, 0);
504 const aarch64_opnd_info *info, aarch64_insn *code,
511 insert_field (FLD_Rn, code, info->addr.base_regno, 0);
513 insert_field (FLD_Rm, code, info->addr.offset.regno, 0);
517 insert_field (FLD_option, code, aarch64_get_operand_modifier_value (kind), 0);
528 insert_field (FLD_S, code, S, 0);
537 code,
543 insert_field (FLD_Rn, code, info->addr.base_regno, 0);
549 insert_field (self->fields[0], code, imm, 0);
559 insert_field (self->fields[1], code, 1, 0);
569 aarch64_insn *code,
575 insert_field (self->fields[0], code, info->addr.base_regno, 0);
577 insert_field (self->fields[1], code,info->addr.offset.imm >> shift, 0);
585 const aarch64_opnd_info *info, aarch64_insn *code,
589 insert_field (FLD_Rn, code, info->addr.base_regno, 0);
592 insert_field (FLD_Rm, code, info->addr.offset.regno, 0);
594 insert_field (FLD_Rm, code, 0x1f, 0);
601 const aarch64_opnd_info *info, aarch64_insn *code,
605 insert_field (FLD_cond, code, info->cond->value, 0);
612 const aarch64_opnd_info *info, aarch64_insn *code,
616 insert_fields (code, info->sysreg, inst->opcode->mask, 5,
624 const aarch64_opnd_info *info, aarch64_insn *code,
628 insert_fields (code, info->pstatefield, inst->opcode->mask, 2,
636 const aarch64_opnd_info *info, aarch64_insn *code,
640 insert_fields (code, info->sysins_op->value, inst->opcode->mask, 4,
649 const aarch64_opnd_info *info, aarch64_insn *code,
653 insert_field (FLD_CRm, code, info->barrier->value, 0);
662 const aarch64_opnd_info *info, aarch64_insn *code,
666 insert_field (FLD_Rt, code, info->prfop->value, 0);
675 const aarch64_opnd_info *info, aarch64_insn *code,
679 insert_fields (code, info->hint_option->value, 0, 2, FLD_op2, FLD_CRm);
687 const aarch64_opnd_info *info, aarch64_insn *code,
693 insert_field (FLD_Rm, code, info->reg.regno, 0);
699 insert_field (FLD_option, code, aarch64_get_operand_modifier_value (kind), 0);
701 insert_field (FLD_imm3, code, info->shifter.amount, 0);
710 const aarch64_opnd_info *info, aarch64_insn *code,
714 insert_field (FLD_Rm, code, info->reg.regno, 0);
716 insert_field (FLD_shift, code,
719 insert_field (FLD_imm6, code, info->shifter.amount, 0);
1248 /* Encode *INST_ORI of the opcode code OPCODE.
1249 Return the encoded result in *CODE and if QLF_SEQ is not NULL, return the
1254 const aarch64_inst *inst_ori, aarch64_insn *code,
1340 *code = inst->value;
