Cross Reference: /toolchain/binutils/binutils-2.27/opcodes/arc-tbl.h

Lines Matching refs:RC_S
95 { "abs_s", 0x00007811, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RC_S }, { 0 }},
302 { "add1_s", 0x00007814, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }},
365 { "add2_s", 0x00007815, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }},
428 { "add3_s", 0x00007816, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }},
575 { "add_s", 0x00006018, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA_S, RB_S, RC_S }, { 0 }},
587 { "add_s", 0x00006800, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RC_S, RB_S, UIMM3_13_S }, { 0 }},
719 { "and_s", 0x00007804, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }},
992 { "asl_s", 0x0000781B, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB_S, RC_S }, { 0 }},
995 { "asl_s", 0x00007818, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RB_S, RB_Sdup, RC_S }, { 0 }},
998 RC_S, RB_S, UIMM3_13_S }, { 0 }},
1358 { "asr_s", 0x0000781C, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB_S, RC_S }, { 0 }},
1361 { "asr_s", 0x0000781A, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RB_S, RB_Sdup, RC_S }, { 0 }},
1364 { "asr_s", 0x00006818, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RC_S, RB_S, UIMM3_13_S }, { 0 }},
1616 { "bic_s", 0x00007806, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }},
6231 { "extb_s", 0x0000780F, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RC_S }, { 0 }},
6252 { "exth_s", 0x00007810, 0x0000F81F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RC_S }, { 0 }},
6273 { "extw_s", 0x00007810, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB_S, RC_S }, { 0 }},
8166 { "ldb_s", 0x00006008, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RA_S, BRAKET, RB_S, RC_S, BRAKETdup }, { 0 }},
8169 { "ldb_s", 0x00008800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RC_S, BRAKET, RB_S, UIMM5_11_S, BRAKETdup }, { 0 }},
8220 { "ldh_s", 0x00006010, 0x0000F818, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RA_S, BRAKET, RB_S, RC_S, BRAKETdup }, { 0 }},
8223 { "ldh_s", 0x00009000, 0x0000F800, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { 0 }},
8226 { "ldh_s", 0x00009800, 0x0000F800, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { C_XHARD }},
8277 RC_S, BRAKETdup }, { 0 }},
8280 { "ldw_s", 0x00009000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, MEMORY, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { 0 }},
8283 { "ldw_s", 0x00009800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, MEMORY, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { C_XHARD }},
8289 { "ld_s", 0x00006000, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RA_S, BRAKET, RB_S, RC_S, BRAKETdup }, { 0 }},
8292 { "ld_s", 0x00004800, 0x0000F818, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, CD2, { RA_S, BRAKET, RB_S, RC_S, BRAKETdup }, { C_AS }},
8310 { "ld_s", 0x00008000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RC_S, BRAKET, RB_S, UIMM7_A32_11_S, BRAKETdup }, { 0 }},
8638 { "lsr_s", 0x0000781D, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB_S, RC_S }, { 0 }},
8641 { "lsr_s", 0x00007819, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RB_S, RB_Sdup, RC_S }, { 0 }},
11101 { "mpyuw_s", 0x0000780A, 0x0000F81F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { RB_S, RB_Sdup, RC_S }, { 0 }},
11584 { "mpyw_s", 0x00007809, 0x0000F81F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { RB_S, RB_Sdup, RC_S }, { 0 }},
11587 { "mpy_s", 0x0000780C, 0x0000F81F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RB_S, RB_Sdup, RC_S }, { 0 }},
11974 { "mul64_s", 0x0000780C, 0x0000F81F, ARC_OPCODE_ARC600, ARITH, NONE, { ZA_S, RB_S, RC_S }, { 0 }},
11977 { "mul64_s", 0x0000780C, 0x0000F81F, ARC_OPCODE_ARC600, ARITH, NONE, { RB_S, RC_S }, { 0 }},
12793 { "neg_s", 0x00007813, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RC_S }, { 0 }},
12892 { "not_s", 0x00007812, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB_S, RC_S }, { 0 }},
12955 { "or_s", 0x00007805, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }},
14557 { "sexb_s", 0x0000780D, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RC_S }, { 0 }},
14578 { "sexh_s", 0x0000780E, 0x0000F81F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RC_S }, { 0 }},
14599 { "sexw_s", 0x0000780E, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB_S, RC_S }, { 0 }},
14734 { "stb_s", 0x0000A800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RC_S, BRAKET, RB_S, UIMM5_11_S, BRAKETdup }, { 0 }},
14767 { "sth_s", 0x0000B000, 0x0000F800, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { 0 }},
14782 { "stw_s", 0x0000B000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, MEMORY, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { 0 }},
14788 { "st_s", 0x0000A000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RC_S, BRAKET, RB_S, UIMM7_A32_11_S, BRAKETdup }, { 0 }},
15157 { "sub_s", 0x00007802, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }},
15160 { "sub_s", 0x00004810, 0x0000F818, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, CD2, { RA_S, RB_S, RC_S }, { 0 }},
15163 { "sub_s", 0x00006808, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RC_S, RB_S, UIMM3_13_S }, { 0 }},
15289 { "tst_s", 0x0000780B, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB_S, RC_S }, { 0 }},
18184 { "xor_s", 0x00007807, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }},
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