1 #ifndef A2XX_XML 2 #define A2XX_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2016-04-26 17:56:44) 12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) 13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32907 bytes, from 2016-11-26 23:01:08) 14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2016-11-26 23:01:08) 15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 23277 bytes, from 2016-12-24 05:01:47) 16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2016-11-26 23:01:08) 17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110757 bytes, from 2016-12-26 17:51:07) 18 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 100594 bytes, from 2017-01-20 23:03:30) 19 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00) 20 21 Copyright (C) 2013-2016 by the following authors: 22 - Rob Clark <robdclark (at) gmail.com> (robclark) 23 - Ilia Mirkin <imirkin (at) alum.mit.edu> (imirkin) 24 25 Permission is hereby granted, free of charge, to any person obtaining 26 a copy of this software and associated documentation files (the 27 "Software"), to deal in the Software without restriction, including 28 without limitation the rights to use, copy, modify, merge, publish, 29 distribute, sublicense, and/or sell copies of the Software, and to 30 permit persons to whom the Software is furnished to do so, subject to 31 the following conditions: 32 33 The above copyright notice and this permission notice (including the 34 next paragraph) shall be included in all copies or substantial 35 portions of the Software. 36 37 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 38 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 39 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 40 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 41 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 42 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 43 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 44 */ 45 46 47 enum a2xx_rb_dither_type { 48 DITHER_PIXEL = 0, 49 DITHER_SUBPIXEL = 1, 50 }; 51 52 enum a2xx_colorformatx { 53 COLORX_4_4_4_4 = 0, 54 COLORX_1_5_5_5 = 1, 55 COLORX_5_6_5 = 2, 56 COLORX_8 = 3, 57 COLORX_8_8 = 4, 58 COLORX_8_8_8_8 = 5, 59 COLORX_S8_8_8_8 = 6, 60 COLORX_16_FLOAT = 7, 61 COLORX_16_16_FLOAT = 8, 62 COLORX_16_16_16_16_FLOAT = 9, 63 COLORX_32_FLOAT = 10, 64 COLORX_32_32_FLOAT = 11, 65 COLORX_32_32_32_32_FLOAT = 12, 66 COLORX_2_3_3 = 13, 67 COLORX_8_8_8 = 14, 68 }; 69 70 enum a2xx_sq_surfaceformat { 71 FMT_1_REVERSE = 0, 72 FMT_1 = 1, 73 FMT_8 = 2, 74 FMT_1_5_5_5 = 3, 75 FMT_5_6_5 = 4, 76 FMT_6_5_5 = 5, 77 FMT_8_8_8_8 = 6, 78 FMT_2_10_10_10 = 7, 79 FMT_8_A = 8, 80 FMT_8_B = 9, 81 FMT_8_8 = 10, 82 FMT_Cr_Y1_Cb_Y0 = 11, 83 FMT_Y1_Cr_Y0_Cb = 12, 84 FMT_5_5_5_1 = 13, 85 FMT_8_8_8_8_A = 14, 86 FMT_4_4_4_4 = 15, 87 FMT_10_11_11 = 16, 88 FMT_11_11_10 = 17, 89 FMT_DXT1 = 18, 90 FMT_DXT2_3 = 19, 91 FMT_DXT4_5 = 20, 92 FMT_24_8 = 22, 93 FMT_24_8_FLOAT = 23, 94 FMT_16 = 24, 95 FMT_16_16 = 25, 96 FMT_16_16_16_16 = 26, 97 FMT_16_EXPAND = 27, 98 FMT_16_16_EXPAND = 28, 99 FMT_16_16_16_16_EXPAND = 29, 100 FMT_16_FLOAT = 30, 101 FMT_16_16_FLOAT = 31, 102 FMT_16_16_16_16_FLOAT = 32, 103 FMT_32 = 33, 104 FMT_32_32 = 34, 105 FMT_32_32_32_32 = 35, 106 FMT_32_FLOAT = 36, 107 FMT_32_32_FLOAT = 37, 108 FMT_32_32_32_32_FLOAT = 38, 109 FMT_32_AS_8 = 39, 110 FMT_32_AS_8_8 = 40, 111 FMT_16_MPEG = 41, 112 FMT_16_16_MPEG = 42, 113 FMT_8_INTERLACED = 43, 114 FMT_32_AS_8_INTERLACED = 44, 115 FMT_32_AS_8_8_INTERLACED = 45, 116 FMT_16_INTERLACED = 46, 117 FMT_16_MPEG_INTERLACED = 47, 118 FMT_16_16_MPEG_INTERLACED = 48, 119 FMT_DXN = 49, 120 FMT_8_8_8_8_AS_16_16_16_16 = 50, 121 FMT_DXT1_AS_16_16_16_16 = 51, 122 FMT_DXT2_3_AS_16_16_16_16 = 52, 123 FMT_DXT4_5_AS_16_16_16_16 = 53, 124 FMT_2_10_10_10_AS_16_16_16_16 = 54, 125 FMT_10_11_11_AS_16_16_16_16 = 55, 126 FMT_11_11_10_AS_16_16_16_16 = 56, 127 FMT_32_32_32_FLOAT = 57, 128 FMT_DXT3A = 58, 129 FMT_DXT5A = 59, 130 FMT_CTX1 = 60, 131 FMT_DXT3A_AS_1_1_1_1 = 61, 132 }; 133 134 enum a2xx_sq_ps_vtx_mode { 135 POSITION_1_VECTOR = 0, 136 POSITION_2_VECTORS_UNUSED = 1, 137 POSITION_2_VECTORS_SPRITE = 2, 138 POSITION_2_VECTORS_EDGE = 3, 139 POSITION_2_VECTORS_KILL = 4, 140 POSITION_2_VECTORS_SPRITE_KILL = 5, 141 POSITION_2_VECTORS_EDGE_KILL = 6, 142 MULTIPASS = 7, 143 }; 144 145 enum a2xx_sq_sample_cntl { 146 CENTROIDS_ONLY = 0, 147 CENTERS_ONLY = 1, 148 CENTROIDS_AND_CENTERS = 2, 149 }; 150 151 enum a2xx_dx_clip_space { 152 DXCLIP_OPENGL = 0, 153 DXCLIP_DIRECTX = 1, 154 }; 155 156 enum a2xx_pa_su_sc_polymode { 157 POLY_DISABLED = 0, 158 POLY_DUALMODE = 1, 159 }; 160 161 enum a2xx_rb_edram_mode { 162 EDRAM_NOP = 0, 163 COLOR_DEPTH = 4, 164 DEPTH_ONLY = 5, 165 EDRAM_COPY = 6, 166 }; 167 168 enum a2xx_pa_sc_pattern_bit_order { 169 LITTLE = 0, 170 BIG = 1, 171 }; 172 173 enum a2xx_pa_sc_auto_reset_cntl { 174 NEVER = 0, 175 EACH_PRIMITIVE = 1, 176 EACH_PACKET = 2, 177 }; 178 179 enum a2xx_pa_pixcenter { 180 PIXCENTER_D3D = 0, 181 PIXCENTER_OGL = 1, 182 }; 183 184 enum a2xx_pa_roundmode { 185 TRUNCATE = 0, 186 ROUND = 1, 187 ROUNDTOEVEN = 2, 188 ROUNDTOODD = 3, 189 }; 190 191 enum a2xx_pa_quantmode { 192 ONE_SIXTEENTH = 0, 193 ONE_EIGTH = 1, 194 ONE_QUARTER = 2, 195 ONE_HALF = 3, 196 ONE = 4, 197 }; 198 199 enum a2xx_rb_copy_sample_select { 200 SAMPLE_0 = 0, 201 SAMPLE_1 = 1, 202 SAMPLE_2 = 2, 203 SAMPLE_3 = 3, 204 SAMPLE_01 = 4, 205 SAMPLE_23 = 5, 206 SAMPLE_0123 = 6, 207 }; 208 209 enum a2xx_rb_blend_opcode { 210 BLEND2_DST_PLUS_SRC = 0, 211 BLEND2_SRC_MINUS_DST = 1, 212 BLEND2_MIN_DST_SRC = 2, 213 BLEND2_MAX_DST_SRC = 3, 214 BLEND2_DST_MINUS_SRC = 4, 215 BLEND2_DST_PLUS_SRC_BIAS = 5, 216 }; 217 218 enum adreno_mmu_clnt_beh { 219 BEH_NEVR = 0, 220 BEH_TRAN_RNG = 1, 221 BEH_TRAN_FLT = 2, 222 }; 223 224 enum sq_tex_clamp { 225 SQ_TEX_WRAP = 0, 226 SQ_TEX_MIRROR = 1, 227 SQ_TEX_CLAMP_LAST_TEXEL = 2, 228 SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 3, 229 SQ_TEX_CLAMP_HALF_BORDER = 4, 230 SQ_TEX_MIRROR_ONCE_HALF_BORDER = 5, 231 SQ_TEX_CLAMP_BORDER = 6, 232 SQ_TEX_MIRROR_ONCE_BORDER = 7, 233 }; 234 235 enum sq_tex_swiz { 236 SQ_TEX_X = 0, 237 SQ_TEX_Y = 1, 238 SQ_TEX_Z = 2, 239 SQ_TEX_W = 3, 240 SQ_TEX_ZERO = 4, 241 SQ_TEX_ONE = 5, 242 }; 243 244 enum sq_tex_filter { 245 SQ_TEX_FILTER_POINT = 0, 246 SQ_TEX_FILTER_BILINEAR = 1, 247 SQ_TEX_FILTER_BICUBIC = 2, 248 }; 249 250 #define REG_A2XX_RBBM_PATCH_RELEASE 0x00000001 251 252 #define REG_A2XX_RBBM_CNTL 0x0000003b 253 254 #define REG_A2XX_RBBM_SOFT_RESET 0x0000003c 255 256 #define REG_A2XX_CP_PFP_UCODE_ADDR 0x000000c0 257 258 #define REG_A2XX_CP_PFP_UCODE_DATA 0x000000c1 259 260 #define REG_A2XX_MH_MMU_CONFIG 0x00000040 261 #define A2XX_MH_MMU_CONFIG_MMU_ENABLE 0x00000001 262 #define A2XX_MH_MMU_CONFIG_SPLIT_MODE_ENABLE 0x00000002 263 #define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK 0x00000030 264 #define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT 4 265 static inline uint32_t A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 266 { 267 return ((val) << A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK; 268 } 269 #define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK 0x000000c0 270 #define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT 6 271 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 272 { 273 return ((val) << A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK; 274 } 275 #define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK 0x00000300 276 #define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT 8 277 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 278 { 279 return ((val) << A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK; 280 } 281 #define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK 0x00000c00 282 #define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT 10 283 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 284 { 285 return ((val) << A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK; 286 } 287 #define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK 0x00003000 288 #define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT 12 289 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 290 { 291 return ((val) << A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK; 292 } 293 #define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK 0x0000c000 294 #define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT 14 295 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 296 { 297 return ((val) << A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK; 298 } 299 #define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK 0x00030000 300 #define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT 16 301 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 302 { 303 return ((val) << A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK; 304 } 305 #define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK 0x000c0000 306 #define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT 18 307 static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 308 { 309 return ((val) << A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK; 310 } 311 #define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK 0x00300000 312 #define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT 20 313 static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 314 { 315 return ((val) << A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK; 316 } 317 #define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK 0x00c00000 318 #define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT 22 319 static inline uint32_t A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 320 { 321 return ((val) << A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK; 322 } 323 #define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK 0x03000000 324 #define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT 24 325 static inline uint32_t A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 326 { 327 return ((val) << A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK; 328 } 329 330 #define REG_A2XX_MH_MMU_VA_RANGE 0x00000041 331 332 #define REG_A2XX_MH_MMU_PT_BASE 0x00000042 333 334 #define REG_A2XX_MH_MMU_PAGE_FAULT 0x00000043 335 336 #define REG_A2XX_MH_MMU_TRAN_ERROR 0x00000044 337 338 #define REG_A2XX_MH_MMU_INVALIDATE 0x00000045 339 340 #define REG_A2XX_MH_MMU_MPU_BASE 0x00000046 341 342 #define REG_A2XX_MH_MMU_MPU_END 0x00000047 343 344 #define REG_A2XX_NQWAIT_UNTIL 0x00000394 345 346 #define REG_A2XX_RBBM_PERFCOUNTER1_SELECT 0x00000395 347 348 #define REG_A2XX_RBBM_PERFCOUNTER1_LO 0x00000397 349 350 #define REG_A2XX_RBBM_PERFCOUNTER1_HI 0x00000398 351 352 #define REG_A2XX_RBBM_DEBUG 0x0000039b 353 354 #define REG_A2XX_RBBM_PM_OVERRIDE1 0x0000039c 355 356 #define REG_A2XX_RBBM_PM_OVERRIDE2 0x0000039d 357 358 #define REG_A2XX_RBBM_DEBUG_OUT 0x000003a0 359 360 #define REG_A2XX_RBBM_DEBUG_CNTL 0x000003a1 361 362 #define REG_A2XX_RBBM_READ_ERROR 0x000003b3 363 364 #define REG_A2XX_RBBM_INT_CNTL 0x000003b4 365 366 #define REG_A2XX_RBBM_INT_STATUS 0x000003b5 367 368 #define REG_A2XX_RBBM_INT_ACK 0x000003b6 369 370 #define REG_A2XX_MASTER_INT_SIGNAL 0x000003b7 371 372 #define REG_A2XX_RBBM_PERIPHID1 0x000003f9 373 374 #define REG_A2XX_RBBM_PERIPHID2 0x000003fa 375 376 #define REG_A2XX_CP_PERFMON_CNTL 0x00000444 377 378 #define REG_A2XX_CP_PERFCOUNTER_SELECT 0x00000445 379 380 #define REG_A2XX_CP_PERFCOUNTER_LO 0x00000446 381 382 #define REG_A2XX_CP_PERFCOUNTER_HI 0x00000447 383 384 #define REG_A2XX_RBBM_STATUS 0x000005d0 385 #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK 0x0000001f 386 #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT 0 387 static inline uint32_t A2XX_RBBM_STATUS_CMDFIFO_AVAIL(uint32_t val) 388 { 389 return ((val) << A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT) & A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK; 390 } 391 #define A2XX_RBBM_STATUS_TC_BUSY 0x00000020 392 #define A2XX_RBBM_STATUS_HIRQ_PENDING 0x00000100 393 #define A2XX_RBBM_STATUS_CPRQ_PENDING 0x00000200 394 #define A2XX_RBBM_STATUS_CFRQ_PENDING 0x00000400 395 #define A2XX_RBBM_STATUS_PFRQ_PENDING 0x00000800 396 #define A2XX_RBBM_STATUS_VGT_BUSY_NO_DMA 0x00001000 397 #define A2XX_RBBM_STATUS_RBBM_WU_BUSY 0x00004000 398 #define A2XX_RBBM_STATUS_CP_NRT_BUSY 0x00010000 399 #define A2XX_RBBM_STATUS_MH_BUSY 0x00040000 400 #define A2XX_RBBM_STATUS_MH_COHERENCY_BUSY 0x00080000 401 #define A2XX_RBBM_STATUS_SX_BUSY 0x00200000 402 #define A2XX_RBBM_STATUS_TPC_BUSY 0x00400000 403 #define A2XX_RBBM_STATUS_SC_CNTX_BUSY 0x01000000 404 #define A2XX_RBBM_STATUS_PA_BUSY 0x02000000 405 #define A2XX_RBBM_STATUS_VGT_BUSY 0x04000000 406 #define A2XX_RBBM_STATUS_SQ_CNTX17_BUSY 0x08000000 407 #define A2XX_RBBM_STATUS_SQ_CNTX0_BUSY 0x10000000 408 #define A2XX_RBBM_STATUS_RB_CNTX_BUSY 0x40000000 409 #define A2XX_RBBM_STATUS_GUI_ACTIVE 0x80000000 410 411 #define REG_A2XX_MH_ARBITER_CONFIG 0x00000a40 412 #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK 0x0000003f 413 #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT 0 414 static inline uint32_t A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT(uint32_t val) 415 { 416 return ((val) << A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK; 417 } 418 #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY 0x00000040 419 #define A2XX_MH_ARBITER_CONFIG_L1_ARB_ENABLE 0x00000080 420 #define A2XX_MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE 0x00000100 421 #define A2XX_MH_ARBITER_CONFIG_L2_ARB_CONTROL 0x00000200 422 #define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK 0x00001c00 423 #define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT 10 424 static inline uint32_t A2XX_MH_ARBITER_CONFIG_PAGE_SIZE(uint32_t val) 425 { 426 return ((val) << A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT) & A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK; 427 } 428 #define A2XX_MH_ARBITER_CONFIG_TC_REORDER_ENABLE 0x00002000 429 #define A2XX_MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE 0x00004000 430 #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE 0x00008000 431 #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK 0x003f0000 432 #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT 16 433 static inline uint32_t A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT(uint32_t val) 434 { 435 return ((val) << A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK; 436 } 437 #define A2XX_MH_ARBITER_CONFIG_CP_CLNT_ENABLE 0x00400000 438 #define A2XX_MH_ARBITER_CONFIG_VGT_CLNT_ENABLE 0x00800000 439 #define A2XX_MH_ARBITER_CONFIG_TC_CLNT_ENABLE 0x01000000 440 #define A2XX_MH_ARBITER_CONFIG_RB_CLNT_ENABLE 0x02000000 441 #define A2XX_MH_ARBITER_CONFIG_PA_CLNT_ENABLE 0x04000000 442 443 #define REG_A2XX_A220_VSC_BIN_SIZE 0x00000c01 444 #define A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f 445 #define A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT 0 446 static inline uint32_t A2XX_A220_VSC_BIN_SIZE_WIDTH(uint32_t val) 447 { 448 assert(!(val & 0x1f)); 449 return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT) & A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK; 450 } 451 #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0 452 #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT 5 453 static inline uint32_t A2XX_A220_VSC_BIN_SIZE_HEIGHT(uint32_t val) 454 { 455 assert(!(val & 0x1f)); 456 return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT) & A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK; 457 } 458 459 static inline uint32_t REG_A2XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; } 460 461 static inline uint32_t REG_A2XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; } 462 463 static inline uint32_t REG_A2XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; } 464 465 static inline uint32_t REG_A2XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; } 466 467 #define REG_A2XX_PC_DEBUG_CNTL 0x00000c38 468 469 #define REG_A2XX_PC_DEBUG_DATA 0x00000c39 470 471 #define REG_A2XX_PA_SC_VIZ_QUERY_STATUS 0x00000c44 472 473 #define REG_A2XX_GRAS_DEBUG_CNTL 0x00000c80 474 475 #define REG_A2XX_PA_SU_DEBUG_CNTL 0x00000c80 476 477 #define REG_A2XX_GRAS_DEBUG_DATA 0x00000c81 478 479 #define REG_A2XX_PA_SU_DEBUG_DATA 0x00000c81 480 481 #define REG_A2XX_PA_SU_FACE_DATA 0x00000c86 482 483 #define REG_A2XX_SQ_GPR_MANAGEMENT 0x00000d00 484 485 #define REG_A2XX_SQ_FLOW_CONTROL 0x00000d01 486 487 #define REG_A2XX_SQ_INST_STORE_MANAGMENT 0x00000d02 488 489 #define REG_A2XX_SQ_DEBUG_MISC 0x00000d05 490 491 #define REG_A2XX_SQ_INT_CNTL 0x00000d34 492 493 #define REG_A2XX_SQ_INT_STATUS 0x00000d35 494 495 #define REG_A2XX_SQ_INT_ACK 0x00000d36 496 497 #define REG_A2XX_SQ_DEBUG_INPUT_FSM 0x00000dae 498 499 #define REG_A2XX_SQ_DEBUG_CONST_MGR_FSM 0x00000daf 500 501 #define REG_A2XX_SQ_DEBUG_TP_FSM 0x00000db0 502 503 #define REG_A2XX_SQ_DEBUG_FSM_ALU_0 0x00000db1 504 505 #define REG_A2XX_SQ_DEBUG_FSM_ALU_1 0x00000db2 506 507 #define REG_A2XX_SQ_DEBUG_EXP_ALLOC 0x00000db3 508 509 #define REG_A2XX_SQ_DEBUG_PTR_BUFF 0x00000db4 510 511 #define REG_A2XX_SQ_DEBUG_GPR_VTX 0x00000db5 512 513 #define REG_A2XX_SQ_DEBUG_GPR_PIX 0x00000db6 514 515 #define REG_A2XX_SQ_DEBUG_TB_STATUS_SEL 0x00000db7 516 517 #define REG_A2XX_SQ_DEBUG_VTX_TB_0 0x00000db8 518 519 #define REG_A2XX_SQ_DEBUG_VTX_TB_1 0x00000db9 520 521 #define REG_A2XX_SQ_DEBUG_VTX_TB_STATUS_REG 0x00000dba 522 523 #define REG_A2XX_SQ_DEBUG_VTX_TB_STATE_MEM 0x00000dbb 524 525 #define REG_A2XX_SQ_DEBUG_PIX_TB_0 0x00000dbc 526 527 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_0 0x00000dbd 528 529 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_1 0x00000dbe 530 531 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_2 0x00000dbf 532 533 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_3 0x00000dc0 534 535 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATE_MEM 0x00000dc1 536 537 #define REG_A2XX_TC_CNTL_STATUS 0x00000e00 538 #define A2XX_TC_CNTL_STATUS_L2_INVALIDATE 0x00000001 539 540 #define REG_A2XX_TP0_CHICKEN 0x00000e1e 541 542 #define REG_A2XX_RB_BC_CONTROL 0x00000f01 543 #define A2XX_RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE 0x00000001 544 #define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK 0x00000006 545 #define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT 1 546 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT(uint32_t val) 547 { 548 return ((val) << A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK; 549 } 550 #define A2XX_RB_BC_CONTROL_DISABLE_EDRAM_CAM 0x00000008 551 #define A2XX_RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH 0x00000010 552 #define A2XX_RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP 0x00000020 553 #define A2XX_RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP 0x00000040 554 #define A2XX_RB_BC_CONTROL_ENABLE_AZ_THROTTLE 0x00000080 555 #define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK 0x00001f00 556 #define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT 8 557 static inline uint32_t A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT(uint32_t val) 558 { 559 return ((val) << A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT) & A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK; 560 } 561 #define A2XX_RB_BC_CONTROL_ENABLE_CRC_UPDATE 0x00004000 562 #define A2XX_RB_BC_CONTROL_CRC_MODE 0x00008000 563 #define A2XX_RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS 0x00010000 564 #define A2XX_RB_BC_CONTROL_DISABLE_ACCUM 0x00020000 565 #define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK 0x003c0000 566 #define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT 18 567 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK(uint32_t val) 568 { 569 return ((val) << A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK; 570 } 571 #define A2XX_RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE 0x00400000 572 #define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK 0x07800000 573 #define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT 23 574 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT(uint32_t val) 575 { 576 return ((val) << A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK; 577 } 578 #define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK 0x18000000 579 #define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT 27 580 static inline uint32_t A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT(uint32_t val) 581 { 582 return ((val) << A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK; 583 } 584 #define A2XX_RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE 0x20000000 585 #define A2XX_RB_BC_CONTROL_CRC_SYSTEM 0x40000000 586 #define A2XX_RB_BC_CONTROL_RESERVED6 0x80000000 587 588 #define REG_A2XX_RB_EDRAM_INFO 0x00000f02 589 590 #define REG_A2XX_RB_DEBUG_CNTL 0x00000f26 591 592 #define REG_A2XX_RB_DEBUG_DATA 0x00000f27 593 594 #define REG_A2XX_RB_SURFACE_INFO 0x00002000 595 596 #define REG_A2XX_RB_COLOR_INFO 0x00002001 597 #define A2XX_RB_COLOR_INFO_FORMAT__MASK 0x0000000f 598 #define A2XX_RB_COLOR_INFO_FORMAT__SHIFT 0 599 static inline uint32_t A2XX_RB_COLOR_INFO_FORMAT(enum a2xx_colorformatx val) 600 { 601 return ((val) << A2XX_RB_COLOR_INFO_FORMAT__SHIFT) & A2XX_RB_COLOR_INFO_FORMAT__MASK; 602 } 603 #define A2XX_RB_COLOR_INFO_ROUND_MODE__MASK 0x00000030 604 #define A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT 4 605 static inline uint32_t A2XX_RB_COLOR_INFO_ROUND_MODE(uint32_t val) 606 { 607 return ((val) << A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT) & A2XX_RB_COLOR_INFO_ROUND_MODE__MASK; 608 } 609 #define A2XX_RB_COLOR_INFO_LINEAR 0x00000040 610 #define A2XX_RB_COLOR_INFO_ENDIAN__MASK 0x00000180 611 #define A2XX_RB_COLOR_INFO_ENDIAN__SHIFT 7 612 static inline uint32_t A2XX_RB_COLOR_INFO_ENDIAN(uint32_t val) 613 { 614 return ((val) << A2XX_RB_COLOR_INFO_ENDIAN__SHIFT) & A2XX_RB_COLOR_INFO_ENDIAN__MASK; 615 } 616 #define A2XX_RB_COLOR_INFO_SWAP__MASK 0x00000600 617 #define A2XX_RB_COLOR_INFO_SWAP__SHIFT 9 618 static inline uint32_t A2XX_RB_COLOR_INFO_SWAP(uint32_t val) 619 { 620 return ((val) << A2XX_RB_COLOR_INFO_SWAP__SHIFT) & A2XX_RB_COLOR_INFO_SWAP__MASK; 621 } 622 #define A2XX_RB_COLOR_INFO_BASE__MASK 0xfffff000 623 #define A2XX_RB_COLOR_INFO_BASE__SHIFT 12 624 static inline uint32_t A2XX_RB_COLOR_INFO_BASE(uint32_t val) 625 { 626 assert(!(val & 0x3ff)); 627 return ((val >> 10) << A2XX_RB_COLOR_INFO_BASE__SHIFT) & A2XX_RB_COLOR_INFO_BASE__MASK; 628 } 629 630 #define REG_A2XX_RB_DEPTH_INFO 0x00002002 631 #define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000001 632 #define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0 633 static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val) 634 { 635 return ((val) << A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; 636 } 637 #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff000 638 #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12 639 static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) 640 { 641 assert(!(val & 0x3ff)); 642 return ((val >> 10) << A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; 643 } 644 645 #define REG_A2XX_A225_RB_COLOR_INFO3 0x00002005 646 647 #define REG_A2XX_COHER_DEST_BASE_0 0x00002006 648 649 #define REG_A2XX_PA_SC_SCREEN_SCISSOR_TL 0x0000200e 650 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 651 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff 652 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 653 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_X(uint32_t val) 654 { 655 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK; 656 } 657 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000 658 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 659 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) 660 { 661 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK; 662 } 663 664 #define REG_A2XX_PA_SC_SCREEN_SCISSOR_BR 0x0000200f 665 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 666 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff 667 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 668 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_X(uint32_t val) 669 { 670 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK; 671 } 672 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000 673 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 674 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) 675 { 676 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK; 677 } 678 679 #define REG_A2XX_PA_SC_WINDOW_OFFSET 0x00002080 680 #define A2XX_PA_SC_WINDOW_OFFSET_X__MASK 0x00007fff 681 #define A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT 0 682 static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_X(int32_t val) 683 { 684 return ((val) << A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_X__MASK; 685 } 686 #define A2XX_PA_SC_WINDOW_OFFSET_Y__MASK 0x7fff0000 687 #define A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT 16 688 static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_Y(int32_t val) 689 { 690 return ((val) << A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_Y__MASK; 691 } 692 #define A2XX_PA_SC_WINDOW_OFFSET_DISABLE 0x80000000 693 694 #define REG_A2XX_PA_SC_WINDOW_SCISSOR_TL 0x00002081 695 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 696 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff 697 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 698 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 699 { 700 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK; 701 } 702 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 703 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 704 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 705 { 706 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK; 707 } 708 709 #define REG_A2XX_PA_SC_WINDOW_SCISSOR_BR 0x00002082 710 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 711 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff 712 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 713 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 714 { 715 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK; 716 } 717 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 718 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 719 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 720 { 721 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK; 722 } 723 724 #define REG_A2XX_UNKNOWN_2010 0x00002010 725 726 #define REG_A2XX_VGT_MAX_VTX_INDX 0x00002100 727 728 #define REG_A2XX_VGT_MIN_VTX_INDX 0x00002101 729 730 #define REG_A2XX_VGT_INDX_OFFSET 0x00002102 731 732 #define REG_A2XX_A225_PC_MULTI_PRIM_IB_RESET_INDX 0x00002103 733 734 #define REG_A2XX_RB_COLOR_MASK 0x00002104 735 #define A2XX_RB_COLOR_MASK_WRITE_RED 0x00000001 736 #define A2XX_RB_COLOR_MASK_WRITE_GREEN 0x00000002 737 #define A2XX_RB_COLOR_MASK_WRITE_BLUE 0x00000004 738 #define A2XX_RB_COLOR_MASK_WRITE_ALPHA 0x00000008 739 740 #define REG_A2XX_RB_BLEND_RED 0x00002105 741 742 #define REG_A2XX_RB_BLEND_GREEN 0x00002106 743 744 #define REG_A2XX_RB_BLEND_BLUE 0x00002107 745 746 #define REG_A2XX_RB_BLEND_ALPHA 0x00002108 747 748 #define REG_A2XX_RB_FOG_COLOR 0x00002109 749 750 #define REG_A2XX_RB_STENCILREFMASK_BF 0x0000210c 751 #define A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff 752 #define A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0 753 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) 754 { 755 return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; 756 } 757 #define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00 758 #define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8 759 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) 760 { 761 return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; 762 } 763 #define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000 764 #define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16 765 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) 766 { 767 return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; 768 } 769 770 #define REG_A2XX_RB_STENCILREFMASK 0x0000210d 771 #define A2XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff 772 #define A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 773 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) 774 { 775 return ((val) << A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILREF__MASK; 776 } 777 #define A2XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 778 #define A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 779 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) 780 { 781 return ((val) << A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILMASK__MASK; 782 } 783 #define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 784 #define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 785 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) 786 { 787 return ((val) << A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; 788 } 789 790 #define REG_A2XX_RB_ALPHA_REF 0x0000210e 791 792 #define REG_A2XX_PA_CL_VPORT_XSCALE 0x0000210f 793 #define A2XX_PA_CL_VPORT_XSCALE__MASK 0xffffffff 794 #define A2XX_PA_CL_VPORT_XSCALE__SHIFT 0 795 static inline uint32_t A2XX_PA_CL_VPORT_XSCALE(float val) 796 { 797 return ((fui(val)) << A2XX_PA_CL_VPORT_XSCALE__SHIFT) & A2XX_PA_CL_VPORT_XSCALE__MASK; 798 } 799 800 #define REG_A2XX_PA_CL_VPORT_XOFFSET 0x00002110 801 #define A2XX_PA_CL_VPORT_XOFFSET__MASK 0xffffffff 802 #define A2XX_PA_CL_VPORT_XOFFSET__SHIFT 0 803 static inline uint32_t A2XX_PA_CL_VPORT_XOFFSET(float val) 804 { 805 return ((fui(val)) << A2XX_PA_CL_VPORT_XOFFSET__SHIFT) & A2XX_PA_CL_VPORT_XOFFSET__MASK; 806 } 807 808 #define REG_A2XX_PA_CL_VPORT_YSCALE 0x00002111 809 #define A2XX_PA_CL_VPORT_YSCALE__MASK 0xffffffff 810 #define A2XX_PA_CL_VPORT_YSCALE__SHIFT 0 811 static inline uint32_t A2XX_PA_CL_VPORT_YSCALE(float val) 812 { 813 return ((fui(val)) << A2XX_PA_CL_VPORT_YSCALE__SHIFT) & A2XX_PA_CL_VPORT_YSCALE__MASK; 814 } 815 816 #define REG_A2XX_PA_CL_VPORT_YOFFSET 0x00002112 817 #define A2XX_PA_CL_VPORT_YOFFSET__MASK 0xffffffff 818 #define A2XX_PA_CL_VPORT_YOFFSET__SHIFT 0 819 static inline uint32_t A2XX_PA_CL_VPORT_YOFFSET(float val) 820 { 821 return ((fui(val)) << A2XX_PA_CL_VPORT_YOFFSET__SHIFT) & A2XX_PA_CL_VPORT_YOFFSET__MASK; 822 } 823 824 #define REG_A2XX_PA_CL_VPORT_ZSCALE 0x00002113 825 #define A2XX_PA_CL_VPORT_ZSCALE__MASK 0xffffffff 826 #define A2XX_PA_CL_VPORT_ZSCALE__SHIFT 0 827 static inline uint32_t A2XX_PA_CL_VPORT_ZSCALE(float val) 828 { 829 return ((fui(val)) << A2XX_PA_CL_VPORT_ZSCALE__SHIFT) & A2XX_PA_CL_VPORT_ZSCALE__MASK; 830 } 831 832 #define REG_A2XX_PA_CL_VPORT_ZOFFSET 0x00002114 833 #define A2XX_PA_CL_VPORT_ZOFFSET__MASK 0xffffffff 834 #define A2XX_PA_CL_VPORT_ZOFFSET__SHIFT 0 835 static inline uint32_t A2XX_PA_CL_VPORT_ZOFFSET(float val) 836 { 837 return ((fui(val)) << A2XX_PA_CL_VPORT_ZOFFSET__SHIFT) & A2XX_PA_CL_VPORT_ZOFFSET__MASK; 838 } 839 840 #define REG_A2XX_SQ_PROGRAM_CNTL 0x00002180 841 #define A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK 0x000000ff 842 #define A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT 0 843 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_REGS(uint32_t val) 844 { 845 return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK; 846 } 847 #define A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK 0x0000ff00 848 #define A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT 8 849 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_REGS(uint32_t val) 850 { 851 return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK; 852 } 853 #define A2XX_SQ_PROGRAM_CNTL_VS_RESOURCE 0x00010000 854 #define A2XX_SQ_PROGRAM_CNTL_PS_RESOURCE 0x00020000 855 #define A2XX_SQ_PROGRAM_CNTL_PARAM_GEN 0x00040000 856 #define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_PIX 0x00080000 857 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK 0x00f00000 858 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT 20 859 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT(uint32_t val) 860 { 861 return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK; 862 } 863 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK 0x07000000 864 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT 24 865 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE(enum a2xx_sq_ps_vtx_mode val) 866 { 867 return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK; 868 } 869 #define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK 0x78000000 870 #define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT 27 871 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE(uint32_t val) 872 { 873 return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK; 874 } 875 #define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_VTX 0x80000000 876 877 #define REG_A2XX_SQ_CONTEXT_MISC 0x00002181 878 #define A2XX_SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE 0x00000001 879 #define A2XX_SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY 0x00000002 880 #define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK 0x0000000c 881 #define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT 2 882 static inline uint32_t A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(enum a2xx_sq_sample_cntl val) 883 { 884 return ((val) << A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT) & A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK; 885 } 886 #define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK 0x0000ff00 887 #define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT 8 888 static inline uint32_t A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val) 889 { 890 return ((val) << A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT) & A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK; 891 } 892 #define A2XX_SQ_CONTEXT_MISC_PERFCOUNTER_REF 0x00010000 893 #define A2XX_SQ_CONTEXT_MISC_YEILD_OPTIMIZE 0x00020000 894 #define A2XX_SQ_CONTEXT_MISC_TX_CACHE_SEL 0x00040000 895 896 #define REG_A2XX_SQ_INTERPOLATOR_CNTL 0x00002182 897 898 #define REG_A2XX_SQ_WRAPPING_0 0x00002183 899 900 #define REG_A2XX_SQ_WRAPPING_1 0x00002184 901 902 #define REG_A2XX_SQ_PS_PROGRAM 0x000021f6 903 904 #define REG_A2XX_SQ_VS_PROGRAM 0x000021f7 905 906 #define REG_A2XX_VGT_EVENT_INITIATOR 0x000021f9 907 908 #define REG_A2XX_VGT_DRAW_INITIATOR 0x000021fc 909 #define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f 910 #define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0 911 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) 912 { 913 return ((val) << A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK; 914 } 915 #define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0 916 #define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6 917 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) 918 { 919 return ((val) << A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK; 920 } 921 #define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK 0x00000600 922 #define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT 9 923 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) 924 { 925 return ((val) << A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT) & A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK; 926 } 927 #define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000800 928 #define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT 11 929 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val) 930 { 931 return ((val) << A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK; 932 } 933 #define A2XX_VGT_DRAW_INITIATOR_NOT_EOP 0x00001000 934 #define A2XX_VGT_DRAW_INITIATOR_SMALL_INDEX 0x00002000 935 #define A2XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE 0x00004000 936 #define A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK 0xff000000 937 #define A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT 24 938 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val) 939 { 940 return ((val) << A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT) & A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK; 941 } 942 943 #define REG_A2XX_VGT_IMMED_DATA 0x000021fd 944 945 #define REG_A2XX_RB_DEPTHCONTROL 0x00002200 946 #define A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE 0x00000001 947 #define A2XX_RB_DEPTHCONTROL_Z_ENABLE 0x00000002 948 #define A2XX_RB_DEPTHCONTROL_Z_WRITE_ENABLE 0x00000004 949 #define A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE 0x00000008 950 #define A2XX_RB_DEPTHCONTROL_ZFUNC__MASK 0x00000070 951 #define A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT 4 952 static inline uint32_t A2XX_RB_DEPTHCONTROL_ZFUNC(enum adreno_compare_func val) 953 { 954 return ((val) << A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_ZFUNC__MASK; 955 } 956 #define A2XX_RB_DEPTHCONTROL_BACKFACE_ENABLE 0x00000080 957 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK 0x00000700 958 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT 8 959 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC(enum adreno_compare_func val) 960 { 961 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK; 962 } 963 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK 0x00003800 964 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT 11 965 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL(enum adreno_stencil_op val) 966 { 967 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK; 968 } 969 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK 0x0001c000 970 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT 14 971 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS(enum adreno_stencil_op val) 972 { 973 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK; 974 } 975 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK 0x000e0000 976 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT 17 977 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL(enum adreno_stencil_op val) 978 { 979 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK; 980 } 981 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK 0x00700000 982 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT 20 983 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF(enum adreno_compare_func val) 984 { 985 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK; 986 } 987 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK 0x03800000 988 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT 23 989 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF(enum adreno_stencil_op val) 990 { 991 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK; 992 } 993 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK 0x1c000000 994 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT 26 995 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF(enum adreno_stencil_op val) 996 { 997 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK; 998 } 999 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK 0xe0000000 1000 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT 29 1001 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF(enum adreno_stencil_op val) 1002 { 1003 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK; 1004 } 1005 1006 #define REG_A2XX_RB_BLEND_CONTROL 0x00002201 1007 #define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK 0x0000001f 1008 #define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT 0 1009 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(enum adreno_rb_blend_factor val) 1010 { 1011 return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK; 1012 } 1013 #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK 0x000000e0 1014 #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT 5 1015 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(enum a2xx_rb_blend_opcode val) 1016 { 1017 return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK; 1018 } 1019 #define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK 0x00001f00 1020 #define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT 8 1021 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(enum adreno_rb_blend_factor val) 1022 { 1023 return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK; 1024 } 1025 #define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK 0x001f0000 1026 #define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT 16 1027 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(enum adreno_rb_blend_factor val) 1028 { 1029 return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK; 1030 } 1031 #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK 0x00e00000 1032 #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT 21 1033 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(enum a2xx_rb_blend_opcode val) 1034 { 1035 return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK; 1036 } 1037 #define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK 0x1f000000 1038 #define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT 24 1039 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(enum adreno_rb_blend_factor val) 1040 { 1041 return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK; 1042 } 1043 #define A2XX_RB_BLEND_CONTROL_BLEND_FORCE_ENABLE 0x20000000 1044 #define A2XX_RB_BLEND_CONTROL_BLEND_FORCE 0x40000000 1045 1046 #define REG_A2XX_RB_COLORCONTROL 0x00002202 1047 #define A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK 0x00000007 1048 #define A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT 0 1049 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_FUNC(enum adreno_compare_func val) 1050 { 1051 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK; 1052 } 1053 #define A2XX_RB_COLORCONTROL_ALPHA_TEST_ENABLE 0x00000008 1054 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE 0x00000010 1055 #define A2XX_RB_COLORCONTROL_BLEND_DISABLE 0x00000020 1056 #define A2XX_RB_COLORCONTROL_VOB_ENABLE 0x00000040 1057 #define A2XX_RB_COLORCONTROL_VS_EXPORTS_FOG 0x00000080 1058 #define A2XX_RB_COLORCONTROL_ROP_CODE__MASK 0x00000f00 1059 #define A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT 8 1060 static inline uint32_t A2XX_RB_COLORCONTROL_ROP_CODE(uint32_t val) 1061 { 1062 return ((val) << A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT) & A2XX_RB_COLORCONTROL_ROP_CODE__MASK; 1063 } 1064 #define A2XX_RB_COLORCONTROL_DITHER_MODE__MASK 0x00003000 1065 #define A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT 12 1066 static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_MODE(enum adreno_rb_dither_mode val) 1067 { 1068 return ((val) << A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_MODE__MASK; 1069 } 1070 #define A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK 0x0000c000 1071 #define A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT 14 1072 static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_TYPE(enum a2xx_rb_dither_type val) 1073 { 1074 return ((val) << A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK; 1075 } 1076 #define A2XX_RB_COLORCONTROL_PIXEL_FOG 0x00010000 1077 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK 0x03000000 1078 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT 24 1079 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0(uint32_t val) 1080 { 1081 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK; 1082 } 1083 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK 0x0c000000 1084 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT 26 1085 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1(uint32_t val) 1086 { 1087 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK; 1088 } 1089 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK 0x30000000 1090 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT 28 1091 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2(uint32_t val) 1092 { 1093 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK; 1094 } 1095 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK 0xc0000000 1096 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT 30 1097 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3(uint32_t val) 1098 { 1099 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK; 1100 } 1101 1102 #define REG_A2XX_VGT_CURRENT_BIN_ID_MAX 0x00002203 1103 #define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK 0x00000007 1104 #define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT 0 1105 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN(uint32_t val) 1106 { 1107 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK; 1108 } 1109 #define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK 0x00000038 1110 #define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT 3 1111 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_ROW(uint32_t val) 1112 { 1113 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK; 1114 } 1115 #define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK 0x000001c0 1116 #define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT 6 1117 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK(uint32_t val) 1118 { 1119 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK; 1120 } 1121 1122 #define REG_A2XX_PA_CL_CLIP_CNTL 0x00002204 1123 #define A2XX_PA_CL_CLIP_CNTL_CLIP_DISABLE 0x00010000 1124 #define A2XX_PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA 0x00040000 1125 #define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK 0x00080000 1126 #define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT 19 1127 static inline uint32_t A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF(enum a2xx_dx_clip_space val) 1128 { 1129 return ((val) << A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT) & A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK; 1130 } 1131 #define A2XX_PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT 0x00100000 1132 #define A2XX_PA_CL_CLIP_CNTL_VTX_KILL_OR 0x00200000 1133 #define A2XX_PA_CL_CLIP_CNTL_XY_NAN_RETAIN 0x00400000 1134 #define A2XX_PA_CL_CLIP_CNTL_Z_NAN_RETAIN 0x00800000 1135 #define A2XX_PA_CL_CLIP_CNTL_W_NAN_RETAIN 0x01000000 1136 1137 #define REG_A2XX_PA_SU_SC_MODE_CNTL 0x00002205 1138 #define A2XX_PA_SU_SC_MODE_CNTL_CULL_FRONT 0x00000001 1139 #define A2XX_PA_SU_SC_MODE_CNTL_CULL_BACK 0x00000002 1140 #define A2XX_PA_SU_SC_MODE_CNTL_FACE 0x00000004 1141 #define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK 0x00000018 1142 #define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT 3 1143 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_POLYMODE(enum a2xx_pa_su_sc_polymode val) 1144 { 1145 return ((val) << A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK; 1146 } 1147 #define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK 0x000000e0 1148 #define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT 5 1149 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) 1150 { 1151 return ((val) << A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK; 1152 } 1153 #define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK 0x00000700 1154 #define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT 8 1155 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(enum adreno_pa_su_sc_draw val) 1156 { 1157 return ((val) << A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK; 1158 } 1159 #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE 0x00000800 1160 #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE 0x00001000 1161 #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE 0x00002000 1162 #define A2XX_PA_SU_SC_MODE_CNTL_MSAA_ENABLE 0x00008000 1163 #define A2XX_PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE 0x00010000 1164 #define A2XX_PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE 0x00040000 1165 #define A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST 0x00080000 1166 #define A2XX_PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS 0x00100000 1167 #define A2XX_PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA 0x00200000 1168 #define A2XX_PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE 0x00800000 1169 #define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI 0x02000000 1170 #define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE 0x04000000 1171 #define A2XX_PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS 0x10000000 1172 #define A2XX_PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS 0x20000000 1173 #define A2XX_PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE 0x40000000 1174 #define A2XX_PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE 0x80000000 1175 1176 #define REG_A2XX_PA_CL_VTE_CNTL 0x00002206 1177 #define A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA 0x00000001 1178 #define A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA 0x00000002 1179 #define A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA 0x00000004 1180 #define A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA 0x00000008 1181 #define A2XX_PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA 0x00000010 1182 #define A2XX_PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA 0x00000020 1183 #define A2XX_PA_CL_VTE_CNTL_VTX_XY_FMT 0x00000100 1184 #define A2XX_PA_CL_VTE_CNTL_VTX_Z_FMT 0x00000200 1185 #define A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT 0x00000400 1186 #define A2XX_PA_CL_VTE_CNTL_PERFCOUNTER_REF 0x00000800 1187 1188 #define REG_A2XX_VGT_CURRENT_BIN_ID_MIN 0x00002207 1189 #define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK 0x00000007 1190 #define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT 0 1191 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN(uint32_t val) 1192 { 1193 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK; 1194 } 1195 #define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK 0x00000038 1196 #define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT 3 1197 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_ROW(uint32_t val) 1198 { 1199 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK; 1200 } 1201 #define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK 0x000001c0 1202 #define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT 6 1203 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK(uint32_t val) 1204 { 1205 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK; 1206 } 1207 1208 #define REG_A2XX_RB_MODECONTROL 0x00002208 1209 #define A2XX_RB_MODECONTROL_EDRAM_MODE__MASK 0x00000007 1210 #define A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT 0 1211 static inline uint32_t A2XX_RB_MODECONTROL_EDRAM_MODE(enum a2xx_rb_edram_mode val) 1212 { 1213 return ((val) << A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT) & A2XX_RB_MODECONTROL_EDRAM_MODE__MASK; 1214 } 1215 1216 #define REG_A2XX_A220_RB_LRZ_VSC_CONTROL 0x00002209 1217 1218 #define REG_A2XX_RB_SAMPLE_POS 0x0000220a 1219 1220 #define REG_A2XX_CLEAR_COLOR 0x0000220b 1221 #define A2XX_CLEAR_COLOR_RED__MASK 0x000000ff 1222 #define A2XX_CLEAR_COLOR_RED__SHIFT 0 1223 static inline uint32_t A2XX_CLEAR_COLOR_RED(uint32_t val) 1224 { 1225 return ((val) << A2XX_CLEAR_COLOR_RED__SHIFT) & A2XX_CLEAR_COLOR_RED__MASK; 1226 } 1227 #define A2XX_CLEAR_COLOR_GREEN__MASK 0x0000ff00 1228 #define A2XX_CLEAR_COLOR_GREEN__SHIFT 8 1229 static inline uint32_t A2XX_CLEAR_COLOR_GREEN(uint32_t val) 1230 { 1231 return ((val) << A2XX_CLEAR_COLOR_GREEN__SHIFT) & A2XX_CLEAR_COLOR_GREEN__MASK; 1232 } 1233 #define A2XX_CLEAR_COLOR_BLUE__MASK 0x00ff0000 1234 #define A2XX_CLEAR_COLOR_BLUE__SHIFT 16 1235 static inline uint32_t A2XX_CLEAR_COLOR_BLUE(uint32_t val) 1236 { 1237 return ((val) << A2XX_CLEAR_COLOR_BLUE__SHIFT) & A2XX_CLEAR_COLOR_BLUE__MASK; 1238 } 1239 #define A2XX_CLEAR_COLOR_ALPHA__MASK 0xff000000 1240 #define A2XX_CLEAR_COLOR_ALPHA__SHIFT 24 1241 static inline uint32_t A2XX_CLEAR_COLOR_ALPHA(uint32_t val) 1242 { 1243 return ((val) << A2XX_CLEAR_COLOR_ALPHA__SHIFT) & A2XX_CLEAR_COLOR_ALPHA__MASK; 1244 } 1245 1246 #define REG_A2XX_A220_GRAS_CONTROL 0x00002210 1247 1248 #define REG_A2XX_PA_SU_POINT_SIZE 0x00002280 1249 #define A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK 0x0000ffff 1250 #define A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT 0 1251 static inline uint32_t A2XX_PA_SU_POINT_SIZE_HEIGHT(float val) 1252 { 1253 return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT) & A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK; 1254 } 1255 #define A2XX_PA_SU_POINT_SIZE_WIDTH__MASK 0xffff0000 1256 #define A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT 16 1257 static inline uint32_t A2XX_PA_SU_POINT_SIZE_WIDTH(float val) 1258 { 1259 return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT) & A2XX_PA_SU_POINT_SIZE_WIDTH__MASK; 1260 } 1261 1262 #define REG_A2XX_PA_SU_POINT_MINMAX 0x00002281 1263 #define A2XX_PA_SU_POINT_MINMAX_MIN__MASK 0x0000ffff 1264 #define A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT 0 1265 static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MIN(float val) 1266 { 1267 return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MIN__MASK; 1268 } 1269 #define A2XX_PA_SU_POINT_MINMAX_MAX__MASK 0xffff0000 1270 #define A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT 16 1271 static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MAX(float val) 1272 { 1273 return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MAX__MASK; 1274 } 1275 1276 #define REG_A2XX_PA_SU_LINE_CNTL 0x00002282 1277 #define A2XX_PA_SU_LINE_CNTL_WIDTH__MASK 0x0000ffff 1278 #define A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT 0 1279 static inline uint32_t A2XX_PA_SU_LINE_CNTL_WIDTH(float val) 1280 { 1281 return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT) & A2XX_PA_SU_LINE_CNTL_WIDTH__MASK; 1282 } 1283 1284 #define REG_A2XX_PA_SC_LINE_STIPPLE 0x00002283 1285 #define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK 0x0000ffff 1286 #define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT 0 1287 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN(uint32_t val) 1288 { 1289 return ((val) << A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK; 1290 } 1291 #define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK 0x00ff0000 1292 #define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT 16 1293 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT(uint32_t val) 1294 { 1295 return ((val) << A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK; 1296 } 1297 #define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK 0x10000000 1298 #define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT 28 1299 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER(enum a2xx_pa_sc_pattern_bit_order val) 1300 { 1301 return ((val) << A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK; 1302 } 1303 #define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK 0x60000000 1304 #define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT 29 1305 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL(enum a2xx_pa_sc_auto_reset_cntl val) 1306 { 1307 return ((val) << A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK; 1308 } 1309 1310 #define REG_A2XX_PA_SC_VIZ_QUERY 0x00002293 1311 1312 #define REG_A2XX_VGT_ENHANCE 0x00002294 1313 1314 #define REG_A2XX_PA_SC_LINE_CNTL 0x00002300 1315 #define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK 0x0000ffff 1316 #define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT 0 1317 static inline uint32_t A2XX_PA_SC_LINE_CNTL_BRES_CNTL(uint32_t val) 1318 { 1319 return ((val) << A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT) & A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK; 1320 } 1321 #define A2XX_PA_SC_LINE_CNTL_USE_BRES_CNTL 0x00000100 1322 #define A2XX_PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH 0x00000200 1323 #define A2XX_PA_SC_LINE_CNTL_LAST_PIXEL 0x00000400 1324 1325 #define REG_A2XX_PA_SC_AA_CONFIG 0x00002301 1326 1327 #define REG_A2XX_PA_SU_VTX_CNTL 0x00002302 1328 #define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK 0x00000001 1329 #define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT 0 1330 static inline uint32_t A2XX_PA_SU_VTX_CNTL_PIX_CENTER(enum a2xx_pa_pixcenter val) 1331 { 1332 return ((val) << A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT) & A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK; 1333 } 1334 #define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK 0x00000006 1335 #define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT 1 1336 static inline uint32_t A2XX_PA_SU_VTX_CNTL_ROUND_MODE(enum a2xx_pa_roundmode val) 1337 { 1338 return ((val) << A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK; 1339 } 1340 #define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK 0x00000380 1341 #define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT 7 1342 static inline uint32_t A2XX_PA_SU_VTX_CNTL_QUANT_MODE(enum a2xx_pa_quantmode val) 1343 { 1344 return ((val) << A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK; 1345 } 1346 1347 #define REG_A2XX_PA_CL_GB_VERT_CLIP_ADJ 0x00002303 1348 #define A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK 0xffffffff 1349 #define A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT 0 1350 static inline uint32_t A2XX_PA_CL_GB_VERT_CLIP_ADJ(float val) 1351 { 1352 return ((fui(val)) << A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK; 1353 } 1354 1355 #define REG_A2XX_PA_CL_GB_VERT_DISC_ADJ 0x00002304 1356 #define A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK 0xffffffff 1357 #define A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT 0 1358 static inline uint32_t A2XX_PA_CL_GB_VERT_DISC_ADJ(float val) 1359 { 1360 return ((fui(val)) << A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK; 1361 } 1362 1363 #define REG_A2XX_PA_CL_GB_HORZ_CLIP_ADJ 0x00002305 1364 #define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK 0xffffffff 1365 #define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT 0 1366 static inline uint32_t A2XX_PA_CL_GB_HORZ_CLIP_ADJ(float val) 1367 { 1368 return ((fui(val)) << A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK; 1369 } 1370 1371 #define REG_A2XX_PA_CL_GB_HORZ_DISC_ADJ 0x00002306 1372 #define A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK 0xffffffff 1373 #define A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT 0 1374 static inline uint32_t A2XX_PA_CL_GB_HORZ_DISC_ADJ(float val) 1375 { 1376 return ((fui(val)) << A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK; 1377 } 1378 1379 #define REG_A2XX_SQ_VS_CONST 0x00002307 1380 #define A2XX_SQ_VS_CONST_BASE__MASK 0x000001ff 1381 #define A2XX_SQ_VS_CONST_BASE__SHIFT 0 1382 static inline uint32_t A2XX_SQ_VS_CONST_BASE(uint32_t val) 1383 { 1384 return ((val) << A2XX_SQ_VS_CONST_BASE__SHIFT) & A2XX_SQ_VS_CONST_BASE__MASK; 1385 } 1386 #define A2XX_SQ_VS_CONST_SIZE__MASK 0x001ff000 1387 #define A2XX_SQ_VS_CONST_SIZE__SHIFT 12 1388 static inline uint32_t A2XX_SQ_VS_CONST_SIZE(uint32_t val) 1389 { 1390 return ((val) << A2XX_SQ_VS_CONST_SIZE__SHIFT) & A2XX_SQ_VS_CONST_SIZE__MASK; 1391 } 1392 1393 #define REG_A2XX_SQ_PS_CONST 0x00002308 1394 #define A2XX_SQ_PS_CONST_BASE__MASK 0x000001ff 1395 #define A2XX_SQ_PS_CONST_BASE__SHIFT 0 1396 static inline uint32_t A2XX_SQ_PS_CONST_BASE(uint32_t val) 1397 { 1398 return ((val) << A2XX_SQ_PS_CONST_BASE__SHIFT) & A2XX_SQ_PS_CONST_BASE__MASK; 1399 } 1400 #define A2XX_SQ_PS_CONST_SIZE__MASK 0x001ff000 1401 #define A2XX_SQ_PS_CONST_SIZE__SHIFT 12 1402 static inline uint32_t A2XX_SQ_PS_CONST_SIZE(uint32_t val) 1403 { 1404 return ((val) << A2XX_SQ_PS_CONST_SIZE__SHIFT) & A2XX_SQ_PS_CONST_SIZE__MASK; 1405 } 1406 1407 #define REG_A2XX_SQ_DEBUG_MISC_0 0x00002309 1408 1409 #define REG_A2XX_SQ_DEBUG_MISC_1 0x0000230a 1410 1411 #define REG_A2XX_PA_SC_AA_MASK 0x00002312 1412 1413 #define REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL 0x00002316 1414 1415 #define REG_A2XX_VGT_OUT_DEALLOC_CNTL 0x00002317 1416 1417 #define REG_A2XX_RB_COPY_CONTROL 0x00002318 1418 #define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK 0x00000007 1419 #define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT 0 1420 static inline uint32_t A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT(enum a2xx_rb_copy_sample_select val) 1421 { 1422 return ((val) << A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT) & A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK; 1423 } 1424 #define A2XX_RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE 0x00000008 1425 #define A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK 0x000000f0 1426 #define A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT 4 1427 static inline uint32_t A2XX_RB_COPY_CONTROL_CLEAR_MASK(uint32_t val) 1428 { 1429 return ((val) << A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT) & A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK; 1430 } 1431 1432 #define REG_A2XX_RB_COPY_DEST_BASE 0x00002319 1433 1434 #define REG_A2XX_RB_COPY_DEST_PITCH 0x0000231a 1435 #define A2XX_RB_COPY_DEST_PITCH__MASK 0xffffffff 1436 #define A2XX_RB_COPY_DEST_PITCH__SHIFT 0 1437 static inline uint32_t A2XX_RB_COPY_DEST_PITCH(uint32_t val) 1438 { 1439 assert(!(val & 0x1f)); 1440 return ((val >> 5) << A2XX_RB_COPY_DEST_PITCH__SHIFT) & A2XX_RB_COPY_DEST_PITCH__MASK; 1441 } 1442 1443 #define REG_A2XX_RB_COPY_DEST_INFO 0x0000231b 1444 #define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK 0x00000007 1445 #define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT 0 1446 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN(enum adreno_rb_surface_endian val) 1447 { 1448 return ((val) << A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT) & A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK; 1449 } 1450 #define A2XX_RB_COPY_DEST_INFO_LINEAR 0x00000008 1451 #define A2XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000f0 1452 #define A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 4 1453 static inline uint32_t A2XX_RB_COPY_DEST_INFO_FORMAT(enum a2xx_colorformatx val) 1454 { 1455 return ((val) << A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A2XX_RB_COPY_DEST_INFO_FORMAT__MASK; 1456 } 1457 #define A2XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300 1458 #define A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8 1459 static inline uint32_t A2XX_RB_COPY_DEST_INFO_SWAP(uint32_t val) 1460 { 1461 return ((val) << A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A2XX_RB_COPY_DEST_INFO_SWAP__MASK; 1462 } 1463 #define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00 1464 #define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10 1465 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) 1466 { 1467 return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK; 1468 } 1469 #define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK 0x00003000 1470 #define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT 12 1471 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_TYPE(enum a2xx_rb_dither_type val) 1472 { 1473 return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK; 1474 } 1475 #define A2XX_RB_COPY_DEST_INFO_WRITE_RED 0x00004000 1476 #define A2XX_RB_COPY_DEST_INFO_WRITE_GREEN 0x00008000 1477 #define A2XX_RB_COPY_DEST_INFO_WRITE_BLUE 0x00010000 1478 #define A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA 0x00020000 1479 1480 #define REG_A2XX_RB_COPY_DEST_OFFSET 0x0000231c 1481 #define A2XX_RB_COPY_DEST_OFFSET_X__MASK 0x00001fff 1482 #define A2XX_RB_COPY_DEST_OFFSET_X__SHIFT 0 1483 static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_X(uint32_t val) 1484 { 1485 return ((val) << A2XX_RB_COPY_DEST_OFFSET_X__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_X__MASK; 1486 } 1487 #define A2XX_RB_COPY_DEST_OFFSET_Y__MASK 0x03ffe000 1488 #define A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT 13 1489 static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_Y(uint32_t val) 1490 { 1491 return ((val) << A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_Y__MASK; 1492 } 1493 1494 #define REG_A2XX_RB_DEPTH_CLEAR 0x0000231d 1495 1496 #define REG_A2XX_RB_SAMPLE_COUNT_CTL 0x00002324 1497 1498 #define REG_A2XX_RB_COLOR_DEST_MASK 0x00002326 1499 1500 #define REG_A2XX_A225_GRAS_UCP0X 0x00002340 1501 1502 #define REG_A2XX_A225_GRAS_UCP5W 0x00002357 1503 1504 #define REG_A2XX_A225_GRAS_UCP_ENABLED 0x00002360 1505 1506 #define REG_A2XX_PA_SU_POLY_OFFSET_FRONT_SCALE 0x00002380 1507 1508 #define REG_A2XX_PA_SU_POLY_OFFSET_BACK_OFFSET 0x00002383 1509 1510 #define REG_A2XX_SQ_CONSTANT_0 0x00004000 1511 1512 #define REG_A2XX_SQ_FETCH_0 0x00004800 1513 1514 #define REG_A2XX_SQ_CF_BOOLEANS 0x00004900 1515 1516 #define REG_A2XX_SQ_CF_LOOP 0x00004908 1517 1518 #define REG_A2XX_COHER_SIZE_PM4 0x00000a29 1519 1520 #define REG_A2XX_COHER_BASE_PM4 0x00000a2a 1521 1522 #define REG_A2XX_COHER_STATUS_PM4 0x00000a2b 1523 1524 #define REG_A2XX_SQ_TEX_0 0x00000000 1525 #define A2XX_SQ_TEX_0_CLAMP_X__MASK 0x00001c00 1526 #define A2XX_SQ_TEX_0_CLAMP_X__SHIFT 10 1527 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_X(enum sq_tex_clamp val) 1528 { 1529 return ((val) << A2XX_SQ_TEX_0_CLAMP_X__SHIFT) & A2XX_SQ_TEX_0_CLAMP_X__MASK; 1530 } 1531 #define A2XX_SQ_TEX_0_CLAMP_Y__MASK 0x0000e000 1532 #define A2XX_SQ_TEX_0_CLAMP_Y__SHIFT 13 1533 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Y(enum sq_tex_clamp val) 1534 { 1535 return ((val) << A2XX_SQ_TEX_0_CLAMP_Y__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Y__MASK; 1536 } 1537 #define A2XX_SQ_TEX_0_CLAMP_Z__MASK 0x00070000 1538 #define A2XX_SQ_TEX_0_CLAMP_Z__SHIFT 16 1539 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Z(enum sq_tex_clamp val) 1540 { 1541 return ((val) << A2XX_SQ_TEX_0_CLAMP_Z__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Z__MASK; 1542 } 1543 #define A2XX_SQ_TEX_0_PITCH__MASK 0xffc00000 1544 #define A2XX_SQ_TEX_0_PITCH__SHIFT 22 1545 static inline uint32_t A2XX_SQ_TEX_0_PITCH(uint32_t val) 1546 { 1547 assert(!(val & 0x1f)); 1548 return ((val >> 5) << A2XX_SQ_TEX_0_PITCH__SHIFT) & A2XX_SQ_TEX_0_PITCH__MASK; 1549 } 1550 1551 #define REG_A2XX_SQ_TEX_1 0x00000001 1552 1553 #define REG_A2XX_SQ_TEX_2 0x00000002 1554 #define A2XX_SQ_TEX_2_WIDTH__MASK 0x00001fff 1555 #define A2XX_SQ_TEX_2_WIDTH__SHIFT 0 1556 static inline uint32_t A2XX_SQ_TEX_2_WIDTH(uint32_t val) 1557 { 1558 return ((val) << A2XX_SQ_TEX_2_WIDTH__SHIFT) & A2XX_SQ_TEX_2_WIDTH__MASK; 1559 } 1560 #define A2XX_SQ_TEX_2_HEIGHT__MASK 0x03ffe000 1561 #define A2XX_SQ_TEX_2_HEIGHT__SHIFT 13 1562 static inline uint32_t A2XX_SQ_TEX_2_HEIGHT(uint32_t val) 1563 { 1564 return ((val) << A2XX_SQ_TEX_2_HEIGHT__SHIFT) & A2XX_SQ_TEX_2_HEIGHT__MASK; 1565 } 1566 1567 #define REG_A2XX_SQ_TEX_3 0x00000003 1568 #define A2XX_SQ_TEX_3_SWIZ_X__MASK 0x0000000e 1569 #define A2XX_SQ_TEX_3_SWIZ_X__SHIFT 1 1570 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_X(enum sq_tex_swiz val) 1571 { 1572 return ((val) << A2XX_SQ_TEX_3_SWIZ_X__SHIFT) & A2XX_SQ_TEX_3_SWIZ_X__MASK; 1573 } 1574 #define A2XX_SQ_TEX_3_SWIZ_Y__MASK 0x00000070 1575 #define A2XX_SQ_TEX_3_SWIZ_Y__SHIFT 4 1576 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Y(enum sq_tex_swiz val) 1577 { 1578 return ((val) << A2XX_SQ_TEX_3_SWIZ_Y__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Y__MASK; 1579 } 1580 #define A2XX_SQ_TEX_3_SWIZ_Z__MASK 0x00000380 1581 #define A2XX_SQ_TEX_3_SWIZ_Z__SHIFT 7 1582 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Z(enum sq_tex_swiz val) 1583 { 1584 return ((val) << A2XX_SQ_TEX_3_SWIZ_Z__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Z__MASK; 1585 } 1586 #define A2XX_SQ_TEX_3_SWIZ_W__MASK 0x00001c00 1587 #define A2XX_SQ_TEX_3_SWIZ_W__SHIFT 10 1588 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_W(enum sq_tex_swiz val) 1589 { 1590 return ((val) << A2XX_SQ_TEX_3_SWIZ_W__SHIFT) & A2XX_SQ_TEX_3_SWIZ_W__MASK; 1591 } 1592 #define A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK 0x00180000 1593 #define A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT 19 1594 static inline uint32_t A2XX_SQ_TEX_3_XY_MAG_FILTER(enum sq_tex_filter val) 1595 { 1596 return ((val) << A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK; 1597 } 1598 #define A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK 0x00600000 1599 #define A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT 21 1600 static inline uint32_t A2XX_SQ_TEX_3_XY_MIN_FILTER(enum sq_tex_filter val) 1601 { 1602 return ((val) << A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK; 1603 } 1604 1605 1606 #endif /* A2XX_XML */ 1607
