1 #ifndef A3XX_XML 2 #define A3XX_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2016-04-26 17:56:44) 12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) 13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32907 bytes, from 2016-11-26 23:01:08) 14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2016-11-26 23:01:08) 15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 23277 bytes, from 2016-12-24 05:01:47) 16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2016-11-26 23:01:08) 17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110757 bytes, from 2016-12-26 17:51:07) 18 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 100594 bytes, from 2017-01-20 23:03:30) 19 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00) 20 21 Copyright (C) 2013-2016 by the following authors: 22 - Rob Clark <robdclark (at) gmail.com> (robclark) 23 - Ilia Mirkin <imirkin (at) alum.mit.edu> (imirkin) 24 25 Permission is hereby granted, free of charge, to any person obtaining 26 a copy of this software and associated documentation files (the 27 "Software"), to deal in the Software without restriction, including 28 without limitation the rights to use, copy, modify, merge, publish, 29 distribute, sublicense, and/or sell copies of the Software, and to 30 permit persons to whom the Software is furnished to do so, subject to 31 the following conditions: 32 33 The above copyright notice and this permission notice (including the 34 next paragraph) shall be included in all copies or substantial 35 portions of the Software. 36 37 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 38 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 39 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 40 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 41 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 42 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 43 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 44 */ 45 46 47 enum a3xx_tile_mode { 48 LINEAR = 0, 49 TILE_32X32 = 2, 50 }; 51 52 enum a3xx_state_block_id { 53 HLSQ_BLOCK_ID_TP_TEX = 2, 54 HLSQ_BLOCK_ID_TP_MIPMAP = 3, 55 HLSQ_BLOCK_ID_SP_VS = 4, 56 HLSQ_BLOCK_ID_SP_FS = 6, 57 }; 58 59 enum a3xx_cache_opcode { 60 INVALIDATE = 1, 61 }; 62 63 enum a3xx_vtx_fmt { 64 VFMT_32_FLOAT = 0, 65 VFMT_32_32_FLOAT = 1, 66 VFMT_32_32_32_FLOAT = 2, 67 VFMT_32_32_32_32_FLOAT = 3, 68 VFMT_16_FLOAT = 4, 69 VFMT_16_16_FLOAT = 5, 70 VFMT_16_16_16_FLOAT = 6, 71 VFMT_16_16_16_16_FLOAT = 7, 72 VFMT_32_FIXED = 8, 73 VFMT_32_32_FIXED = 9, 74 VFMT_32_32_32_FIXED = 10, 75 VFMT_32_32_32_32_FIXED = 11, 76 VFMT_16_SINT = 16, 77 VFMT_16_16_SINT = 17, 78 VFMT_16_16_16_SINT = 18, 79 VFMT_16_16_16_16_SINT = 19, 80 VFMT_16_UINT = 20, 81 VFMT_16_16_UINT = 21, 82 VFMT_16_16_16_UINT = 22, 83 VFMT_16_16_16_16_UINT = 23, 84 VFMT_16_SNORM = 24, 85 VFMT_16_16_SNORM = 25, 86 VFMT_16_16_16_SNORM = 26, 87 VFMT_16_16_16_16_SNORM = 27, 88 VFMT_16_UNORM = 28, 89 VFMT_16_16_UNORM = 29, 90 VFMT_16_16_16_UNORM = 30, 91 VFMT_16_16_16_16_UNORM = 31, 92 VFMT_32_UINT = 32, 93 VFMT_32_32_UINT = 33, 94 VFMT_32_32_32_UINT = 34, 95 VFMT_32_32_32_32_UINT = 35, 96 VFMT_32_SINT = 36, 97 VFMT_32_32_SINT = 37, 98 VFMT_32_32_32_SINT = 38, 99 VFMT_32_32_32_32_SINT = 39, 100 VFMT_8_UINT = 40, 101 VFMT_8_8_UINT = 41, 102 VFMT_8_8_8_UINT = 42, 103 VFMT_8_8_8_8_UINT = 43, 104 VFMT_8_UNORM = 44, 105 VFMT_8_8_UNORM = 45, 106 VFMT_8_8_8_UNORM = 46, 107 VFMT_8_8_8_8_UNORM = 47, 108 VFMT_8_SINT = 48, 109 VFMT_8_8_SINT = 49, 110 VFMT_8_8_8_SINT = 50, 111 VFMT_8_8_8_8_SINT = 51, 112 VFMT_8_SNORM = 52, 113 VFMT_8_8_SNORM = 53, 114 VFMT_8_8_8_SNORM = 54, 115 VFMT_8_8_8_8_SNORM = 55, 116 VFMT_10_10_10_2_UINT = 56, 117 VFMT_10_10_10_2_UNORM = 57, 118 VFMT_10_10_10_2_SINT = 58, 119 VFMT_10_10_10_2_SNORM = 59, 120 VFMT_2_10_10_10_UINT = 60, 121 VFMT_2_10_10_10_UNORM = 61, 122 VFMT_2_10_10_10_SINT = 62, 123 VFMT_2_10_10_10_SNORM = 63, 124 }; 125 126 enum a3xx_tex_fmt { 127 TFMT_5_6_5_UNORM = 4, 128 TFMT_5_5_5_1_UNORM = 5, 129 TFMT_4_4_4_4_UNORM = 7, 130 TFMT_Z16_UNORM = 9, 131 TFMT_X8Z24_UNORM = 10, 132 TFMT_Z32_FLOAT = 11, 133 TFMT_UV_64X32 = 16, 134 TFMT_VU_64X32 = 17, 135 TFMT_Y_64X32 = 18, 136 TFMT_NV12_64X32 = 19, 137 TFMT_UV_LINEAR = 20, 138 TFMT_VU_LINEAR = 21, 139 TFMT_Y_LINEAR = 22, 140 TFMT_NV12_LINEAR = 23, 141 TFMT_I420_Y = 24, 142 TFMT_I420_U = 26, 143 TFMT_I420_V = 27, 144 TFMT_ATC_RGB = 32, 145 TFMT_ATC_RGBA_EXPLICIT = 33, 146 TFMT_ETC1 = 34, 147 TFMT_ATC_RGBA_INTERPOLATED = 35, 148 TFMT_DXT1 = 36, 149 TFMT_DXT3 = 37, 150 TFMT_DXT5 = 38, 151 TFMT_2_10_10_10_UNORM = 40, 152 TFMT_10_10_10_2_UNORM = 41, 153 TFMT_9_9_9_E5_FLOAT = 42, 154 TFMT_11_11_10_FLOAT = 43, 155 TFMT_A8_UNORM = 44, 156 TFMT_L8_UNORM = 45, 157 TFMT_L8_A8_UNORM = 47, 158 TFMT_8_UNORM = 48, 159 TFMT_8_8_UNORM = 49, 160 TFMT_8_8_8_UNORM = 50, 161 TFMT_8_8_8_8_UNORM = 51, 162 TFMT_8_SNORM = 52, 163 TFMT_8_8_SNORM = 53, 164 TFMT_8_8_8_SNORM = 54, 165 TFMT_8_8_8_8_SNORM = 55, 166 TFMT_8_UINT = 56, 167 TFMT_8_8_UINT = 57, 168 TFMT_8_8_8_UINT = 58, 169 TFMT_8_8_8_8_UINT = 59, 170 TFMT_8_SINT = 60, 171 TFMT_8_8_SINT = 61, 172 TFMT_8_8_8_SINT = 62, 173 TFMT_8_8_8_8_SINT = 63, 174 TFMT_16_FLOAT = 64, 175 TFMT_16_16_FLOAT = 65, 176 TFMT_16_16_16_16_FLOAT = 67, 177 TFMT_16_UINT = 68, 178 TFMT_16_16_UINT = 69, 179 TFMT_16_16_16_16_UINT = 71, 180 TFMT_16_SINT = 72, 181 TFMT_16_16_SINT = 73, 182 TFMT_16_16_16_16_SINT = 75, 183 TFMT_16_UNORM = 76, 184 TFMT_16_16_UNORM = 77, 185 TFMT_16_16_16_16_UNORM = 79, 186 TFMT_16_SNORM = 80, 187 TFMT_16_16_SNORM = 81, 188 TFMT_16_16_16_16_SNORM = 83, 189 TFMT_32_FLOAT = 84, 190 TFMT_32_32_FLOAT = 85, 191 TFMT_32_32_32_32_FLOAT = 87, 192 TFMT_32_UINT = 88, 193 TFMT_32_32_UINT = 89, 194 TFMT_32_32_32_32_UINT = 91, 195 TFMT_32_SINT = 92, 196 TFMT_32_32_SINT = 93, 197 TFMT_32_32_32_32_SINT = 95, 198 TFMT_2_10_10_10_UINT = 96, 199 TFMT_10_10_10_2_UINT = 97, 200 TFMT_ETC2_RG11_SNORM = 112, 201 TFMT_ETC2_RG11_UNORM = 113, 202 TFMT_ETC2_R11_SNORM = 114, 203 TFMT_ETC2_R11_UNORM = 115, 204 TFMT_ETC2_RGBA8 = 116, 205 TFMT_ETC2_RGB8A1 = 117, 206 TFMT_ETC2_RGB8 = 118, 207 }; 208 209 enum a3xx_tex_fetchsize { 210 TFETCH_DISABLE = 0, 211 TFETCH_1_BYTE = 1, 212 TFETCH_2_BYTE = 2, 213 TFETCH_4_BYTE = 3, 214 TFETCH_8_BYTE = 4, 215 TFETCH_16_BYTE = 5, 216 }; 217 218 enum a3xx_color_fmt { 219 RB_R5G6B5_UNORM = 0, 220 RB_R5G5B5A1_UNORM = 1, 221 RB_R4G4B4A4_UNORM = 3, 222 RB_R8G8B8_UNORM = 4, 223 RB_R8G8B8A8_UNORM = 8, 224 RB_R8G8B8A8_SNORM = 9, 225 RB_R8G8B8A8_UINT = 10, 226 RB_R8G8B8A8_SINT = 11, 227 RB_R8G8_UNORM = 12, 228 RB_R8G8_SNORM = 13, 229 RB_R8_UINT = 14, 230 RB_R8_SINT = 15, 231 RB_R10G10B10A2_UNORM = 16, 232 RB_A2R10G10B10_UNORM = 17, 233 RB_R10G10B10A2_UINT = 18, 234 RB_A2R10G10B10_UINT = 19, 235 RB_A8_UNORM = 20, 236 RB_R8_UNORM = 21, 237 RB_R16_FLOAT = 24, 238 RB_R16G16_FLOAT = 25, 239 RB_R16G16B16A16_FLOAT = 27, 240 RB_R11G11B10_FLOAT = 28, 241 RB_R16_SNORM = 32, 242 RB_R16G16_SNORM = 33, 243 RB_R16G16B16A16_SNORM = 35, 244 RB_R16_UNORM = 36, 245 RB_R16G16_UNORM = 37, 246 RB_R16G16B16A16_UNORM = 39, 247 RB_R16_SINT = 40, 248 RB_R16G16_SINT = 41, 249 RB_R16G16B16A16_SINT = 43, 250 RB_R16_UINT = 44, 251 RB_R16G16_UINT = 45, 252 RB_R16G16B16A16_UINT = 47, 253 RB_R32_FLOAT = 48, 254 RB_R32G32_FLOAT = 49, 255 RB_R32G32B32A32_FLOAT = 51, 256 RB_R32_SINT = 52, 257 RB_R32G32_SINT = 53, 258 RB_R32G32B32A32_SINT = 55, 259 RB_R32_UINT = 56, 260 RB_R32G32_UINT = 57, 261 RB_R32G32B32A32_UINT = 59, 262 }; 263 264 enum a3xx_cp_perfcounter_select { 265 CP_ALWAYS_COUNT = 0, 266 CP_AHB_PFPTRANS_WAIT = 3, 267 CP_AHB_NRTTRANS_WAIT = 6, 268 CP_CSF_NRT_READ_WAIT = 8, 269 CP_CSF_I1_FIFO_FULL = 9, 270 CP_CSF_I2_FIFO_FULL = 10, 271 CP_CSF_ST_FIFO_FULL = 11, 272 CP_RESERVED_12 = 12, 273 CP_CSF_RING_ROQ_FULL = 13, 274 CP_CSF_I1_ROQ_FULL = 14, 275 CP_CSF_I2_ROQ_FULL = 15, 276 CP_CSF_ST_ROQ_FULL = 16, 277 CP_RESERVED_17 = 17, 278 CP_MIU_TAG_MEM_FULL = 18, 279 CP_MIU_NRT_WRITE_STALLED = 22, 280 CP_MIU_NRT_READ_STALLED = 23, 281 CP_ME_REGS_RB_DONE_FIFO_FULL = 26, 282 CP_ME_REGS_VS_EVENT_FIFO_FULL = 27, 283 CP_ME_REGS_PS_EVENT_FIFO_FULL = 28, 284 CP_ME_REGS_CF_EVENT_FIFO_FULL = 29, 285 CP_ME_MICRO_RB_STARVED = 30, 286 CP_AHB_RBBM_DWORD_SENT = 40, 287 CP_ME_BUSY_CLOCKS = 41, 288 CP_ME_WAIT_CONTEXT_AVAIL = 42, 289 CP_PFP_TYPE0_PACKET = 43, 290 CP_PFP_TYPE3_PACKET = 44, 291 CP_CSF_RB_WPTR_NEQ_RPTR = 45, 292 CP_CSF_I1_SIZE_NEQ_ZERO = 46, 293 CP_CSF_I2_SIZE_NEQ_ZERO = 47, 294 CP_CSF_RBI1I2_FETCHING = 48, 295 }; 296 297 enum a3xx_gras_tse_perfcounter_select { 298 GRAS_TSEPERF_INPUT_PRIM = 0, 299 GRAS_TSEPERF_INPUT_NULL_PRIM = 1, 300 GRAS_TSEPERF_TRIVAL_REJ_PRIM = 2, 301 GRAS_TSEPERF_CLIPPED_PRIM = 3, 302 GRAS_TSEPERF_NEW_PRIM = 4, 303 GRAS_TSEPERF_ZERO_AREA_PRIM = 5, 304 GRAS_TSEPERF_FACENESS_CULLED_PRIM = 6, 305 GRAS_TSEPERF_ZERO_PIXEL_PRIM = 7, 306 GRAS_TSEPERF_OUTPUT_NULL_PRIM = 8, 307 GRAS_TSEPERF_OUTPUT_VISIBLE_PRIM = 9, 308 GRAS_TSEPERF_PRE_CLIP_PRIM = 10, 309 GRAS_TSEPERF_POST_CLIP_PRIM = 11, 310 GRAS_TSEPERF_WORKING_CYCLES = 12, 311 GRAS_TSEPERF_PC_STARVE = 13, 312 GRAS_TSERASPERF_STALL = 14, 313 }; 314 315 enum a3xx_gras_ras_perfcounter_select { 316 GRAS_RASPERF_16X16_TILES = 0, 317 GRAS_RASPERF_8X8_TILES = 1, 318 GRAS_RASPERF_4X4_TILES = 2, 319 GRAS_RASPERF_WORKING_CYCLES = 3, 320 GRAS_RASPERF_STALL_CYCLES_BY_RB = 4, 321 GRAS_RASPERF_STALL_CYCLES_BY_VSC = 5, 322 GRAS_RASPERF_STARVE_CYCLES_BY_TSE = 6, 323 }; 324 325 enum a3xx_hlsq_perfcounter_select { 326 HLSQ_PERF_SP_VS_CONSTANT = 0, 327 HLSQ_PERF_SP_VS_INSTRUCTIONS = 1, 328 HLSQ_PERF_SP_FS_CONSTANT = 2, 329 HLSQ_PERF_SP_FS_INSTRUCTIONS = 3, 330 HLSQ_PERF_TP_STATE = 4, 331 HLSQ_PERF_QUADS = 5, 332 HLSQ_PERF_PIXELS = 6, 333 HLSQ_PERF_VERTICES = 7, 334 HLSQ_PERF_FS8_THREADS = 8, 335 HLSQ_PERF_FS16_THREADS = 9, 336 HLSQ_PERF_FS32_THREADS = 10, 337 HLSQ_PERF_VS8_THREADS = 11, 338 HLSQ_PERF_VS16_THREADS = 12, 339 HLSQ_PERF_SP_VS_DATA_BYTES = 13, 340 HLSQ_PERF_SP_FS_DATA_BYTES = 14, 341 HLSQ_PERF_ACTIVE_CYCLES = 15, 342 HLSQ_PERF_STALL_CYCLES_SP_STATE = 16, 343 HLSQ_PERF_STALL_CYCLES_SP_VS = 17, 344 HLSQ_PERF_STALL_CYCLES_SP_FS = 18, 345 HLSQ_PERF_STALL_CYCLES_UCHE = 19, 346 HLSQ_PERF_RBBM_LOAD_CYCLES = 20, 347 HLSQ_PERF_DI_TO_VS_START_SP0 = 21, 348 HLSQ_PERF_DI_TO_FS_START_SP0 = 22, 349 HLSQ_PERF_VS_START_TO_DONE_SP0 = 23, 350 HLSQ_PERF_FS_START_TO_DONE_SP0 = 24, 351 HLSQ_PERF_SP_STATE_COPY_CYCLES_VS = 25, 352 HLSQ_PERF_SP_STATE_COPY_CYCLES_FS = 26, 353 HLSQ_PERF_UCHE_LATENCY_CYCLES = 27, 354 HLSQ_PERF_UCHE_LATENCY_COUNT = 28, 355 }; 356 357 enum a3xx_pc_perfcounter_select { 358 PC_PCPERF_VISIBILITY_STREAMS = 0, 359 PC_PCPERF_TOTAL_INSTANCES = 1, 360 PC_PCPERF_PRIMITIVES_PC_VPC = 2, 361 PC_PCPERF_PRIMITIVES_KILLED_BY_VS = 3, 362 PC_PCPERF_PRIMITIVES_VISIBLE_BY_VS = 4, 363 PC_PCPERF_DRAWCALLS_KILLED_BY_VS = 5, 364 PC_PCPERF_DRAWCALLS_VISIBLE_BY_VS = 6, 365 PC_PCPERF_VERTICES_TO_VFD = 7, 366 PC_PCPERF_REUSED_VERTICES = 8, 367 PC_PCPERF_CYCLES_STALLED_BY_VFD = 9, 368 PC_PCPERF_CYCLES_STALLED_BY_TSE = 10, 369 PC_PCPERF_CYCLES_STALLED_BY_VBIF = 11, 370 PC_PCPERF_CYCLES_IS_WORKING = 12, 371 }; 372 373 enum a3xx_rb_perfcounter_select { 374 RB_RBPERF_ACTIVE_CYCLES_ANY = 0, 375 RB_RBPERF_ACTIVE_CYCLES_ALL = 1, 376 RB_RBPERF_STARVE_CYCLES_BY_SP = 2, 377 RB_RBPERF_STARVE_CYCLES_BY_RAS = 3, 378 RB_RBPERF_STARVE_CYCLES_BY_MARB = 4, 379 RB_RBPERF_STALL_CYCLES_BY_MARB = 5, 380 RB_RBPERF_STALL_CYCLES_BY_HLSQ = 6, 381 RB_RBPERF_RB_MARB_DATA = 7, 382 RB_RBPERF_SP_RB_QUAD = 8, 383 RB_RBPERF_RAS_EARLY_Z_QUADS = 9, 384 RB_RBPERF_GMEM_CH0_READ = 10, 385 RB_RBPERF_GMEM_CH1_READ = 11, 386 RB_RBPERF_GMEM_CH0_WRITE = 12, 387 RB_RBPERF_GMEM_CH1_WRITE = 13, 388 RB_RBPERF_CP_CONTEXT_DONE = 14, 389 RB_RBPERF_CP_CACHE_FLUSH = 15, 390 RB_RBPERF_CP_ZPASS_DONE = 16, 391 }; 392 393 enum a3xx_rbbm_perfcounter_select { 394 RBBM_ALAWYS_ON = 0, 395 RBBM_VBIF_BUSY = 1, 396 RBBM_TSE_BUSY = 2, 397 RBBM_RAS_BUSY = 3, 398 RBBM_PC_DCALL_BUSY = 4, 399 RBBM_PC_VSD_BUSY = 5, 400 RBBM_VFD_BUSY = 6, 401 RBBM_VPC_BUSY = 7, 402 RBBM_UCHE_BUSY = 8, 403 RBBM_VSC_BUSY = 9, 404 RBBM_HLSQ_BUSY = 10, 405 RBBM_ANY_RB_BUSY = 11, 406 RBBM_ANY_TEX_BUSY = 12, 407 RBBM_ANY_USP_BUSY = 13, 408 RBBM_ANY_MARB_BUSY = 14, 409 RBBM_ANY_ARB_BUSY = 15, 410 RBBM_AHB_STATUS_BUSY = 16, 411 RBBM_AHB_STATUS_STALLED = 17, 412 RBBM_AHB_STATUS_TXFR = 18, 413 RBBM_AHB_STATUS_TXFR_SPLIT = 19, 414 RBBM_AHB_STATUS_TXFR_ERROR = 20, 415 RBBM_AHB_STATUS_LONG_STALL = 21, 416 RBBM_RBBM_STATUS_MASKED = 22, 417 }; 418 419 enum a3xx_sp_perfcounter_select { 420 SP_LM_LOAD_INSTRUCTIONS = 0, 421 SP_LM_STORE_INSTRUCTIONS = 1, 422 SP_LM_ATOMICS = 2, 423 SP_UCHE_LOAD_INSTRUCTIONS = 3, 424 SP_UCHE_STORE_INSTRUCTIONS = 4, 425 SP_UCHE_ATOMICS = 5, 426 SP_VS_TEX_INSTRUCTIONS = 6, 427 SP_VS_CFLOW_INSTRUCTIONS = 7, 428 SP_VS_EFU_INSTRUCTIONS = 8, 429 SP_VS_FULL_ALU_INSTRUCTIONS = 9, 430 SP_VS_HALF_ALU_INSTRUCTIONS = 10, 431 SP_FS_TEX_INSTRUCTIONS = 11, 432 SP_FS_CFLOW_INSTRUCTIONS = 12, 433 SP_FS_EFU_INSTRUCTIONS = 13, 434 SP_FS_FULL_ALU_INSTRUCTIONS = 14, 435 SP_FS_HALF_ALU_INSTRUCTIONS = 15, 436 SP_FS_BARY_INSTRUCTIONS = 16, 437 SP_VS_INSTRUCTIONS = 17, 438 SP_FS_INSTRUCTIONS = 18, 439 SP_ADDR_LOCK_COUNT = 19, 440 SP_UCHE_READ_TRANS = 20, 441 SP_UCHE_WRITE_TRANS = 21, 442 SP_EXPORT_VPC_TRANS = 22, 443 SP_EXPORT_RB_TRANS = 23, 444 SP_PIXELS_KILLED = 24, 445 SP_ICL1_REQUESTS = 25, 446 SP_ICL1_MISSES = 26, 447 SP_ICL0_REQUESTS = 27, 448 SP_ICL0_MISSES = 28, 449 SP_ALU_ACTIVE_CYCLES = 29, 450 SP_EFU_ACTIVE_CYCLES = 30, 451 SP_STALL_CYCLES_BY_VPC = 31, 452 SP_STALL_CYCLES_BY_TP = 32, 453 SP_STALL_CYCLES_BY_UCHE = 33, 454 SP_STALL_CYCLES_BY_RB = 34, 455 SP_ACTIVE_CYCLES_ANY = 35, 456 SP_ACTIVE_CYCLES_ALL = 36, 457 }; 458 459 enum a3xx_tp_perfcounter_select { 460 TPL1_TPPERF_L1_REQUESTS = 0, 461 TPL1_TPPERF_TP0_L1_REQUESTS = 1, 462 TPL1_TPPERF_TP0_L1_MISSES = 2, 463 TPL1_TPPERF_TP1_L1_REQUESTS = 3, 464 TPL1_TPPERF_TP1_L1_MISSES = 4, 465 TPL1_TPPERF_TP2_L1_REQUESTS = 5, 466 TPL1_TPPERF_TP2_L1_MISSES = 6, 467 TPL1_TPPERF_TP3_L1_REQUESTS = 7, 468 TPL1_TPPERF_TP3_L1_MISSES = 8, 469 TPL1_TPPERF_OUTPUT_TEXELS_POINT = 9, 470 TPL1_TPPERF_OUTPUT_TEXELS_BILINEAR = 10, 471 TPL1_TPPERF_OUTPUT_TEXELS_MIP = 11, 472 TPL1_TPPERF_OUTPUT_TEXELS_ANISO = 12, 473 TPL1_TPPERF_BILINEAR_OPS = 13, 474 TPL1_TPPERF_QUADSQUADS_OFFSET = 14, 475 TPL1_TPPERF_QUADQUADS_SHADOW = 15, 476 TPL1_TPPERF_QUADS_ARRAY = 16, 477 TPL1_TPPERF_QUADS_PROJECTION = 17, 478 TPL1_TPPERF_QUADS_GRADIENT = 18, 479 TPL1_TPPERF_QUADS_1D2D = 19, 480 TPL1_TPPERF_QUADS_3DCUBE = 20, 481 TPL1_TPPERF_ZERO_LOD = 21, 482 TPL1_TPPERF_OUTPUT_TEXELS = 22, 483 TPL1_TPPERF_ACTIVE_CYCLES_ANY = 23, 484 TPL1_TPPERF_ACTIVE_CYCLES_ALL = 24, 485 TPL1_TPPERF_STALL_CYCLES_BY_ARB = 25, 486 TPL1_TPPERF_LATENCY = 26, 487 TPL1_TPPERF_LATENCY_TRANS = 27, 488 }; 489 490 enum a3xx_vfd_perfcounter_select { 491 VFD_PERF_UCHE_BYTE_FETCHED = 0, 492 VFD_PERF_UCHE_TRANS = 1, 493 VFD_PERF_VPC_BYPASS_COMPONENTS = 2, 494 VFD_PERF_FETCH_INSTRUCTIONS = 3, 495 VFD_PERF_DECODE_INSTRUCTIONS = 4, 496 VFD_PERF_ACTIVE_CYCLES = 5, 497 VFD_PERF_STALL_CYCLES_UCHE = 6, 498 VFD_PERF_STALL_CYCLES_HLSQ = 7, 499 VFD_PERF_STALL_CYCLES_VPC_BYPASS = 8, 500 VFD_PERF_STALL_CYCLES_VPC_ALLOC = 9, 501 }; 502 503 enum a3xx_vpc_perfcounter_select { 504 VPC_PERF_SP_LM_PRIMITIVES = 0, 505 VPC_PERF_COMPONENTS_FROM_SP = 1, 506 VPC_PERF_SP_LM_COMPONENTS = 2, 507 VPC_PERF_ACTIVE_CYCLES = 3, 508 VPC_PERF_STALL_CYCLES_LM = 4, 509 VPC_PERF_STALL_CYCLES_RAS = 5, 510 }; 511 512 enum a3xx_uche_perfcounter_select { 513 UCHE_UCHEPERF_VBIF_READ_BEATS_TP = 0, 514 UCHE_UCHEPERF_VBIF_READ_BEATS_VFD = 1, 515 UCHE_UCHEPERF_VBIF_READ_BEATS_HLSQ = 2, 516 UCHE_UCHEPERF_VBIF_READ_BEATS_MARB = 3, 517 UCHE_UCHEPERF_VBIF_READ_BEATS_SP = 4, 518 UCHE_UCHEPERF_READ_REQUESTS_TP = 8, 519 UCHE_UCHEPERF_READ_REQUESTS_VFD = 9, 520 UCHE_UCHEPERF_READ_REQUESTS_HLSQ = 10, 521 UCHE_UCHEPERF_READ_REQUESTS_MARB = 11, 522 UCHE_UCHEPERF_READ_REQUESTS_SP = 12, 523 UCHE_UCHEPERF_WRITE_REQUESTS_MARB = 13, 524 UCHE_UCHEPERF_WRITE_REQUESTS_SP = 14, 525 UCHE_UCHEPERF_TAG_CHECK_FAILS = 15, 526 UCHE_UCHEPERF_EVICTS = 16, 527 UCHE_UCHEPERF_FLUSHES = 17, 528 UCHE_UCHEPERF_VBIF_LATENCY_CYCLES = 18, 529 UCHE_UCHEPERF_VBIF_LATENCY_SAMPLES = 19, 530 UCHE_UCHEPERF_ACTIVE_CYCLES = 20, 531 }; 532 533 enum a3xx_intp_mode { 534 SMOOTH = 0, 535 FLAT = 1, 536 ZERO = 2, 537 ONE = 3, 538 }; 539 540 enum a3xx_repl_mode { 541 S = 1, 542 T = 2, 543 ONE_T = 3, 544 }; 545 546 enum a3xx_tex_filter { 547 A3XX_TEX_NEAREST = 0, 548 A3XX_TEX_LINEAR = 1, 549 A3XX_TEX_ANISO = 2, 550 }; 551 552 enum a3xx_tex_clamp { 553 A3XX_TEX_REPEAT = 0, 554 A3XX_TEX_CLAMP_TO_EDGE = 1, 555 A3XX_TEX_MIRROR_REPEAT = 2, 556 A3XX_TEX_CLAMP_TO_BORDER = 3, 557 A3XX_TEX_MIRROR_CLAMP = 4, 558 }; 559 560 enum a3xx_tex_aniso { 561 A3XX_TEX_ANISO_1 = 0, 562 A3XX_TEX_ANISO_2 = 1, 563 A3XX_TEX_ANISO_4 = 2, 564 A3XX_TEX_ANISO_8 = 3, 565 A3XX_TEX_ANISO_16 = 4, 566 }; 567 568 enum a3xx_tex_swiz { 569 A3XX_TEX_X = 0, 570 A3XX_TEX_Y = 1, 571 A3XX_TEX_Z = 2, 572 A3XX_TEX_W = 3, 573 A3XX_TEX_ZERO = 4, 574 A3XX_TEX_ONE = 5, 575 }; 576 577 enum a3xx_tex_type { 578 A3XX_TEX_1D = 0, 579 A3XX_TEX_2D = 1, 580 A3XX_TEX_CUBE = 2, 581 A3XX_TEX_3D = 3, 582 }; 583 584 enum a3xx_tex_msaa { 585 A3XX_TPL1_MSAA1X = 0, 586 A3XX_TPL1_MSAA2X = 1, 587 A3XX_TPL1_MSAA4X = 2, 588 A3XX_TPL1_MSAA8X = 3, 589 }; 590 591 #define A3XX_INT0_RBBM_GPU_IDLE 0x00000001 592 #define A3XX_INT0_RBBM_AHB_ERROR 0x00000002 593 #define A3XX_INT0_RBBM_REG_TIMEOUT 0x00000004 594 #define A3XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008 595 #define A3XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010 596 #define A3XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00000020 597 #define A3XX_INT0_VFD_ERROR 0x00000040 598 #define A3XX_INT0_CP_SW_INT 0x00000080 599 #define A3XX_INT0_CP_T0_PACKET_IN_IB 0x00000100 600 #define A3XX_INT0_CP_OPCODE_ERROR 0x00000200 601 #define A3XX_INT0_CP_RESERVED_BIT_ERROR 0x00000400 602 #define A3XX_INT0_CP_HW_FAULT 0x00000800 603 #define A3XX_INT0_CP_DMA 0x00001000 604 #define A3XX_INT0_CP_IB2_INT 0x00002000 605 #define A3XX_INT0_CP_IB1_INT 0x00004000 606 #define A3XX_INT0_CP_RB_INT 0x00008000 607 #define A3XX_INT0_CP_REG_PROTECT_FAULT 0x00010000 608 #define A3XX_INT0_CP_RB_DONE_TS 0x00020000 609 #define A3XX_INT0_CP_VS_DONE_TS 0x00040000 610 #define A3XX_INT0_CP_PS_DONE_TS 0x00080000 611 #define A3XX_INT0_CACHE_FLUSH_TS 0x00100000 612 #define A3XX_INT0_CP_AHB_ERROR_HALT 0x00200000 613 #define A3XX_INT0_MISC_HANG_DETECT 0x01000000 614 #define A3XX_INT0_UCHE_OOB_ACCESS 0x02000000 615 #define REG_A3XX_RBBM_HW_VERSION 0x00000000 616 617 #define REG_A3XX_RBBM_HW_RELEASE 0x00000001 618 619 #define REG_A3XX_RBBM_HW_CONFIGURATION 0x00000002 620 621 #define REG_A3XX_RBBM_CLOCK_CTL 0x00000010 622 623 #define REG_A3XX_RBBM_SP_HYST_CNT 0x00000012 624 625 #define REG_A3XX_RBBM_SW_RESET_CMD 0x00000018 626 627 #define REG_A3XX_RBBM_AHB_CTL0 0x00000020 628 629 #define REG_A3XX_RBBM_AHB_CTL1 0x00000021 630 631 #define REG_A3XX_RBBM_AHB_CMD 0x00000022 632 633 #define REG_A3XX_RBBM_AHB_ERROR_STATUS 0x00000027 634 635 #define REG_A3XX_RBBM_GPR0_CTL 0x0000002e 636 637 #define REG_A3XX_RBBM_STATUS 0x00000030 638 #define A3XX_RBBM_STATUS_HI_BUSY 0x00000001 639 #define A3XX_RBBM_STATUS_CP_ME_BUSY 0x00000002 640 #define A3XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004 641 #define A3XX_RBBM_STATUS_CP_NRT_BUSY 0x00004000 642 #define A3XX_RBBM_STATUS_VBIF_BUSY 0x00008000 643 #define A3XX_RBBM_STATUS_TSE_BUSY 0x00010000 644 #define A3XX_RBBM_STATUS_RAS_BUSY 0x00020000 645 #define A3XX_RBBM_STATUS_RB_BUSY 0x00040000 646 #define A3XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000 647 #define A3XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000 648 #define A3XX_RBBM_STATUS_VFD_BUSY 0x00200000 649 #define A3XX_RBBM_STATUS_VPC_BUSY 0x00400000 650 #define A3XX_RBBM_STATUS_UCHE_BUSY 0x00800000 651 #define A3XX_RBBM_STATUS_SP_BUSY 0x01000000 652 #define A3XX_RBBM_STATUS_TPL1_BUSY 0x02000000 653 #define A3XX_RBBM_STATUS_MARB_BUSY 0x04000000 654 #define A3XX_RBBM_STATUS_VSC_BUSY 0x08000000 655 #define A3XX_RBBM_STATUS_ARB_BUSY 0x10000000 656 #define A3XX_RBBM_STATUS_HLSQ_BUSY 0x20000000 657 #define A3XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000 658 #define A3XX_RBBM_STATUS_GPU_BUSY 0x80000000 659 660 #define REG_A3XX_RBBM_NQWAIT_UNTIL 0x00000040 661 662 #define REG_A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x00000033 663 664 #define REG_A3XX_RBBM_INTERFACE_HANG_INT_CTL 0x00000050 665 666 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL0 0x00000051 667 668 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL1 0x00000054 669 670 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL2 0x00000057 671 672 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL3 0x0000005a 673 674 #define REG_A3XX_RBBM_INT_SET_CMD 0x00000060 675 676 #define REG_A3XX_RBBM_INT_CLEAR_CMD 0x00000061 677 678 #define REG_A3XX_RBBM_INT_0_MASK 0x00000063 679 680 #define REG_A3XX_RBBM_INT_0_STATUS 0x00000064 681 682 #define REG_A3XX_RBBM_PERFCTR_CTL 0x00000080 683 #define A3XX_RBBM_PERFCTR_CTL_ENABLE 0x00000001 684 685 #define REG_A3XX_RBBM_PERFCTR_LOAD_CMD0 0x00000081 686 687 #define REG_A3XX_RBBM_PERFCTR_LOAD_CMD1 0x00000082 688 689 #define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000084 690 691 #define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000085 692 693 #define REG_A3XX_RBBM_PERFCOUNTER0_SELECT 0x00000086 694 695 #define REG_A3XX_RBBM_PERFCOUNTER1_SELECT 0x00000087 696 697 #define REG_A3XX_RBBM_GPU_BUSY_MASKED 0x00000088 698 699 #define REG_A3XX_RBBM_PERFCTR_CP_0_LO 0x00000090 700 701 #define REG_A3XX_RBBM_PERFCTR_CP_0_HI 0x00000091 702 703 #define REG_A3XX_RBBM_PERFCTR_RBBM_0_LO 0x00000092 704 705 #define REG_A3XX_RBBM_PERFCTR_RBBM_0_HI 0x00000093 706 707 #define REG_A3XX_RBBM_PERFCTR_RBBM_1_LO 0x00000094 708 709 #define REG_A3XX_RBBM_PERFCTR_RBBM_1_HI 0x00000095 710 711 #define REG_A3XX_RBBM_PERFCTR_PC_0_LO 0x00000096 712 713 #define REG_A3XX_RBBM_PERFCTR_PC_0_HI 0x00000097 714 715 #define REG_A3XX_RBBM_PERFCTR_PC_1_LO 0x00000098 716 717 #define REG_A3XX_RBBM_PERFCTR_PC_1_HI 0x00000099 718 719 #define REG_A3XX_RBBM_PERFCTR_PC_2_LO 0x0000009a 720 721 #define REG_A3XX_RBBM_PERFCTR_PC_2_HI 0x0000009b 722 723 #define REG_A3XX_RBBM_PERFCTR_PC_3_LO 0x0000009c 724 725 #define REG_A3XX_RBBM_PERFCTR_PC_3_HI 0x0000009d 726 727 #define REG_A3XX_RBBM_PERFCTR_VFD_0_LO 0x0000009e 728 729 #define REG_A3XX_RBBM_PERFCTR_VFD_0_HI 0x0000009f 730 731 #define REG_A3XX_RBBM_PERFCTR_VFD_1_LO 0x000000a0 732 733 #define REG_A3XX_RBBM_PERFCTR_VFD_1_HI 0x000000a1 734 735 #define REG_A3XX_RBBM_PERFCTR_HLSQ_0_LO 0x000000a2 736 737 #define REG_A3XX_RBBM_PERFCTR_HLSQ_0_HI 0x000000a3 738 739 #define REG_A3XX_RBBM_PERFCTR_HLSQ_1_LO 0x000000a4 740 741 #define REG_A3XX_RBBM_PERFCTR_HLSQ_1_HI 0x000000a5 742 743 #define REG_A3XX_RBBM_PERFCTR_HLSQ_2_LO 0x000000a6 744 745 #define REG_A3XX_RBBM_PERFCTR_HLSQ_2_HI 0x000000a7 746 747 #define REG_A3XX_RBBM_PERFCTR_HLSQ_3_LO 0x000000a8 748 749 #define REG_A3XX_RBBM_PERFCTR_HLSQ_3_HI 0x000000a9 750 751 #define REG_A3XX_RBBM_PERFCTR_HLSQ_4_LO 0x000000aa 752 753 #define REG_A3XX_RBBM_PERFCTR_HLSQ_4_HI 0x000000ab 754 755 #define REG_A3XX_RBBM_PERFCTR_HLSQ_5_LO 0x000000ac 756 757 #define REG_A3XX_RBBM_PERFCTR_HLSQ_5_HI 0x000000ad 758 759 #define REG_A3XX_RBBM_PERFCTR_VPC_0_LO 0x000000ae 760 761 #define REG_A3XX_RBBM_PERFCTR_VPC_0_HI 0x000000af 762 763 #define REG_A3XX_RBBM_PERFCTR_VPC_1_LO 0x000000b0 764 765 #define REG_A3XX_RBBM_PERFCTR_VPC_1_HI 0x000000b1 766 767 #define REG_A3XX_RBBM_PERFCTR_TSE_0_LO 0x000000b2 768 769 #define REG_A3XX_RBBM_PERFCTR_TSE_0_HI 0x000000b3 770 771 #define REG_A3XX_RBBM_PERFCTR_TSE_1_LO 0x000000b4 772 773 #define REG_A3XX_RBBM_PERFCTR_TSE_1_HI 0x000000b5 774 775 #define REG_A3XX_RBBM_PERFCTR_RAS_0_LO 0x000000b6 776 777 #define REG_A3XX_RBBM_PERFCTR_RAS_0_HI 0x000000b7 778 779 #define REG_A3XX_RBBM_PERFCTR_RAS_1_LO 0x000000b8 780 781 #define REG_A3XX_RBBM_PERFCTR_RAS_1_HI 0x000000b9 782 783 #define REG_A3XX_RBBM_PERFCTR_UCHE_0_LO 0x000000ba 784 785 #define REG_A3XX_RBBM_PERFCTR_UCHE_0_HI 0x000000bb 786 787 #define REG_A3XX_RBBM_PERFCTR_UCHE_1_LO 0x000000bc 788 789 #define REG_A3XX_RBBM_PERFCTR_UCHE_1_HI 0x000000bd 790 791 #define REG_A3XX_RBBM_PERFCTR_UCHE_2_LO 0x000000be 792 793 #define REG_A3XX_RBBM_PERFCTR_UCHE_2_HI 0x000000bf 794 795 #define REG_A3XX_RBBM_PERFCTR_UCHE_3_LO 0x000000c0 796 797 #define REG_A3XX_RBBM_PERFCTR_UCHE_3_HI 0x000000c1 798 799 #define REG_A3XX_RBBM_PERFCTR_UCHE_4_LO 0x000000c2 800 801 #define REG_A3XX_RBBM_PERFCTR_UCHE_4_HI 0x000000c3 802 803 #define REG_A3XX_RBBM_PERFCTR_UCHE_5_LO 0x000000c4 804 805 #define REG_A3XX_RBBM_PERFCTR_UCHE_5_HI 0x000000c5 806 807 #define REG_A3XX_RBBM_PERFCTR_TP_0_LO 0x000000c6 808 809 #define REG_A3XX_RBBM_PERFCTR_TP_0_HI 0x000000c7 810 811 #define REG_A3XX_RBBM_PERFCTR_TP_1_LO 0x000000c8 812 813 #define REG_A3XX_RBBM_PERFCTR_TP_1_HI 0x000000c9 814 815 #define REG_A3XX_RBBM_PERFCTR_TP_2_LO 0x000000ca 816 817 #define REG_A3XX_RBBM_PERFCTR_TP_2_HI 0x000000cb 818 819 #define REG_A3XX_RBBM_PERFCTR_TP_3_LO 0x000000cc 820 821 #define REG_A3XX_RBBM_PERFCTR_TP_3_HI 0x000000cd 822 823 #define REG_A3XX_RBBM_PERFCTR_TP_4_LO 0x000000ce 824 825 #define REG_A3XX_RBBM_PERFCTR_TP_4_HI 0x000000cf 826 827 #define REG_A3XX_RBBM_PERFCTR_TP_5_LO 0x000000d0 828 829 #define REG_A3XX_RBBM_PERFCTR_TP_5_HI 0x000000d1 830 831 #define REG_A3XX_RBBM_PERFCTR_SP_0_LO 0x000000d2 832 833 #define REG_A3XX_RBBM_PERFCTR_SP_0_HI 0x000000d3 834 835 #define REG_A3XX_RBBM_PERFCTR_SP_1_LO 0x000000d4 836 837 #define REG_A3XX_RBBM_PERFCTR_SP_1_HI 0x000000d5 838 839 #define REG_A3XX_RBBM_PERFCTR_SP_2_LO 0x000000d6 840 841 #define REG_A3XX_RBBM_PERFCTR_SP_2_HI 0x000000d7 842 843 #define REG_A3XX_RBBM_PERFCTR_SP_3_LO 0x000000d8 844 845 #define REG_A3XX_RBBM_PERFCTR_SP_3_HI 0x000000d9 846 847 #define REG_A3XX_RBBM_PERFCTR_SP_4_LO 0x000000da 848 849 #define REG_A3XX_RBBM_PERFCTR_SP_4_HI 0x000000db 850 851 #define REG_A3XX_RBBM_PERFCTR_SP_5_LO 0x000000dc 852 853 #define REG_A3XX_RBBM_PERFCTR_SP_5_HI 0x000000dd 854 855 #define REG_A3XX_RBBM_PERFCTR_SP_6_LO 0x000000de 856 857 #define REG_A3XX_RBBM_PERFCTR_SP_6_HI 0x000000df 858 859 #define REG_A3XX_RBBM_PERFCTR_SP_7_LO 0x000000e0 860 861 #define REG_A3XX_RBBM_PERFCTR_SP_7_HI 0x000000e1 862 863 #define REG_A3XX_RBBM_PERFCTR_RB_0_LO 0x000000e2 864 865 #define REG_A3XX_RBBM_PERFCTR_RB_0_HI 0x000000e3 866 867 #define REG_A3XX_RBBM_PERFCTR_RB_1_LO 0x000000e4 868 869 #define REG_A3XX_RBBM_PERFCTR_RB_1_HI 0x000000e5 870 871 #define REG_A3XX_RBBM_PERFCTR_PWR_0_LO 0x000000ea 872 873 #define REG_A3XX_RBBM_PERFCTR_PWR_0_HI 0x000000eb 874 875 #define REG_A3XX_RBBM_PERFCTR_PWR_1_LO 0x000000ec 876 877 #define REG_A3XX_RBBM_PERFCTR_PWR_1_HI 0x000000ed 878 879 #define REG_A3XX_RBBM_RBBM_CTL 0x00000100 880 881 #define REG_A3XX_RBBM_DEBUG_BUS_CTL 0x00000111 882 883 #define REG_A3XX_RBBM_DEBUG_BUS_DATA_STATUS 0x00000112 884 885 #define REG_A3XX_CP_PFP_UCODE_ADDR 0x000001c9 886 887 #define REG_A3XX_CP_PFP_UCODE_DATA 0x000001ca 888 889 #define REG_A3XX_CP_ROQ_ADDR 0x000001cc 890 891 #define REG_A3XX_CP_ROQ_DATA 0x000001cd 892 893 #define REG_A3XX_CP_MERCIU_ADDR 0x000001d1 894 895 #define REG_A3XX_CP_MERCIU_DATA 0x000001d2 896 897 #define REG_A3XX_CP_MERCIU_DATA2 0x000001d3 898 899 #define REG_A3XX_CP_MEQ_ADDR 0x000001da 900 901 #define REG_A3XX_CP_MEQ_DATA 0x000001db 902 903 #define REG_A3XX_CP_WFI_PEND_CTR 0x000001f5 904 905 #define REG_A3XX_RBBM_PM_OVERRIDE2 0x0000039d 906 907 #define REG_A3XX_CP_PERFCOUNTER_SELECT 0x00000445 908 909 #define REG_A3XX_CP_HW_FAULT 0x0000045c 910 911 #define REG_A3XX_CP_PROTECT_CTRL 0x0000045e 912 913 #define REG_A3XX_CP_PROTECT_STATUS 0x0000045f 914 915 static inline uint32_t REG_A3XX_CP_PROTECT(uint32_t i0) { return 0x00000460 + 0x1*i0; } 916 917 static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000460 + 0x1*i0; } 918 919 #define REG_A3XX_CP_AHB_FAULT 0x0000054d 920 921 #define REG_A3XX_SQ_GPR_MANAGEMENT 0x00000d00 922 923 #define REG_A3XX_SQ_INST_STORE_MANAGMENT 0x00000d02 924 925 #define REG_A3XX_TP0_CHICKEN 0x00000e1e 926 927 #define REG_A3XX_SP_GLOBAL_MEM_SIZE 0x00000e22 928 929 #define REG_A3XX_SP_GLOBAL_MEM_ADDR 0x00000e23 930 931 #define REG_A3XX_GRAS_CL_CLIP_CNTL 0x00002040 932 #define A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER 0x00001000 933 #define A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE 0x00010000 934 #define A3XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE 0x00020000 935 #define A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE 0x00080000 936 #define A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE 0x00100000 937 #define A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE 0x00200000 938 #define A3XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z 0x00400000 939 #define A3XX_GRAS_CL_CLIP_CNTL_ZCOORD 0x00800000 940 #define A3XX_GRAS_CL_CLIP_CNTL_WCOORD 0x01000000 941 #define A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE 0x02000000 942 #define A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__MASK 0x1c000000 943 #define A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__SHIFT 26 944 static inline uint32_t A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(uint32_t val) 945 { 946 return ((val) << A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__SHIFT) & A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__MASK; 947 } 948 949 #define REG_A3XX_GRAS_CL_GB_CLIP_ADJ 0x00002044 950 #define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff 951 #define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT 0 952 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) 953 { 954 return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK; 955 } 956 #define A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK 0x000ffc00 957 #define A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT 10 958 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) 959 { 960 return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK; 961 } 962 963 #define REG_A3XX_GRAS_CL_VPORT_XOFFSET 0x00002048 964 #define A3XX_GRAS_CL_VPORT_XOFFSET__MASK 0xffffffff 965 #define A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT 0 966 static inline uint32_t A3XX_GRAS_CL_VPORT_XOFFSET(float val) 967 { 968 return ((fui(val)) << A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_XOFFSET__MASK; 969 } 970 971 #define REG_A3XX_GRAS_CL_VPORT_XSCALE 0x00002049 972 #define A3XX_GRAS_CL_VPORT_XSCALE__MASK 0xffffffff 973 #define A3XX_GRAS_CL_VPORT_XSCALE__SHIFT 0 974 static inline uint32_t A3XX_GRAS_CL_VPORT_XSCALE(float val) 975 { 976 return ((fui(val)) << A3XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_XSCALE__MASK; 977 } 978 979 #define REG_A3XX_GRAS_CL_VPORT_YOFFSET 0x0000204a 980 #define A3XX_GRAS_CL_VPORT_YOFFSET__MASK 0xffffffff 981 #define A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT 0 982 static inline uint32_t A3XX_GRAS_CL_VPORT_YOFFSET(float val) 983 { 984 return ((fui(val)) << A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_YOFFSET__MASK; 985 } 986 987 #define REG_A3XX_GRAS_CL_VPORT_YSCALE 0x0000204b 988 #define A3XX_GRAS_CL_VPORT_YSCALE__MASK 0xffffffff 989 #define A3XX_GRAS_CL_VPORT_YSCALE__SHIFT 0 990 static inline uint32_t A3XX_GRAS_CL_VPORT_YSCALE(float val) 991 { 992 return ((fui(val)) << A3XX_GRAS_CL_VPORT_YSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_YSCALE__MASK; 993 } 994 995 #define REG_A3XX_GRAS_CL_VPORT_ZOFFSET 0x0000204c 996 #define A3XX_GRAS_CL_VPORT_ZOFFSET__MASK 0xffffffff 997 #define A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT 0 998 static inline uint32_t A3XX_GRAS_CL_VPORT_ZOFFSET(float val) 999 { 1000 return ((fui(val)) << A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_ZOFFSET__MASK; 1001 } 1002 1003 #define REG_A3XX_GRAS_CL_VPORT_ZSCALE 0x0000204d 1004 #define A3XX_GRAS_CL_VPORT_ZSCALE__MASK 0xffffffff 1005 #define A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT 0 1006 static inline uint32_t A3XX_GRAS_CL_VPORT_ZSCALE(float val) 1007 { 1008 return ((fui(val)) << A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_ZSCALE__MASK; 1009 } 1010 1011 #define REG_A3XX_GRAS_SU_POINT_MINMAX 0x00002068 1012 #define A3XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff 1013 #define A3XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0 1014 static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MIN(float val) 1015 { 1016 return ((((uint32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A3XX_GRAS_SU_POINT_MINMAX_MIN__MASK; 1017 } 1018 #define A3XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000 1019 #define A3XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16 1020 static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MAX(float val) 1021 { 1022 return ((((uint32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A3XX_GRAS_SU_POINT_MINMAX_MAX__MASK; 1023 } 1024 1025 #define REG_A3XX_GRAS_SU_POINT_SIZE 0x00002069 1026 #define A3XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff 1027 #define A3XX_GRAS_SU_POINT_SIZE__SHIFT 0 1028 static inline uint32_t A3XX_GRAS_SU_POINT_SIZE(float val) 1029 { 1030 return ((((int32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_SIZE__SHIFT) & A3XX_GRAS_SU_POINT_SIZE__MASK; 1031 } 1032 1033 #define REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE 0x0000206c 1034 #define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK 0x00ffffff 1035 #define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT 0 1036 static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL(float val) 1037 { 1038 return ((((int32_t)(val * 1048576.0))) << A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK; 1039 } 1040 1041 #define REG_A3XX_GRAS_SU_POLY_OFFSET_OFFSET 0x0000206d 1042 #define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff 1043 #define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0 1044 static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) 1045 { 1046 return ((((int32_t)(val * 64.0))) << A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; 1047 } 1048 1049 #define REG_A3XX_GRAS_SU_MODE_CONTROL 0x00002070 1050 #define A3XX_GRAS_SU_MODE_CONTROL_CULL_FRONT 0x00000001 1051 #define A3XX_GRAS_SU_MODE_CONTROL_CULL_BACK 0x00000002 1052 #define A3XX_GRAS_SU_MODE_CONTROL_FRONT_CW 0x00000004 1053 #define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007f8 1054 #define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 3 1055 static inline uint32_t A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val) 1056 { 1057 return ((((int32_t)(val * 4.0))) << A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK; 1058 } 1059 #define A3XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800 1060 1061 #define REG_A3XX_GRAS_SC_CONTROL 0x00002072 1062 #define A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK 0x000000f0 1063 #define A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT 4 1064 static inline uint32_t A3XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val) 1065 { 1066 return ((val) << A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK; 1067 } 1068 #define A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK 0x00000f00 1069 #define A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT 8 1070 static inline uint32_t A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(enum a3xx_msaa_samples val) 1071 { 1072 return ((val) << A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK; 1073 } 1074 #define A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK 0x0000f000 1075 #define A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT 12 1076 static inline uint32_t A3XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val) 1077 { 1078 return ((val) << A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK; 1079 } 1080 1081 #define REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL 0x00002074 1082 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 1083 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff 1084 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 1085 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val) 1086 { 1087 return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK; 1088 } 1089 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000 1090 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 1091 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) 1092 { 1093 return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK; 1094 } 1095 1096 #define REG_A3XX_GRAS_SC_SCREEN_SCISSOR_BR 0x00002075 1097 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 1098 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff 1099 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 1100 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val) 1101 { 1102 return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK; 1103 } 1104 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000 1105 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 1106 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) 1107 { 1108 return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK; 1109 } 1110 1111 #define REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL 0x00002079 1112 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 1113 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff 1114 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 1115 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 1116 { 1117 return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; 1118 } 1119 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 1120 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 1121 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 1122 { 1123 return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; 1124 } 1125 1126 #define REG_A3XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000207a 1127 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 1128 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff 1129 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 1130 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 1131 { 1132 return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; 1133 } 1134 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 1135 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 1136 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 1137 { 1138 return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; 1139 } 1140 1141 #define REG_A3XX_RB_MODE_CONTROL 0x000020c0 1142 #define A3XX_RB_MODE_CONTROL_GMEM_BYPASS 0x00000080 1143 #define A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK 0x00000700 1144 #define A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT 8 1145 static inline uint32_t A3XX_RB_MODE_CONTROL_RENDER_MODE(enum a3xx_render_mode val) 1146 { 1147 return ((val) << A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT) & A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK; 1148 } 1149 #define A3XX_RB_MODE_CONTROL_MRT__MASK 0x00003000 1150 #define A3XX_RB_MODE_CONTROL_MRT__SHIFT 12 1151 static inline uint32_t A3XX_RB_MODE_CONTROL_MRT(uint32_t val) 1152 { 1153 return ((val) << A3XX_RB_MODE_CONTROL_MRT__SHIFT) & A3XX_RB_MODE_CONTROL_MRT__MASK; 1154 } 1155 #define A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE 0x00008000 1156 #define A3XX_RB_MODE_CONTROL_PACKER_TIMER_ENABLE 0x00010000 1157 1158 #define REG_A3XX_RB_RENDER_CONTROL 0x000020c1 1159 #define A3XX_RB_RENDER_CONTROL_DUAL_COLOR_IN_ENABLE 0x00000001 1160 #define A3XX_RB_RENDER_CONTROL_YUV_IN_ENABLE 0x00000002 1161 #define A3XX_RB_RENDER_CONTROL_COV_VALUE_INPUT_ENABLE 0x00000004 1162 #define A3XX_RB_RENDER_CONTROL_FACENESS 0x00000008 1163 #define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK 0x00000ff0 1164 #define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT 4 1165 static inline uint32_t A3XX_RB_RENDER_CONTROL_BIN_WIDTH(uint32_t val) 1166 { 1167 assert(!(val & 0x1f)); 1168 return ((val >> 5) << A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT) & A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK; 1169 } 1170 #define A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00001000 1171 #define A3XX_RB_RENDER_CONTROL_ENABLE_GMEM 0x00002000 1172 #define A3XX_RB_RENDER_CONTROL_XCOORD 0x00004000 1173 #define A3XX_RB_RENDER_CONTROL_YCOORD 0x00008000 1174 #define A3XX_RB_RENDER_CONTROL_ZCOORD 0x00010000 1175 #define A3XX_RB_RENDER_CONTROL_WCOORD 0x00020000 1176 #define A3XX_RB_RENDER_CONTROL_I_CLAMP_ENABLE 0x00080000 1177 #define A3XX_RB_RENDER_CONTROL_COV_VALUE_OUTPUT_ENABLE 0x00100000 1178 #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST 0x00400000 1179 #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK 0x07000000 1180 #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT 24 1181 static inline uint32_t A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) 1182 { 1183 return ((val) << A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK; 1184 } 1185 #define A3XX_RB_RENDER_CONTROL_ALPHA_TO_COVERAGE 0x40000000 1186 #define A3XX_RB_RENDER_CONTROL_ALPHA_TO_ONE 0x80000000 1187 1188 #define REG_A3XX_RB_MSAA_CONTROL 0x000020c2 1189 #define A3XX_RB_MSAA_CONTROL_DISABLE 0x00000400 1190 #define A3XX_RB_MSAA_CONTROL_SAMPLES__MASK 0x0000f000 1191 #define A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT 12 1192 static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLES(enum a3xx_msaa_samples val) 1193 { 1194 return ((val) << A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A3XX_RB_MSAA_CONTROL_SAMPLES__MASK; 1195 } 1196 #define A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK 0xffff0000 1197 #define A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT 16 1198 static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(uint32_t val) 1199 { 1200 return ((val) << A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT) & A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK; 1201 } 1202 1203 #define REG_A3XX_RB_ALPHA_REF 0x000020c3 1204 #define A3XX_RB_ALPHA_REF_UINT__MASK 0x0000ff00 1205 #define A3XX_RB_ALPHA_REF_UINT__SHIFT 8 1206 static inline uint32_t A3XX_RB_ALPHA_REF_UINT(uint32_t val) 1207 { 1208 return ((val) << A3XX_RB_ALPHA_REF_UINT__SHIFT) & A3XX_RB_ALPHA_REF_UINT__MASK; 1209 } 1210 #define A3XX_RB_ALPHA_REF_FLOAT__MASK 0xffff0000 1211 #define A3XX_RB_ALPHA_REF_FLOAT__SHIFT 16 1212 static inline uint32_t A3XX_RB_ALPHA_REF_FLOAT(float val) 1213 { 1214 return ((util_float_to_half(val)) << A3XX_RB_ALPHA_REF_FLOAT__SHIFT) & A3XX_RB_ALPHA_REF_FLOAT__MASK; 1215 } 1216 1217 static inline uint32_t REG_A3XX_RB_MRT(uint32_t i0) { return 0x000020c4 + 0x4*i0; } 1218 1219 static inline uint32_t REG_A3XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020c4 + 0x4*i0; } 1220 #define A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008 1221 #define A3XX_RB_MRT_CONTROL_BLEND 0x00000010 1222 #define A3XX_RB_MRT_CONTROL_BLEND2 0x00000020 1223 #define A3XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000f00 1224 #define A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 8 1225 static inline uint32_t A3XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) 1226 { 1227 return ((val) << A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A3XX_RB_MRT_CONTROL_ROP_CODE__MASK; 1228 } 1229 #define A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK 0x00003000 1230 #define A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT 12 1231 static inline uint32_t A3XX_RB_MRT_CONTROL_DITHER_MODE(enum adreno_rb_dither_mode val) 1232 { 1233 return ((val) << A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT) & A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK; 1234 } 1235 #define A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x0f000000 1236 #define A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 24 1237 static inline uint32_t A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) 1238 { 1239 return ((val) << A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; 1240 } 1241 1242 static inline uint32_t REG_A3XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020c5 + 0x4*i0; } 1243 #define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x0000003f 1244 #define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 1245 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a3xx_color_fmt val) 1246 { 1247 return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; 1248 } 1249 #define A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x000000c0 1250 #define A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 6 1251 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a3xx_tile_mode val) 1252 { 1253 return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; 1254 } 1255 #define A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00000c00 1256 #define A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 10 1257 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) 1258 { 1259 return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; 1260 } 1261 #define A3XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00004000 1262 #define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK 0xfffe0000 1263 #define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 17 1264 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val) 1265 { 1266 assert(!(val & 0x1f)); 1267 return ((val >> 5) << A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK; 1268 } 1269 1270 static inline uint32_t REG_A3XX_RB_MRT_BUF_BASE(uint32_t i0) { return 0x000020c6 + 0x4*i0; } 1271 #define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK 0xfffffff0 1272 #define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT 4 1273 static inline uint32_t A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(uint32_t val) 1274 { 1275 assert(!(val & 0x1f)); 1276 return ((val >> 5) << A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT) & A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK; 1277 } 1278 1279 static inline uint32_t REG_A3XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020c7 + 0x4*i0; } 1280 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f 1281 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0 1282 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) 1283 { 1284 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; 1285 } 1286 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0 1287 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5 1288 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 1289 { 1290 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; 1291 } 1292 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00 1293 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8 1294 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) 1295 { 1296 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; 1297 } 1298 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000 1299 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16 1300 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) 1301 { 1302 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; 1303 } 1304 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000 1305 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21 1306 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 1307 { 1308 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; 1309 } 1310 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000 1311 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24 1312 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) 1313 { 1314 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; 1315 } 1316 #define A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE 0x20000000 1317 1318 #define REG_A3XX_RB_BLEND_RED 0x000020e4 1319 #define A3XX_RB_BLEND_RED_UINT__MASK 0x000000ff 1320 #define A3XX_RB_BLEND_RED_UINT__SHIFT 0 1321 static inline uint32_t A3XX_RB_BLEND_RED_UINT(uint32_t val) 1322 { 1323 return ((val) << A3XX_RB_BLEND_RED_UINT__SHIFT) & A3XX_RB_BLEND_RED_UINT__MASK; 1324 } 1325 #define A3XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000 1326 #define A3XX_RB_BLEND_RED_FLOAT__SHIFT 16 1327 static inline uint32_t A3XX_RB_BLEND_RED_FLOAT(float val) 1328 { 1329 return ((util_float_to_half(val)) << A3XX_RB_BLEND_RED_FLOAT__SHIFT) & A3XX_RB_BLEND_RED_FLOAT__MASK; 1330 } 1331 1332 #define REG_A3XX_RB_BLEND_GREEN 0x000020e5 1333 #define A3XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff 1334 #define A3XX_RB_BLEND_GREEN_UINT__SHIFT 0 1335 static inline uint32_t A3XX_RB_BLEND_GREEN_UINT(uint32_t val) 1336 { 1337 return ((val) << A3XX_RB_BLEND_GREEN_UINT__SHIFT) & A3XX_RB_BLEND_GREEN_UINT__MASK; 1338 } 1339 #define A3XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000 1340 #define A3XX_RB_BLEND_GREEN_FLOAT__SHIFT 16 1341 static inline uint32_t A3XX_RB_BLEND_GREEN_FLOAT(float val) 1342 { 1343 return ((util_float_to_half(val)) << A3XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A3XX_RB_BLEND_GREEN_FLOAT__MASK; 1344 } 1345 1346 #define REG_A3XX_RB_BLEND_BLUE 0x000020e6 1347 #define A3XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff 1348 #define A3XX_RB_BLEND_BLUE_UINT__SHIFT 0 1349 static inline uint32_t A3XX_RB_BLEND_BLUE_UINT(uint32_t val) 1350 { 1351 return ((val) << A3XX_RB_BLEND_BLUE_UINT__SHIFT) & A3XX_RB_BLEND_BLUE_UINT__MASK; 1352 } 1353 #define A3XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000 1354 #define A3XX_RB_BLEND_BLUE_FLOAT__SHIFT 16 1355 static inline uint32_t A3XX_RB_BLEND_BLUE_FLOAT(float val) 1356 { 1357 return ((util_float_to_half(val)) << A3XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A3XX_RB_BLEND_BLUE_FLOAT__MASK; 1358 } 1359 1360 #define REG_A3XX_RB_BLEND_ALPHA 0x000020e7 1361 #define A3XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff 1362 #define A3XX_RB_BLEND_ALPHA_UINT__SHIFT 0 1363 static inline uint32_t A3XX_RB_BLEND_ALPHA_UINT(uint32_t val) 1364 { 1365 return ((val) << A3XX_RB_BLEND_ALPHA_UINT__SHIFT) & A3XX_RB_BLEND_ALPHA_UINT__MASK; 1366 } 1367 #define A3XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000 1368 #define A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16 1369 static inline uint32_t A3XX_RB_BLEND_ALPHA_FLOAT(float val) 1370 { 1371 return ((util_float_to_half(val)) << A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A3XX_RB_BLEND_ALPHA_FLOAT__MASK; 1372 } 1373 1374 #define REG_A3XX_RB_CLEAR_COLOR_DW0 0x000020e8 1375 1376 #define REG_A3XX_RB_CLEAR_COLOR_DW1 0x000020e9 1377 1378 #define REG_A3XX_RB_CLEAR_COLOR_DW2 0x000020ea 1379 1380 #define REG_A3XX_RB_CLEAR_COLOR_DW3 0x000020eb 1381 1382 #define REG_A3XX_RB_COPY_CONTROL 0x000020ec 1383 #define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK 0x00000003 1384 #define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT 0 1385 static inline uint32_t A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val) 1386 { 1387 return ((val) << A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK; 1388 } 1389 #define A3XX_RB_COPY_CONTROL_DEPTHCLEAR 0x00000008 1390 #define A3XX_RB_COPY_CONTROL_MODE__MASK 0x00000070 1391 #define A3XX_RB_COPY_CONTROL_MODE__SHIFT 4 1392 static inline uint32_t A3XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val) 1393 { 1394 return ((val) << A3XX_RB_COPY_CONTROL_MODE__SHIFT) & A3XX_RB_COPY_CONTROL_MODE__MASK; 1395 } 1396 #define A3XX_RB_COPY_CONTROL_MSAA_SRGB_DOWNSAMPLE 0x00000080 1397 #define A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK 0x00000f00 1398 #define A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT 8 1399 static inline uint32_t A3XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val) 1400 { 1401 return ((val) << A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK; 1402 } 1403 #define A3XX_RB_COPY_CONTROL_DEPTH32_RESOLVE 0x00001000 1404 #define A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xffffc000 1405 #define A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14 1406 static inline uint32_t A3XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) 1407 { 1408 assert(!(val & 0x3fff)); 1409 return ((val >> 14) << A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK; 1410 } 1411 1412 #define REG_A3XX_RB_COPY_DEST_BASE 0x000020ed 1413 #define A3XX_RB_COPY_DEST_BASE_BASE__MASK 0xfffffff0 1414 #define A3XX_RB_COPY_DEST_BASE_BASE__SHIFT 4 1415 static inline uint32_t A3XX_RB_COPY_DEST_BASE_BASE(uint32_t val) 1416 { 1417 assert(!(val & 0x1f)); 1418 return ((val >> 5) << A3XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A3XX_RB_COPY_DEST_BASE_BASE__MASK; 1419 } 1420 1421 #define REG_A3XX_RB_COPY_DEST_PITCH 0x000020ee 1422 #define A3XX_RB_COPY_DEST_PITCH_PITCH__MASK 0xffffffff 1423 #define A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT 0 1424 static inline uint32_t A3XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val) 1425 { 1426 assert(!(val & 0x1f)); 1427 return ((val >> 5) << A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A3XX_RB_COPY_DEST_PITCH_PITCH__MASK; 1428 } 1429 1430 #define REG_A3XX_RB_COPY_DEST_INFO 0x000020ef 1431 #define A3XX_RB_COPY_DEST_INFO_TILE__MASK 0x00000003 1432 #define A3XX_RB_COPY_DEST_INFO_TILE__SHIFT 0 1433 static inline uint32_t A3XX_RB_COPY_DEST_INFO_TILE(enum a3xx_tile_mode val) 1434 { 1435 return ((val) << A3XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A3XX_RB_COPY_DEST_INFO_TILE__MASK; 1436 } 1437 #define A3XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000fc 1438 #define A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 2 1439 static inline uint32_t A3XX_RB_COPY_DEST_INFO_FORMAT(enum a3xx_color_fmt val) 1440 { 1441 return ((val) << A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A3XX_RB_COPY_DEST_INFO_FORMAT__MASK; 1442 } 1443 #define A3XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300 1444 #define A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8 1445 static inline uint32_t A3XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val) 1446 { 1447 return ((val) << A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A3XX_RB_COPY_DEST_INFO_SWAP__MASK; 1448 } 1449 #define A3XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00 1450 #define A3XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10 1451 static inline uint32_t A3XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) 1452 { 1453 return ((val) << A3XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A3XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK; 1454 } 1455 #define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK 0x0003c000 1456 #define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT 14 1457 static inline uint32_t A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val) 1458 { 1459 return ((val) << A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK; 1460 } 1461 #define A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK 0x001c0000 1462 #define A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT 18 1463 static inline uint32_t A3XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val) 1464 { 1465 return ((val) << A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK; 1466 } 1467 1468 #define REG_A3XX_RB_DEPTH_CONTROL 0x00002100 1469 #define A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z 0x00000001 1470 #define A3XX_RB_DEPTH_CONTROL_Z_ENABLE 0x00000002 1471 #define A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004 1472 #define A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00000008 1473 #define A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070 1474 #define A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT 4 1475 static inline uint32_t A3XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val) 1476 { 1477 return ((val) << A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK; 1478 } 1479 #define A3XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE 0x00000080 1480 #define A3XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000 1481 1482 #define REG_A3XX_RB_DEPTH_CLEAR 0x00002101 1483 1484 #define REG_A3XX_RB_DEPTH_INFO 0x00002102 1485 #define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000003 1486 #define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0 1487 static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val) 1488 { 1489 return ((val) << A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; 1490 } 1491 #define A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff800 1492 #define A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 11 1493 static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) 1494 { 1495 assert(!(val & 0xfff)); 1496 return ((val >> 12) << A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; 1497 } 1498 1499 #define REG_A3XX_RB_DEPTH_PITCH 0x00002103 1500 #define A3XX_RB_DEPTH_PITCH__MASK 0xffffffff 1501 #define A3XX_RB_DEPTH_PITCH__SHIFT 0 1502 static inline uint32_t A3XX_RB_DEPTH_PITCH(uint32_t val) 1503 { 1504 assert(!(val & 0x7)); 1505 return ((val >> 3) << A3XX_RB_DEPTH_PITCH__SHIFT) & A3XX_RB_DEPTH_PITCH__MASK; 1506 } 1507 1508 #define REG_A3XX_RB_STENCIL_CONTROL 0x00002104 1509 #define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001 1510 #define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002 1511 #define A3XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004 1512 #define A3XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700 1513 #define A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8 1514 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) 1515 { 1516 return ((val) << A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A3XX_RB_STENCIL_CONTROL_FUNC__MASK; 1517 } 1518 #define A3XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800 1519 #define A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11 1520 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) 1521 { 1522 return ((val) << A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A3XX_RB_STENCIL_CONTROL_FAIL__MASK; 1523 } 1524 #define A3XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000 1525 #define A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14 1526 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) 1527 { 1528 return ((val) << A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZPASS__MASK; 1529 } 1530 #define A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000 1531 #define A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17 1532 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) 1533 { 1534 return ((val) << A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK; 1535 } 1536 #define A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000 1537 #define A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20 1538 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) 1539 { 1540 return ((val) << A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; 1541 } 1542 #define A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000 1543 #define A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23 1544 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) 1545 { 1546 return ((val) << A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; 1547 } 1548 #define A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000 1549 #define A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26 1550 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) 1551 { 1552 return ((val) << A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; 1553 } 1554 #define A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000 1555 #define A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29 1556 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) 1557 { 1558 return ((val) << A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; 1559 } 1560 1561 #define REG_A3XX_RB_STENCIL_CLEAR 0x00002105 1562 1563 #define REG_A3XX_RB_STENCIL_INFO 0x00002106 1564 #define A3XX_RB_STENCIL_INFO_STENCIL_BASE__MASK 0xfffff800 1565 #define A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT 11 1566 static inline uint32_t A3XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val) 1567 { 1568 assert(!(val & 0xfff)); 1569 return ((val >> 12) << A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A3XX_RB_STENCIL_INFO_STENCIL_BASE__MASK; 1570 } 1571 1572 #define REG_A3XX_RB_STENCIL_PITCH 0x00002107 1573 #define A3XX_RB_STENCIL_PITCH__MASK 0xffffffff 1574 #define A3XX_RB_STENCIL_PITCH__SHIFT 0 1575 static inline uint32_t A3XX_RB_STENCIL_PITCH(uint32_t val) 1576 { 1577 assert(!(val & 0x7)); 1578 return ((val >> 3) << A3XX_RB_STENCIL_PITCH__SHIFT) & A3XX_RB_STENCIL_PITCH__MASK; 1579 } 1580 1581 #define REG_A3XX_RB_STENCILREFMASK 0x00002108 1582 #define A3XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff 1583 #define A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 1584 static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) 1585 { 1586 return ((val) << A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILREF__MASK; 1587 } 1588 #define A3XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 1589 #define A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 1590 static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) 1591 { 1592 return ((val) << A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILMASK__MASK; 1593 } 1594 #define A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 1595 #define A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 1596 static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) 1597 { 1598 return ((val) << A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; 1599 } 1600 1601 #define REG_A3XX_RB_STENCILREFMASK_BF 0x00002109 1602 #define A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff 1603 #define A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0 1604 static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) 1605 { 1606 return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; 1607 } 1608 #define A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00 1609 #define A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8 1610 static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) 1611 { 1612 return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; 1613 } 1614 #define A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000 1615 #define A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16 1616 static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) 1617 { 1618 return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; 1619 } 1620 1621 #define REG_A3XX_RB_LRZ_VSC_CONTROL 0x0000210c 1622 #define A3XX_RB_LRZ_VSC_CONTROL_BINNING_ENABLE 0x00000002 1623 1624 #define REG_A3XX_RB_WINDOW_OFFSET 0x0000210e 1625 #define A3XX_RB_WINDOW_OFFSET_X__MASK 0x0000ffff 1626 #define A3XX_RB_WINDOW_OFFSET_X__SHIFT 0 1627 static inline uint32_t A3XX_RB_WINDOW_OFFSET_X(uint32_t val) 1628 { 1629 return ((val) << A3XX_RB_WINDOW_OFFSET_X__SHIFT) & A3XX_RB_WINDOW_OFFSET_X__MASK; 1630 } 1631 #define A3XX_RB_WINDOW_OFFSET_Y__MASK 0xffff0000 1632 #define A3XX_RB_WINDOW_OFFSET_Y__SHIFT 16 1633 static inline uint32_t A3XX_RB_WINDOW_OFFSET_Y(uint32_t val) 1634 { 1635 return ((val) << A3XX_RB_WINDOW_OFFSET_Y__SHIFT) & A3XX_RB_WINDOW_OFFSET_Y__MASK; 1636 } 1637 1638 #define REG_A3XX_RB_SAMPLE_COUNT_CONTROL 0x00002110 1639 #define A3XX_RB_SAMPLE_COUNT_CONTROL_RESET 0x00000001 1640 #define A3XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002 1641 1642 #define REG_A3XX_RB_SAMPLE_COUNT_ADDR 0x00002111 1643 1644 #define REG_A3XX_RB_Z_CLAMP_MIN 0x00002114 1645 1646 #define REG_A3XX_RB_Z_CLAMP_MAX 0x00002115 1647 1648 #define REG_A3XX_VGT_BIN_BASE 0x000021e1 1649 1650 #define REG_A3XX_VGT_BIN_SIZE 0x000021e2 1651 1652 #define REG_A3XX_PC_VSTREAM_CONTROL 0x000021e4 1653 #define A3XX_PC_VSTREAM_CONTROL_SIZE__MASK 0x003f0000 1654 #define A3XX_PC_VSTREAM_CONTROL_SIZE__SHIFT 16 1655 static inline uint32_t A3XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val) 1656 { 1657 return ((val) << A3XX_PC_VSTREAM_CONTROL_SIZE__SHIFT) & A3XX_PC_VSTREAM_CONTROL_SIZE__MASK; 1658 } 1659 #define A3XX_PC_VSTREAM_CONTROL_N__MASK 0x07c00000 1660 #define A3XX_PC_VSTREAM_CONTROL_N__SHIFT 22 1661 static inline uint32_t A3XX_PC_VSTREAM_CONTROL_N(uint32_t val) 1662 { 1663 return ((val) << A3XX_PC_VSTREAM_CONTROL_N__SHIFT) & A3XX_PC_VSTREAM_CONTROL_N__MASK; 1664 } 1665 1666 #define REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL 0x000021ea 1667 1668 #define REG_A3XX_PC_PRIM_VTX_CNTL 0x000021ec 1669 #define A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK 0x0000001f 1670 #define A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT 0 1671 static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(uint32_t val) 1672 { 1673 return ((val) << A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK; 1674 } 1675 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK 0x000000e0 1676 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT 5 1677 static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) 1678 { 1679 return ((val) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK; 1680 } 1681 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK 0x00000700 1682 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT 8 1683 static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val) 1684 { 1685 return ((val) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK; 1686 } 1687 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_ENABLE 0x00001000 1688 #define A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART 0x00100000 1689 #define A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000 1690 #define A3XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000 1691 1692 #define REG_A3XX_PC_RESTART_INDEX 0x000021ed 1693 1694 #define REG_A3XX_HLSQ_CONTROL_0_REG 0x00002200 1695 #define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000030 1696 #define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4 1697 static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val) 1698 { 1699 return ((val) << A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK; 1700 } 1701 #define A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040 1702 #define A3XX_HLSQ_CONTROL_0_REG_COMPUTEMODE 0x00000100 1703 #define A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART 0x00000200 1704 #define A3XX_HLSQ_CONTROL_0_REG_RESERVED2 0x00000400 1705 #define A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__MASK 0x00fff000 1706 #define A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__SHIFT 12 1707 static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC(uint32_t val) 1708 { 1709 return ((val) << A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__MASK; 1710 } 1711 #define A3XX_HLSQ_CONTROL_0_REG_FSONLYTEX 0x02000000 1712 #define A3XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE 0x04000000 1713 #define A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK 0x08000000 1714 #define A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT 27 1715 static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val) 1716 { 1717 return ((val) << A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK; 1718 } 1719 #define A3XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE 0x10000000 1720 #define A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE 0x20000000 1721 #define A3XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE 0x40000000 1722 #define A3XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT 0x80000000 1723 1724 #define REG_A3XX_HLSQ_CONTROL_1_REG 0x00002201 1725 #define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x000000c0 1726 #define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT 6 1727 static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val) 1728 { 1729 return ((val) << A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK; 1730 } 1731 #define A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100 1732 #define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__MASK 0x00ff0000 1733 #define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__SHIFT 16 1734 static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID(uint32_t val) 1735 { 1736 return ((val) << A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__MASK; 1737 } 1738 #define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__MASK 0xff000000 1739 #define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__SHIFT 24 1740 static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID(uint32_t val) 1741 { 1742 return ((val) << A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__MASK; 1743 } 1744 1745 #define REG_A3XX_HLSQ_CONTROL_2_REG 0x00002202 1746 #define A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__MASK 0x000003fc 1747 #define A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__SHIFT 2 1748 static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID(uint32_t val) 1749 { 1750 return ((val) << A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__MASK; 1751 } 1752 #define A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__MASK 0x03fc0000 1753 #define A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__SHIFT 18 1754 static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID(uint32_t val) 1755 { 1756 return ((val) << A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__MASK; 1757 } 1758 #define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000 1759 #define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT 26 1760 static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val) 1761 { 1762 return ((val) << A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK; 1763 } 1764 1765 #define REG_A3XX_HLSQ_CONTROL_3_REG 0x00002203 1766 #define A3XX_HLSQ_CONTROL_3_REG_REGID__MASK 0x000000ff 1767 #define A3XX_HLSQ_CONTROL_3_REG_REGID__SHIFT 0 1768 static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val) 1769 { 1770 return ((val) << A3XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A3XX_HLSQ_CONTROL_3_REG_REGID__MASK; 1771 } 1772 1773 #define REG_A3XX_HLSQ_VS_CONTROL_REG 0x00002204 1774 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x000003ff 1775 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT 0 1776 static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val) 1777 { 1778 return ((val) << A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK; 1779 } 1780 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x001ff000 1781 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT 12 1782 static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val) 1783 { 1784 return ((val) << A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK; 1785 } 1786 #define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 1787 #define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT 24 1788 static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val) 1789 { 1790 return ((val) << A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK; 1791 } 1792 1793 #define REG_A3XX_HLSQ_FS_CONTROL_REG 0x00002205 1794 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x000003ff 1795 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT 0 1796 static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val) 1797 { 1798 return ((val) << A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK; 1799 } 1800 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x001ff000 1801 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT 12 1802 static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val) 1803 { 1804 return ((val) << A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK; 1805 } 1806 #define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 1807 #define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT 24 1808 static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val) 1809 { 1810 return ((val) << A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK; 1811 } 1812 1813 #define REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG 0x00002206 1814 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK 0x000001ff 1815 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT 0 1816 static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(uint32_t val) 1817 { 1818 return ((val) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK; 1819 } 1820 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK 0x01ff0000 1821 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT 16 1822 static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(uint32_t val) 1823 { 1824 return ((val) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK; 1825 } 1826 1827 #define REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG 0x00002207 1828 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK 0x000001ff 1829 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT 0 1830 static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(uint32_t val) 1831 { 1832 return ((val) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK; 1833 } 1834 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK 0x01ff0000 1835 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT 16 1836 static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(uint32_t val) 1837 { 1838 return ((val) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK; 1839 } 1840 1841 #define REG_A3XX_HLSQ_CL_NDRANGE_0_REG 0x0000220a 1842 #define A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__MASK 0x00000003 1843 #define A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__SHIFT 0 1844 static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM(uint32_t val) 1845 { 1846 return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__MASK; 1847 } 1848 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__MASK 0x00000ffc 1849 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__SHIFT 2 1850 static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0(uint32_t val) 1851 { 1852 return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__MASK; 1853 } 1854 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__MASK 0x003ff000 1855 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__SHIFT 12 1856 static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1(uint32_t val) 1857 { 1858 return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__MASK; 1859 } 1860 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__MASK 0xffc00000 1861 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__SHIFT 22 1862 static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2(uint32_t val) 1863 { 1864 return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__MASK; 1865 } 1866 1867 static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK(uint32_t i0) { return 0x0000220b + 0x2*i0; } 1868 1869 static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_SIZE(uint32_t i0) { return 0x0000220b + 0x2*i0; } 1870 1871 static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_OFFSET(uint32_t i0) { return 0x0000220c + 0x2*i0; } 1872 1873 #define REG_A3XX_HLSQ_CL_CONTROL_0_REG 0x00002211 1874 1875 #define REG_A3XX_HLSQ_CL_CONTROL_1_REG 0x00002212 1876 1877 #define REG_A3XX_HLSQ_CL_KERNEL_CONST_REG 0x00002214 1878 1879 static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP(uint32_t i0) { return 0x00002215 + 0x1*i0; } 1880 1881 static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP_RATIO(uint32_t i0) { return 0x00002215 + 0x1*i0; } 1882 1883 #define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Y_REG 0x00002216 1884 1885 #define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Z_REG 0x00002217 1886 1887 #define REG_A3XX_HLSQ_CL_WG_OFFSET_REG 0x0000221a 1888 1889 #define REG_A3XX_VFD_CONTROL_0 0x00002240 1890 #define A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK 0x0003ffff 1891 #define A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT 0 1892 static inline uint32_t A3XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val) 1893 { 1894 return ((val) << A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK; 1895 } 1896 #define A3XX_VFD_CONTROL_0_PACKETSIZE__MASK 0x003c0000 1897 #define A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT 18 1898 static inline uint32_t A3XX_VFD_CONTROL_0_PACKETSIZE(uint32_t val) 1899 { 1900 return ((val) << A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT) & A3XX_VFD_CONTROL_0_PACKETSIZE__MASK; 1901 } 1902 #define A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK 0x07c00000 1903 #define A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT 22 1904 static inline uint32_t A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val) 1905 { 1906 return ((val) << A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK; 1907 } 1908 #define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK 0xf8000000 1909 #define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT 27 1910 static inline uint32_t A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val) 1911 { 1912 return ((val) << A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK; 1913 } 1914 1915 #define REG_A3XX_VFD_CONTROL_1 0x00002241 1916 #define A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000000f 1917 #define A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT 0 1918 static inline uint32_t A3XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val) 1919 { 1920 return ((val) << A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK; 1921 } 1922 #define A3XX_VFD_CONTROL_1_MAXTHRESHOLD__MASK 0x000000f0 1923 #define A3XX_VFD_CONTROL_1_MAXTHRESHOLD__SHIFT 4 1924 static inline uint32_t A3XX_VFD_CONTROL_1_MAXTHRESHOLD(uint32_t val) 1925 { 1926 return ((val) << A3XX_VFD_CONTROL_1_MAXTHRESHOLD__SHIFT) & A3XX_VFD_CONTROL_1_MAXTHRESHOLD__MASK; 1927 } 1928 #define A3XX_VFD_CONTROL_1_MINTHRESHOLD__MASK 0x00000f00 1929 #define A3XX_VFD_CONTROL_1_MINTHRESHOLD__SHIFT 8 1930 static inline uint32_t A3XX_VFD_CONTROL_1_MINTHRESHOLD(uint32_t val) 1931 { 1932 return ((val) << A3XX_VFD_CONTROL_1_MINTHRESHOLD__SHIFT) & A3XX_VFD_CONTROL_1_MINTHRESHOLD__MASK; 1933 } 1934 #define A3XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000 1935 #define A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16 1936 static inline uint32_t A3XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) 1937 { 1938 return ((val) << A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A3XX_VFD_CONTROL_1_REGID4VTX__MASK; 1939 } 1940 #define A3XX_VFD_CONTROL_1_REGID4INST__MASK 0xff000000 1941 #define A3XX_VFD_CONTROL_1_REGID4INST__SHIFT 24 1942 static inline uint32_t A3XX_VFD_CONTROL_1_REGID4INST(uint32_t val) 1943 { 1944 return ((val) << A3XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A3XX_VFD_CONTROL_1_REGID4INST__MASK; 1945 } 1946 1947 #define REG_A3XX_VFD_INDEX_MIN 0x00002242 1948 1949 #define REG_A3XX_VFD_INDEX_MAX 0x00002243 1950 1951 #define REG_A3XX_VFD_INSTANCEID_OFFSET 0x00002244 1952 1953 #define REG_A3XX_VFD_INDEX_OFFSET 0x00002245 1954 1955 #define REG_A3XX_VFD_INDEX_OFFSET 0x00002245 1956 1957 static inline uint32_t REG_A3XX_VFD_FETCH(uint32_t i0) { return 0x00002246 + 0x2*i0; } 1958 1959 static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x00002246 + 0x2*i0; } 1960 #define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f 1961 #define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT 0 1962 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val) 1963 { 1964 return ((val) << A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK; 1965 } 1966 #define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK 0x0000ff80 1967 #define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT 7 1968 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val) 1969 { 1970 return ((val) << A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK; 1971 } 1972 #define A3XX_VFD_FETCH_INSTR_0_INSTANCED 0x00010000 1973 #define A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT 0x00020000 1974 #define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK 0x00fc0000 1975 #define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT 18 1976 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_INDEXCODE(uint32_t val) 1977 { 1978 return ((val) << A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK; 1979 } 1980 #define A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK 0xff000000 1981 #define A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT 24 1982 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_STEPRATE(uint32_t val) 1983 { 1984 return ((val) << A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK; 1985 } 1986 1987 static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x00002247 + 0x2*i0; } 1988 1989 static inline uint32_t REG_A3XX_VFD_DECODE(uint32_t i0) { return 0x00002266 + 0x1*i0; } 1990 1991 static inline uint32_t REG_A3XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x00002266 + 0x1*i0; } 1992 #define A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f 1993 #define A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT 0 1994 static inline uint32_t A3XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val) 1995 { 1996 return ((val) << A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK; 1997 } 1998 #define A3XX_VFD_DECODE_INSTR_CONSTFILL 0x00000010 1999 #define A3XX_VFD_DECODE_INSTR_FORMAT__MASK 0x00000fc0 2000 #define A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT 6 2001 static inline uint32_t A3XX_VFD_DECODE_INSTR_FORMAT(enum a3xx_vtx_fmt val) 2002 { 2003 return ((val) << A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A3XX_VFD_DECODE_INSTR_FORMAT__MASK; 2004 } 2005 #define A3XX_VFD_DECODE_INSTR_REGID__MASK 0x000ff000 2006 #define A3XX_VFD_DECODE_INSTR_REGID__SHIFT 12 2007 static inline uint32_t A3XX_VFD_DECODE_INSTR_REGID(uint32_t val) 2008 { 2009 return ((val) << A3XX_VFD_DECODE_INSTR_REGID__SHIFT) & A3XX_VFD_DECODE_INSTR_REGID__MASK; 2010 } 2011 #define A3XX_VFD_DECODE_INSTR_INT 0x00100000 2012 #define A3XX_VFD_DECODE_INSTR_SWAP__MASK 0x00c00000 2013 #define A3XX_VFD_DECODE_INSTR_SWAP__SHIFT 22 2014 static inline uint32_t A3XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) 2015 { 2016 return ((val) << A3XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A3XX_VFD_DECODE_INSTR_SWAP__MASK; 2017 } 2018 #define A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK 0x1f000000 2019 #define A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT 24 2020 static inline uint32_t A3XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val) 2021 { 2022 return ((val) << A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK; 2023 } 2024 #define A3XX_VFD_DECODE_INSTR_LASTCOMPVALID 0x20000000 2025 #define A3XX_VFD_DECODE_INSTR_SWITCHNEXT 0x40000000 2026 2027 #define REG_A3XX_VFD_VS_THREADING_THRESHOLD 0x0000227e 2028 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK 0x0000000f 2029 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT 0 2030 static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(uint32_t val) 2031 { 2032 return ((val) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK; 2033 } 2034 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK 0x0000ff00 2035 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT 8 2036 static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(uint32_t val) 2037 { 2038 return ((val) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK; 2039 } 2040 2041 #define REG_A3XX_VPC_ATTR 0x00002280 2042 #define A3XX_VPC_ATTR_TOTALATTR__MASK 0x000001ff 2043 #define A3XX_VPC_ATTR_TOTALATTR__SHIFT 0 2044 static inline uint32_t A3XX_VPC_ATTR_TOTALATTR(uint32_t val) 2045 { 2046 return ((val) << A3XX_VPC_ATTR_TOTALATTR__SHIFT) & A3XX_VPC_ATTR_TOTALATTR__MASK; 2047 } 2048 #define A3XX_VPC_ATTR_PSIZE 0x00000200 2049 #define A3XX_VPC_ATTR_THRDASSIGN__MASK 0x0ffff000 2050 #define A3XX_VPC_ATTR_THRDASSIGN__SHIFT 12 2051 static inline uint32_t A3XX_VPC_ATTR_THRDASSIGN(uint32_t val) 2052 { 2053 return ((val) << A3XX_VPC_ATTR_THRDASSIGN__SHIFT) & A3XX_VPC_ATTR_THRDASSIGN__MASK; 2054 } 2055 #define A3XX_VPC_ATTR_LMSIZE__MASK 0xf0000000 2056 #define A3XX_VPC_ATTR_LMSIZE__SHIFT 28 2057 static inline uint32_t A3XX_VPC_ATTR_LMSIZE(uint32_t val) 2058 { 2059 return ((val) << A3XX_VPC_ATTR_LMSIZE__SHIFT) & A3XX_VPC_ATTR_LMSIZE__MASK; 2060 } 2061 2062 #define REG_A3XX_VPC_PACK 0x00002281 2063 #define A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK 0x0000ff00 2064 #define A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT 8 2065 static inline uint32_t A3XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val) 2066 { 2067 return ((val) << A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK; 2068 } 2069 #define A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK 0x00ff0000 2070 #define A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT 16 2071 static inline uint32_t A3XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val) 2072 { 2073 return ((val) << A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK; 2074 } 2075 2076 static inline uint32_t REG_A3XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002282 + 0x1*i0; } 2077 2078 static inline uint32_t REG_A3XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002282 + 0x1*i0; } 2079 #define A3XX_VPC_VARYING_INTERP_MODE_C0__MASK 0x00000003 2080 #define A3XX_VPC_VARYING_INTERP_MODE_C0__SHIFT 0 2081 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C0(enum a3xx_intp_mode val) 2082 { 2083 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C0__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C0__MASK; 2084 } 2085 #define A3XX_VPC_VARYING_INTERP_MODE_C1__MASK 0x0000000c 2086 #define A3XX_VPC_VARYING_INTERP_MODE_C1__SHIFT 2 2087 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C1(enum a3xx_intp_mode val) 2088 { 2089 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C1__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C1__MASK; 2090 } 2091 #define A3XX_VPC_VARYING_INTERP_MODE_C2__MASK 0x00000030 2092 #define A3XX_VPC_VARYING_INTERP_MODE_C2__SHIFT 4 2093 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C2(enum a3xx_intp_mode val) 2094 { 2095 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C2__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C2__MASK; 2096 } 2097 #define A3XX_VPC_VARYING_INTERP_MODE_C3__MASK 0x000000c0 2098 #define A3XX_VPC_VARYING_INTERP_MODE_C3__SHIFT 6 2099 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C3(enum a3xx_intp_mode val) 2100 { 2101 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C3__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C3__MASK; 2102 } 2103 #define A3XX_VPC_VARYING_INTERP_MODE_C4__MASK 0x00000300 2104 #define A3XX_VPC_VARYING_INTERP_MODE_C4__SHIFT 8 2105 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C4(enum a3xx_intp_mode val) 2106 { 2107 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C4__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C4__MASK; 2108 } 2109 #define A3XX_VPC_VARYING_INTERP_MODE_C5__MASK 0x00000c00 2110 #define A3XX_VPC_VARYING_INTERP_MODE_C5__SHIFT 10 2111 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C5(enum a3xx_intp_mode val) 2112 { 2113 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C5__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C5__MASK; 2114 } 2115 #define A3XX_VPC_VARYING_INTERP_MODE_C6__MASK 0x00003000 2116 #define A3XX_VPC_VARYING_INTERP_MODE_C6__SHIFT 12 2117 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C6(enum a3xx_intp_mode val) 2118 { 2119 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C6__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C6__MASK; 2120 } 2121 #define A3XX_VPC_VARYING_INTERP_MODE_C7__MASK 0x0000c000 2122 #define A3XX_VPC_VARYING_INTERP_MODE_C7__SHIFT 14 2123 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C7(enum a3xx_intp_mode val) 2124 { 2125 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C7__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C7__MASK; 2126 } 2127 #define A3XX_VPC_VARYING_INTERP_MODE_C8__MASK 0x00030000 2128 #define A3XX_VPC_VARYING_INTERP_MODE_C8__SHIFT 16 2129 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C8(enum a3xx_intp_mode val) 2130 { 2131 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C8__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C8__MASK; 2132 } 2133 #define A3XX_VPC_VARYING_INTERP_MODE_C9__MASK 0x000c0000 2134 #define A3XX_VPC_VARYING_INTERP_MODE_C9__SHIFT 18 2135 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C9(enum a3xx_intp_mode val) 2136 { 2137 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C9__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C9__MASK; 2138 } 2139 #define A3XX_VPC_VARYING_INTERP_MODE_CA__MASK 0x00300000 2140 #define A3XX_VPC_VARYING_INTERP_MODE_CA__SHIFT 20 2141 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CA(enum a3xx_intp_mode val) 2142 { 2143 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CA__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CA__MASK; 2144 } 2145 #define A3XX_VPC_VARYING_INTERP_MODE_CB__MASK 0x00c00000 2146 #define A3XX_VPC_VARYING_INTERP_MODE_CB__SHIFT 22 2147 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CB(enum a3xx_intp_mode val) 2148 { 2149 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CB__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CB__MASK; 2150 } 2151 #define A3XX_VPC_VARYING_INTERP_MODE_CC__MASK 0x03000000 2152 #define A3XX_VPC_VARYING_INTERP_MODE_CC__SHIFT 24 2153 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CC(enum a3xx_intp_mode val) 2154 { 2155 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CC__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CC__MASK; 2156 } 2157 #define A3XX_VPC_VARYING_INTERP_MODE_CD__MASK 0x0c000000 2158 #define A3XX_VPC_VARYING_INTERP_MODE_CD__SHIFT 26 2159 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CD(enum a3xx_intp_mode val) 2160 { 2161 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CD__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CD__MASK; 2162 } 2163 #define A3XX_VPC_VARYING_INTERP_MODE_CE__MASK 0x30000000 2164 #define A3XX_VPC_VARYING_INTERP_MODE_CE__SHIFT 28 2165 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CE(enum a3xx_intp_mode val) 2166 { 2167 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CE__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CE__MASK; 2168 } 2169 #define A3XX_VPC_VARYING_INTERP_MODE_CF__MASK 0xc0000000 2170 #define A3XX_VPC_VARYING_INTERP_MODE_CF__SHIFT 30 2171 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CF(enum a3xx_intp_mode val) 2172 { 2173 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CF__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CF__MASK; 2174 } 2175 2176 static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00002286 + 0x1*i0; } 2177 2178 static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00002286 + 0x1*i0; } 2179 #define A3XX_VPC_VARYING_PS_REPL_MODE_C0__MASK 0x00000003 2180 #define A3XX_VPC_VARYING_PS_REPL_MODE_C0__SHIFT 0 2181 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C0(enum a3xx_repl_mode val) 2182 { 2183 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C0__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C0__MASK; 2184 } 2185 #define A3XX_VPC_VARYING_PS_REPL_MODE_C1__MASK 0x0000000c 2186 #define A3XX_VPC_VARYING_PS_REPL_MODE_C1__SHIFT 2 2187 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C1(enum a3xx_repl_mode val) 2188 { 2189 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C1__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C1__MASK; 2190 } 2191 #define A3XX_VPC_VARYING_PS_REPL_MODE_C2__MASK 0x00000030 2192 #define A3XX_VPC_VARYING_PS_REPL_MODE_C2__SHIFT 4 2193 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C2(enum a3xx_repl_mode val) 2194 { 2195 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C2__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C2__MASK; 2196 } 2197 #define A3XX_VPC_VARYING_PS_REPL_MODE_C3__MASK 0x000000c0 2198 #define A3XX_VPC_VARYING_PS_REPL_MODE_C3__SHIFT 6 2199 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C3(enum a3xx_repl_mode val) 2200 { 2201 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C3__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C3__MASK; 2202 } 2203 #define A3XX_VPC_VARYING_PS_REPL_MODE_C4__MASK 0x00000300 2204 #define A3XX_VPC_VARYING_PS_REPL_MODE_C4__SHIFT 8 2205 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C4(enum a3xx_repl_mode val) 2206 { 2207 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C4__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C4__MASK; 2208 } 2209 #define A3XX_VPC_VARYING_PS_REPL_MODE_C5__MASK 0x00000c00 2210 #define A3XX_VPC_VARYING_PS_REPL_MODE_C5__SHIFT 10 2211 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C5(enum a3xx_repl_mode val) 2212 { 2213 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C5__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C5__MASK; 2214 } 2215 #define A3XX_VPC_VARYING_PS_REPL_MODE_C6__MASK 0x00003000 2216 #define A3XX_VPC_VARYING_PS_REPL_MODE_C6__SHIFT 12 2217 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C6(enum a3xx_repl_mode val) 2218 { 2219 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C6__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C6__MASK; 2220 } 2221 #define A3XX_VPC_VARYING_PS_REPL_MODE_C7__MASK 0x0000c000 2222 #define A3XX_VPC_VARYING_PS_REPL_MODE_C7__SHIFT 14 2223 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C7(enum a3xx_repl_mode val) 2224 { 2225 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C7__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C7__MASK; 2226 } 2227 #define A3XX_VPC_VARYING_PS_REPL_MODE_C8__MASK 0x00030000 2228 #define A3XX_VPC_VARYING_PS_REPL_MODE_C8__SHIFT 16 2229 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C8(enum a3xx_repl_mode val) 2230 { 2231 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C8__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C8__MASK; 2232 } 2233 #define A3XX_VPC_VARYING_PS_REPL_MODE_C9__MASK 0x000c0000 2234 #define A3XX_VPC_VARYING_PS_REPL_MODE_C9__SHIFT 18 2235 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C9(enum a3xx_repl_mode val) 2236 { 2237 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C9__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C9__MASK; 2238 } 2239 #define A3XX_VPC_VARYING_PS_REPL_MODE_CA__MASK 0x00300000 2240 #define A3XX_VPC_VARYING_PS_REPL_MODE_CA__SHIFT 20 2241 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CA(enum a3xx_repl_mode val) 2242 { 2243 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CA__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CA__MASK; 2244 } 2245 #define A3XX_VPC_VARYING_PS_REPL_MODE_CB__MASK 0x00c00000 2246 #define A3XX_VPC_VARYING_PS_REPL_MODE_CB__SHIFT 22 2247 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CB(enum a3xx_repl_mode val) 2248 { 2249 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CB__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CB__MASK; 2250 } 2251 #define A3XX_VPC_VARYING_PS_REPL_MODE_CC__MASK 0x03000000 2252 #define A3XX_VPC_VARYING_PS_REPL_MODE_CC__SHIFT 24 2253 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CC(enum a3xx_repl_mode val) 2254 { 2255 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CC__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CC__MASK; 2256 } 2257 #define A3XX_VPC_VARYING_PS_REPL_MODE_CD__MASK 0x0c000000 2258 #define A3XX_VPC_VARYING_PS_REPL_MODE_CD__SHIFT 26 2259 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CD(enum a3xx_repl_mode val) 2260 { 2261 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CD__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CD__MASK; 2262 } 2263 #define A3XX_VPC_VARYING_PS_REPL_MODE_CE__MASK 0x30000000 2264 #define A3XX_VPC_VARYING_PS_REPL_MODE_CE__SHIFT 28 2265 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CE(enum a3xx_repl_mode val) 2266 { 2267 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CE__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CE__MASK; 2268 } 2269 #define A3XX_VPC_VARYING_PS_REPL_MODE_CF__MASK 0xc0000000 2270 #define A3XX_VPC_VARYING_PS_REPL_MODE_CF__SHIFT 30 2271 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CF(enum a3xx_repl_mode val) 2272 { 2273 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CF__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CF__MASK; 2274 } 2275 2276 #define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0 0x0000228a 2277 2278 #define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_1 0x0000228b 2279 2280 #define REG_A3XX_SP_SP_CTRL_REG 0x000022c0 2281 #define A3XX_SP_SP_CTRL_REG_RESOLVE 0x00010000 2282 #define A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK 0x00040000 2283 #define A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT 18 2284 static inline uint32_t A3XX_SP_SP_CTRL_REG_CONSTMODE(uint32_t val) 2285 { 2286 return ((val) << A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK; 2287 } 2288 #define A3XX_SP_SP_CTRL_REG_BINNING 0x00080000 2289 #define A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK 0x00300000 2290 #define A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT 20 2291 static inline uint32_t A3XX_SP_SP_CTRL_REG_SLEEPMODE(uint32_t val) 2292 { 2293 return ((val) << A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK; 2294 } 2295 #define A3XX_SP_SP_CTRL_REG_L0MODE__MASK 0x00c00000 2296 #define A3XX_SP_SP_CTRL_REG_L0MODE__SHIFT 22 2297 static inline uint32_t A3XX_SP_SP_CTRL_REG_L0MODE(uint32_t val) 2298 { 2299 return ((val) << A3XX_SP_SP_CTRL_REG_L0MODE__SHIFT) & A3XX_SP_SP_CTRL_REG_L0MODE__MASK; 2300 } 2301 2302 #define REG_A3XX_SP_VS_CTRL_REG0 0x000022c4 2303 #define A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001 2304 #define A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0 2305 static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 2306 { 2307 return ((val) << A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK; 2308 } 2309 #define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK 0x00000002 2310 #define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT 1 2311 static inline uint32_t A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val) 2312 { 2313 return ((val) << A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK; 2314 } 2315 #define A3XX_SP_VS_CTRL_REG0_CACHEINVALID 0x00000004 2316 #define A3XX_SP_VS_CTRL_REG0_ALUSCHMODE 0x00000008 2317 #define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 2318 #define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 2319 static inline uint32_t A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 2320 { 2321 return ((val) << A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 2322 } 2323 #define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00 2324 #define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 2325 static inline uint32_t A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 2326 { 2327 return ((val) << A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 2328 } 2329 #define A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000 2330 #define A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20 2331 static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 2332 { 2333 return ((val) << A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK; 2334 } 2335 #define A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000 2336 #define A3XX_SP_VS_CTRL_REG0_LENGTH__MASK 0xff000000 2337 #define A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT 24 2338 static inline uint32_t A3XX_SP_VS_CTRL_REG0_LENGTH(uint32_t val) 2339 { 2340 return ((val) << A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT) & A3XX_SP_VS_CTRL_REG0_LENGTH__MASK; 2341 } 2342 2343 #define REG_A3XX_SP_VS_CTRL_REG1 0x000022c5 2344 #define A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK 0x000003ff 2345 #define A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT 0 2346 static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val) 2347 { 2348 return ((val) << A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK; 2349 } 2350 #define A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK 0x000ffc00 2351 #define A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT 10 2352 static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val) 2353 { 2354 return ((val) << A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK; 2355 } 2356 #define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x7f000000 2357 #define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 24 2358 static inline uint32_t A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) 2359 { 2360 return ((val) << A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK; 2361 } 2362 2363 #define REG_A3XX_SP_VS_PARAM_REG 0x000022c6 2364 #define A3XX_SP_VS_PARAM_REG_POSREGID__MASK 0x000000ff 2365 #define A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT 0 2366 static inline uint32_t A3XX_SP_VS_PARAM_REG_POSREGID(uint32_t val) 2367 { 2368 return ((val) << A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A3XX_SP_VS_PARAM_REG_POSREGID__MASK; 2369 } 2370 #define A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK 0x0000ff00 2371 #define A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT 8 2372 static inline uint32_t A3XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val) 2373 { 2374 return ((val) << A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK; 2375 } 2376 #define A3XX_SP_VS_PARAM_REG_POS2DMODE 0x00010000 2377 #define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0x01f00000 2378 #define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT 20 2379 static inline uint32_t A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val) 2380 { 2381 return ((val) << A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK; 2382 } 2383 2384 static inline uint32_t REG_A3XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; } 2385 2386 static inline uint32_t REG_A3XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; } 2387 #define A3XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff 2388 #define A3XX_SP_VS_OUT_REG_A_REGID__SHIFT 0 2389 static inline uint32_t A3XX_SP_VS_OUT_REG_A_REGID(uint32_t val) 2390 { 2391 return ((val) << A3XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_A_REGID__MASK; 2392 } 2393 #define A3XX_SP_VS_OUT_REG_A_HALF 0x00000100 2394 #define A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00001e00 2395 #define A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 9 2396 static inline uint32_t A3XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) 2397 { 2398 return ((val) << A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK; 2399 } 2400 #define A3XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000 2401 #define A3XX_SP_VS_OUT_REG_B_REGID__SHIFT 16 2402 static inline uint32_t A3XX_SP_VS_OUT_REG_B_REGID(uint32_t val) 2403 { 2404 return ((val) << A3XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_B_REGID__MASK; 2405 } 2406 #define A3XX_SP_VS_OUT_REG_B_HALF 0x01000000 2407 #define A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x1e000000 2408 #define A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 25 2409 static inline uint32_t A3XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) 2410 { 2411 return ((val) << A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK; 2412 } 2413 2414 static inline uint32_t REG_A3XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d0 + 0x1*i0; } 2415 2416 static inline uint32_t REG_A3XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d0 + 0x1*i0; } 2417 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x0000007f 2418 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0 2419 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) 2420 { 2421 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; 2422 } 2423 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x00007f00 2424 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8 2425 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) 2426 { 2427 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; 2428 } 2429 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x007f0000 2430 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16 2431 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) 2432 { 2433 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; 2434 } 2435 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0x7f000000 2436 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24 2437 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) 2438 { 2439 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; 2440 } 2441 2442 #define REG_A3XX_SP_VS_OBJ_OFFSET_REG 0x000022d4 2443 #define A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK 0x0000ffff 2444 #define A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT 0 2445 static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET(uint32_t val) 2446 { 2447 return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK; 2448 } 2449 #define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 2450 #define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 2451 static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 2452 { 2453 return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 2454 } 2455 #define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 2456 #define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 2457 static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 2458 { 2459 return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 2460 } 2461 2462 #define REG_A3XX_SP_VS_OBJ_START_REG 0x000022d5 2463 2464 #define REG_A3XX_SP_VS_PVT_MEM_PARAM_REG 0x000022d6 2465 #define A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK 0x000000ff 2466 #define A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT 0 2467 static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM(uint32_t val) 2468 { 2469 return ((val) << A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK; 2470 } 2471 #define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK 0x00ffff00 2472 #define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT 8 2473 static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET(uint32_t val) 2474 { 2475 return ((val) << A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK; 2476 } 2477 #define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK 0xff000000 2478 #define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT 24 2479 static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD(uint32_t val) 2480 { 2481 return ((val) << A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK; 2482 } 2483 2484 #define REG_A3XX_SP_VS_PVT_MEM_ADDR_REG 0x000022d7 2485 #define A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__MASK 0x0000001f 2486 #define A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT 0 2487 static inline uint32_t A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN(uint32_t val) 2488 { 2489 return ((val) << A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT) & A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__MASK; 2490 } 2491 #define A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK 0xffffffe0 2492 #define A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT 5 2493 static inline uint32_t A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS(uint32_t val) 2494 { 2495 assert(!(val & 0x1f)); 2496 return ((val >> 5) << A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT) & A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK; 2497 } 2498 2499 #define REG_A3XX_SP_VS_PVT_MEM_SIZE_REG 0x000022d8 2500 2501 #define REG_A3XX_SP_VS_LENGTH_REG 0x000022df 2502 #define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK 0xffffffff 2503 #define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT 0 2504 static inline uint32_t A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(uint32_t val) 2505 { 2506 return ((val) << A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT) & A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK; 2507 } 2508 2509 #define REG_A3XX_SP_FS_CTRL_REG0 0x000022e0 2510 #define A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001 2511 #define A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0 2512 static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 2513 { 2514 return ((val) << A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK; 2515 } 2516 #define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK 0x00000002 2517 #define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT 1 2518 static inline uint32_t A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val) 2519 { 2520 return ((val) << A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK; 2521 } 2522 #define A3XX_SP_FS_CTRL_REG0_CACHEINVALID 0x00000004 2523 #define A3XX_SP_FS_CTRL_REG0_ALUSCHMODE 0x00000008 2524 #define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 2525 #define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 2526 static inline uint32_t A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 2527 { 2528 return ((val) << A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 2529 } 2530 #define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00 2531 #define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 2532 static inline uint32_t A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 2533 { 2534 return ((val) << A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 2535 } 2536 #define A3XX_SP_FS_CTRL_REG0_FSBYPASSENABLE 0x00020000 2537 #define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP 0x00040000 2538 #define A3XX_SP_FS_CTRL_REG0_OUTORDERED 0x00080000 2539 #define A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000 2540 #define A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20 2541 static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 2542 { 2543 return ((val) << A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; 2544 } 2545 #define A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE 0x00200000 2546 #define A3XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00400000 2547 #define A3XX_SP_FS_CTRL_REG0_COMPUTEMODE 0x00800000 2548 #define A3XX_SP_FS_CTRL_REG0_LENGTH__MASK 0xff000000 2549 #define A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT 24 2550 static inline uint32_t A3XX_SP_FS_CTRL_REG0_LENGTH(uint32_t val) 2551 { 2552 return ((val) << A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT) & A3XX_SP_FS_CTRL_REG0_LENGTH__MASK; 2553 } 2554 2555 #define REG_A3XX_SP_FS_CTRL_REG1 0x000022e1 2556 #define A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK 0x000003ff 2557 #define A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT 0 2558 static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val) 2559 { 2560 return ((val) << A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK; 2561 } 2562 #define A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK 0x000ffc00 2563 #define A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT 10 2564 static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val) 2565 { 2566 return ((val) << A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK; 2567 } 2568 #define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x00f00000 2569 #define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 20 2570 static inline uint32_t A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) 2571 { 2572 return ((val) << A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK; 2573 } 2574 #define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK 0x7f000000 2575 #define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT 24 2576 static inline uint32_t A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(uint32_t val) 2577 { 2578 return ((val) << A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT) & A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK; 2579 } 2580 2581 #define REG_A3XX_SP_FS_OBJ_OFFSET_REG 0x000022e2 2582 #define A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK 0x0000ffff 2583 #define A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT 0 2584 static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET(uint32_t val) 2585 { 2586 return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK; 2587 } 2588 #define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 2589 #define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 2590 static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 2591 { 2592 return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 2593 } 2594 #define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 2595 #define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 2596 static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 2597 { 2598 return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 2599 } 2600 2601 #define REG_A3XX_SP_FS_OBJ_START_REG 0x000022e3 2602 2603 #define REG_A3XX_SP_FS_PVT_MEM_PARAM_REG 0x000022e4 2604 #define A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK 0x000000ff 2605 #define A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT 0 2606 static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM(uint32_t val) 2607 { 2608 return ((val) << A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT) & A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK; 2609 } 2610 #define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK 0x00ffff00 2611 #define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT 8 2612 static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET(uint32_t val) 2613 { 2614 return ((val) << A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT) & A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK; 2615 } 2616 #define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK 0xff000000 2617 #define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT 24 2618 static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD(uint32_t val) 2619 { 2620 return ((val) << A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT) & A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK; 2621 } 2622 2623 #define REG_A3XX_SP_FS_PVT_MEM_ADDR_REG 0x000022e5 2624 #define A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__MASK 0x0000001f 2625 #define A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT 0 2626 static inline uint32_t A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN(uint32_t val) 2627 { 2628 return ((val) << A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT) & A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__MASK; 2629 } 2630 #define A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK 0xffffffe0 2631 #define A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT 5 2632 static inline uint32_t A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS(uint32_t val) 2633 { 2634 assert(!(val & 0x1f)); 2635 return ((val >> 5) << A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT) & A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK; 2636 } 2637 2638 #define REG_A3XX_SP_FS_PVT_MEM_SIZE_REG 0x000022e6 2639 2640 #define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0 0x000022e8 2641 2642 #define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_1 0x000022e9 2643 2644 #define REG_A3XX_SP_FS_OUTPUT_REG 0x000022ec 2645 #define A3XX_SP_FS_OUTPUT_REG_MRT__MASK 0x00000003 2646 #define A3XX_SP_FS_OUTPUT_REG_MRT__SHIFT 0 2647 static inline uint32_t A3XX_SP_FS_OUTPUT_REG_MRT(uint32_t val) 2648 { 2649 return ((val) << A3XX_SP_FS_OUTPUT_REG_MRT__SHIFT) & A3XX_SP_FS_OUTPUT_REG_MRT__MASK; 2650 } 2651 #define A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE 0x00000080 2652 #define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK 0x0000ff00 2653 #define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT 8 2654 static inline uint32_t A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val) 2655 { 2656 return ((val) << A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK; 2657 } 2658 2659 static inline uint32_t REG_A3XX_SP_FS_MRT(uint32_t i0) { return 0x000022f0 + 0x1*i0; } 2660 2661 static inline uint32_t REG_A3XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f0 + 0x1*i0; } 2662 #define A3XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff 2663 #define A3XX_SP_FS_MRT_REG_REGID__SHIFT 0 2664 static inline uint32_t A3XX_SP_FS_MRT_REG_REGID(uint32_t val) 2665 { 2666 return ((val) << A3XX_SP_FS_MRT_REG_REGID__SHIFT) & A3XX_SP_FS_MRT_REG_REGID__MASK; 2667 } 2668 #define A3XX_SP_FS_MRT_REG_HALF_PRECISION 0x00000100 2669 #define A3XX_SP_FS_MRT_REG_SINT 0x00000400 2670 #define A3XX_SP_FS_MRT_REG_UINT 0x00000800 2671 2672 static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT(uint32_t i0) { return 0x000022f4 + 0x1*i0; } 2673 2674 static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(uint32_t i0) { return 0x000022f4 + 0x1*i0; } 2675 #define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK 0x0000003f 2676 #define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT 0 2677 static inline uint32_t A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(enum a3xx_color_fmt val) 2678 { 2679 return ((val) << A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT) & A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK; 2680 } 2681 2682 #define REG_A3XX_SP_FS_LENGTH_REG 0x000022ff 2683 #define A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK 0xffffffff 2684 #define A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT 0 2685 static inline uint32_t A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(uint32_t val) 2686 { 2687 return ((val) << A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT) & A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK; 2688 } 2689 2690 #define REG_A3XX_PA_SC_AA_CONFIG 0x00002301 2691 2692 #define REG_A3XX_TPL1_TP_VS_TEX_OFFSET 0x00002340 2693 #define A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK 0x000000ff 2694 #define A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT 0 2695 static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val) 2696 { 2697 return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK; 2698 } 2699 #define A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK 0x0000ff00 2700 #define A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT 8 2701 static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val) 2702 { 2703 return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK; 2704 } 2705 #define A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK 0xffff0000 2706 #define A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT 16 2707 static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(uint32_t val) 2708 { 2709 return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK; 2710 } 2711 2712 #define REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR 0x00002341 2713 2714 #define REG_A3XX_TPL1_TP_FS_TEX_OFFSET 0x00002342 2715 #define A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK 0x000000ff 2716 #define A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT 0 2717 static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val) 2718 { 2719 return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK; 2720 } 2721 #define A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK 0x0000ff00 2722 #define A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT 8 2723 static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val) 2724 { 2725 return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK; 2726 } 2727 #define A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK 0xffff0000 2728 #define A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT 16 2729 static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(uint32_t val) 2730 { 2731 return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK; 2732 } 2733 2734 #define REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR 0x00002343 2735 2736 #define REG_A3XX_VBIF_CLKON 0x00003001 2737 2738 #define REG_A3XX_VBIF_FIXED_SORT_EN 0x0000300c 2739 2740 #define REG_A3XX_VBIF_FIXED_SORT_SEL0 0x0000300d 2741 2742 #define REG_A3XX_VBIF_FIXED_SORT_SEL1 0x0000300e 2743 2744 #define REG_A3XX_VBIF_ABIT_SORT 0x0000301c 2745 2746 #define REG_A3XX_VBIF_ABIT_SORT_CONF 0x0000301d 2747 2748 #define REG_A3XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a 2749 2750 #define REG_A3XX_VBIF_IN_RD_LIM_CONF0 0x0000302c 2751 2752 #define REG_A3XX_VBIF_IN_RD_LIM_CONF1 0x0000302d 2753 2754 #define REG_A3XX_VBIF_IN_WR_LIM_CONF0 0x00003030 2755 2756 #define REG_A3XX_VBIF_IN_WR_LIM_CONF1 0x00003031 2757 2758 #define REG_A3XX_VBIF_OUT_RD_LIM_CONF0 0x00003034 2759 2760 #define REG_A3XX_VBIF_OUT_WR_LIM_CONF0 0x00003035 2761 2762 #define REG_A3XX_VBIF_DDR_OUT_MAX_BURST 0x00003036 2763 2764 #define REG_A3XX_VBIF_ARB_CTL 0x0000303c 2765 2766 #define REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049 2767 2768 #define REG_A3XX_VBIF_OUT_AXI_AMEMTYPE_CONF0 0x00003058 2769 2770 #define REG_A3XX_VBIF_OUT_AXI_AOOO_EN 0x0000305e 2771 2772 #define REG_A3XX_VBIF_OUT_AXI_AOOO 0x0000305f 2773 2774 #define REG_A3XX_VBIF_PERF_CNT_EN 0x00003070 2775 #define A3XX_VBIF_PERF_CNT_EN_CNT0 0x00000001 2776 #define A3XX_VBIF_PERF_CNT_EN_CNT1 0x00000002 2777 #define A3XX_VBIF_PERF_CNT_EN_PWRCNT0 0x00000004 2778 #define A3XX_VBIF_PERF_CNT_EN_PWRCNT1 0x00000008 2779 #define A3XX_VBIF_PERF_CNT_EN_PWRCNT2 0x00000010 2780 2781 #define REG_A3XX_VBIF_PERF_CNT_CLR 0x00003071 2782 #define A3XX_VBIF_PERF_CNT_CLR_CNT0 0x00000001 2783 #define A3XX_VBIF_PERF_CNT_CLR_CNT1 0x00000002 2784 #define A3XX_VBIF_PERF_CNT_CLR_PWRCNT0 0x00000004 2785 #define A3XX_VBIF_PERF_CNT_CLR_PWRCNT1 0x00000008 2786 #define A3XX_VBIF_PERF_CNT_CLR_PWRCNT2 0x00000010 2787 2788 #define REG_A3XX_VBIF_PERF_CNT_SEL 0x00003072 2789 2790 #define REG_A3XX_VBIF_PERF_CNT0_LO 0x00003073 2791 2792 #define REG_A3XX_VBIF_PERF_CNT0_HI 0x00003074 2793 2794 #define REG_A3XX_VBIF_PERF_CNT1_LO 0x00003075 2795 2796 #define REG_A3XX_VBIF_PERF_CNT1_HI 0x00003076 2797 2798 #define REG_A3XX_VBIF_PERF_PWR_CNT0_LO 0x00003077 2799 2800 #define REG_A3XX_VBIF_PERF_PWR_CNT0_HI 0x00003078 2801 2802 #define REG_A3XX_VBIF_PERF_PWR_CNT1_LO 0x00003079 2803 2804 #define REG_A3XX_VBIF_PERF_PWR_CNT1_HI 0x0000307a 2805 2806 #define REG_A3XX_VBIF_PERF_PWR_CNT2_LO 0x0000307b 2807 2808 #define REG_A3XX_VBIF_PERF_PWR_CNT2_HI 0x0000307c 2809 2810 #define REG_A3XX_VSC_BIN_SIZE 0x00000c01 2811 #define A3XX_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f 2812 #define A3XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 2813 static inline uint32_t A3XX_VSC_BIN_SIZE_WIDTH(uint32_t val) 2814 { 2815 assert(!(val & 0x1f)); 2816 return ((val >> 5) << A3XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A3XX_VSC_BIN_SIZE_WIDTH__MASK; 2817 } 2818 #define A3XX_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0 2819 #define A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT 5 2820 static inline uint32_t A3XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) 2821 { 2822 assert(!(val & 0x1f)); 2823 return ((val >> 5) << A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A3XX_VSC_BIN_SIZE_HEIGHT__MASK; 2824 } 2825 2826 #define REG_A3XX_VSC_SIZE_ADDRESS 0x00000c02 2827 2828 static inline uint32_t REG_A3XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; } 2829 2830 static inline uint32_t REG_A3XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; } 2831 #define A3XX_VSC_PIPE_CONFIG_X__MASK 0x000003ff 2832 #define A3XX_VSC_PIPE_CONFIG_X__SHIFT 0 2833 static inline uint32_t A3XX_VSC_PIPE_CONFIG_X(uint32_t val) 2834 { 2835 return ((val) << A3XX_VSC_PIPE_CONFIG_X__SHIFT) & A3XX_VSC_PIPE_CONFIG_X__MASK; 2836 } 2837 #define A3XX_VSC_PIPE_CONFIG_Y__MASK 0x000ffc00 2838 #define A3XX_VSC_PIPE_CONFIG_Y__SHIFT 10 2839 static inline uint32_t A3XX_VSC_PIPE_CONFIG_Y(uint32_t val) 2840 { 2841 return ((val) << A3XX_VSC_PIPE_CONFIG_Y__SHIFT) & A3XX_VSC_PIPE_CONFIG_Y__MASK; 2842 } 2843 #define A3XX_VSC_PIPE_CONFIG_W__MASK 0x00f00000 2844 #define A3XX_VSC_PIPE_CONFIG_W__SHIFT 20 2845 static inline uint32_t A3XX_VSC_PIPE_CONFIG_W(uint32_t val) 2846 { 2847 return ((val) << A3XX_VSC_PIPE_CONFIG_W__SHIFT) & A3XX_VSC_PIPE_CONFIG_W__MASK; 2848 } 2849 #define A3XX_VSC_PIPE_CONFIG_H__MASK 0x0f000000 2850 #define A3XX_VSC_PIPE_CONFIG_H__SHIFT 24 2851 static inline uint32_t A3XX_VSC_PIPE_CONFIG_H(uint32_t val) 2852 { 2853 return ((val) << A3XX_VSC_PIPE_CONFIG_H__SHIFT) & A3XX_VSC_PIPE_CONFIG_H__MASK; 2854 } 2855 2856 static inline uint32_t REG_A3XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; } 2857 2858 static inline uint32_t REG_A3XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; } 2859 2860 #define REG_A3XX_VSC_BIN_CONTROL 0x00000c3c 2861 #define A3XX_VSC_BIN_CONTROL_BINNING_ENABLE 0x00000001 2862 2863 #define REG_A3XX_UNKNOWN_0C3D 0x00000c3d 2864 2865 #define REG_A3XX_PC_PERFCOUNTER0_SELECT 0x00000c48 2866 2867 #define REG_A3XX_PC_PERFCOUNTER1_SELECT 0x00000c49 2868 2869 #define REG_A3XX_PC_PERFCOUNTER2_SELECT 0x00000c4a 2870 2871 #define REG_A3XX_PC_PERFCOUNTER3_SELECT 0x00000c4b 2872 2873 #define REG_A3XX_GRAS_TSE_DEBUG_ECO 0x00000c81 2874 2875 #define REG_A3XX_GRAS_PERFCOUNTER0_SELECT 0x00000c88 2876 2877 #define REG_A3XX_GRAS_PERFCOUNTER1_SELECT 0x00000c89 2878 2879 #define REG_A3XX_GRAS_PERFCOUNTER2_SELECT 0x00000c8a 2880 2881 #define REG_A3XX_GRAS_PERFCOUNTER3_SELECT 0x00000c8b 2882 2883 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE(uint32_t i0) { return 0x00000ca0 + 0x4*i0; } 2884 2885 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_X(uint32_t i0) { return 0x00000ca0 + 0x4*i0; } 2886 2887 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Y(uint32_t i0) { return 0x00000ca1 + 0x4*i0; } 2888 2889 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Z(uint32_t i0) { return 0x00000ca2 + 0x4*i0; } 2890 2891 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_W(uint32_t i0) { return 0x00000ca3 + 0x4*i0; } 2892 2893 #define REG_A3XX_RB_GMEM_BASE_ADDR 0x00000cc0 2894 2895 #define REG_A3XX_RB_DEBUG_ECO_CONTROLS_ADDR 0x00000cc1 2896 2897 #define REG_A3XX_RB_PERFCOUNTER0_SELECT 0x00000cc6 2898 2899 #define REG_A3XX_RB_PERFCOUNTER1_SELECT 0x00000cc7 2900 2901 #define REG_A3XX_RB_FRAME_BUFFER_DIMENSION 0x00000ce0 2902 #define A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK 0x00003fff 2903 #define A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT 0 2904 static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val) 2905 { 2906 return ((val) << A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK; 2907 } 2908 #define A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK 0x0fffc000 2909 #define A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT 14 2910 static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) 2911 { 2912 return ((val) << A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK; 2913 } 2914 2915 #define REG_A3XX_HLSQ_PERFCOUNTER0_SELECT 0x00000e00 2916 2917 #define REG_A3XX_HLSQ_PERFCOUNTER1_SELECT 0x00000e01 2918 2919 #define REG_A3XX_HLSQ_PERFCOUNTER2_SELECT 0x00000e02 2920 2921 #define REG_A3XX_HLSQ_PERFCOUNTER3_SELECT 0x00000e03 2922 2923 #define REG_A3XX_HLSQ_PERFCOUNTER4_SELECT 0x00000e04 2924 2925 #define REG_A3XX_HLSQ_PERFCOUNTER5_SELECT 0x00000e05 2926 2927 #define REG_A3XX_UNKNOWN_0E43 0x00000e43 2928 2929 #define REG_A3XX_VFD_PERFCOUNTER0_SELECT 0x00000e44 2930 2931 #define REG_A3XX_VFD_PERFCOUNTER1_SELECT 0x00000e45 2932 2933 #define REG_A3XX_VPC_VPC_DEBUG_RAM_SEL 0x00000e61 2934 2935 #define REG_A3XX_VPC_VPC_DEBUG_RAM_READ 0x00000e62 2936 2937 #define REG_A3XX_VPC_PERFCOUNTER0_SELECT 0x00000e64 2938 2939 #define REG_A3XX_VPC_PERFCOUNTER1_SELECT 0x00000e65 2940 2941 #define REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG 0x00000e82 2942 2943 #define REG_A3XX_UCHE_PERFCOUNTER0_SELECT 0x00000e84 2944 2945 #define REG_A3XX_UCHE_PERFCOUNTER1_SELECT 0x00000e85 2946 2947 #define REG_A3XX_UCHE_PERFCOUNTER2_SELECT 0x00000e86 2948 2949 #define REG_A3XX_UCHE_PERFCOUNTER3_SELECT 0x00000e87 2950 2951 #define REG_A3XX_UCHE_PERFCOUNTER4_SELECT 0x00000e88 2952 2953 #define REG_A3XX_UCHE_PERFCOUNTER5_SELECT 0x00000e89 2954 2955 #define REG_A3XX_UCHE_CACHE_INVALIDATE0_REG 0x00000ea0 2956 #define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK 0x0fffffff 2957 #define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT 0 2958 static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(uint32_t val) 2959 { 2960 return ((val) << A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK; 2961 } 2962 2963 #define REG_A3XX_UCHE_CACHE_INVALIDATE1_REG 0x00000ea1 2964 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK 0x0fffffff 2965 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT 0 2966 static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(uint32_t val) 2967 { 2968 return ((val) << A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK; 2969 } 2970 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK 0x30000000 2971 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT 28 2972 static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(enum a3xx_cache_opcode val) 2973 { 2974 return ((val) << A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK; 2975 } 2976 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ENTIRE_CACHE 0x80000000 2977 2978 #define REG_A3XX_UNKNOWN_0EA6 0x00000ea6 2979 2980 #define REG_A3XX_SP_PERFCOUNTER0_SELECT 0x00000ec4 2981 2982 #define REG_A3XX_SP_PERFCOUNTER1_SELECT 0x00000ec5 2983 2984 #define REG_A3XX_SP_PERFCOUNTER2_SELECT 0x00000ec6 2985 2986 #define REG_A3XX_SP_PERFCOUNTER3_SELECT 0x00000ec7 2987 2988 #define REG_A3XX_SP_PERFCOUNTER4_SELECT 0x00000ec8 2989 2990 #define REG_A3XX_SP_PERFCOUNTER5_SELECT 0x00000ec9 2991 2992 #define REG_A3XX_SP_PERFCOUNTER6_SELECT 0x00000eca 2993 2994 #define REG_A3XX_SP_PERFCOUNTER7_SELECT 0x00000ecb 2995 2996 #define REG_A3XX_UNKNOWN_0EE0 0x00000ee0 2997 2998 #define REG_A3XX_UNKNOWN_0F03 0x00000f03 2999 3000 #define REG_A3XX_TP_PERFCOUNTER0_SELECT 0x00000f04 3001 3002 #define REG_A3XX_TP_PERFCOUNTER1_SELECT 0x00000f05 3003 3004 #define REG_A3XX_TP_PERFCOUNTER2_SELECT 0x00000f06 3005 3006 #define REG_A3XX_TP_PERFCOUNTER3_SELECT 0x00000f07 3007 3008 #define REG_A3XX_TP_PERFCOUNTER4_SELECT 0x00000f08 3009 3010 #define REG_A3XX_TP_PERFCOUNTER5_SELECT 0x00000f09 3011 3012 #define REG_A3XX_VGT_CL_INITIATOR 0x000021f0 3013 3014 #define REG_A3XX_VGT_EVENT_INITIATOR 0x000021f9 3015 3016 #define REG_A3XX_VGT_DRAW_INITIATOR 0x000021fc 3017 #define A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f 3018 #define A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0 3019 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) 3020 { 3021 return ((val) << A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK; 3022 } 3023 #define A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0 3024 #define A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6 3025 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) 3026 { 3027 return ((val) << A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK; 3028 } 3029 #define A3XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK 0x00000600 3030 #define A3XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT 9 3031 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) 3032 { 3033 return ((val) << A3XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT) & A3XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK; 3034 } 3035 #define A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000800 3036 #define A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT 11 3037 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val) 3038 { 3039 return ((val) << A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK; 3040 } 3041 #define A3XX_VGT_DRAW_INITIATOR_NOT_EOP 0x00001000 3042 #define A3XX_VGT_DRAW_INITIATOR_SMALL_INDEX 0x00002000 3043 #define A3XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE 0x00004000 3044 #define A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK 0xff000000 3045 #define A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT 24 3046 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val) 3047 { 3048 return ((val) << A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT) & A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK; 3049 } 3050 3051 #define REG_A3XX_VGT_IMMED_DATA 0x000021fd 3052 3053 #define REG_A3XX_TEX_SAMP_0 0x00000000 3054 #define A3XX_TEX_SAMP_0_CLAMPENABLE 0x00000001 3055 #define A3XX_TEX_SAMP_0_MIPFILTER_LINEAR 0x00000002 3056 #define A3XX_TEX_SAMP_0_XY_MAG__MASK 0x0000000c 3057 #define A3XX_TEX_SAMP_0_XY_MAG__SHIFT 2 3058 static inline uint32_t A3XX_TEX_SAMP_0_XY_MAG(enum a3xx_tex_filter val) 3059 { 3060 return ((val) << A3XX_TEX_SAMP_0_XY_MAG__SHIFT) & A3XX_TEX_SAMP_0_XY_MAG__MASK; 3061 } 3062 #define A3XX_TEX_SAMP_0_XY_MIN__MASK 0x00000030 3063 #define A3XX_TEX_SAMP_0_XY_MIN__SHIFT 4 3064 static inline uint32_t A3XX_TEX_SAMP_0_XY_MIN(enum a3xx_tex_filter val) 3065 { 3066 return ((val) << A3XX_TEX_SAMP_0_XY_MIN__SHIFT) & A3XX_TEX_SAMP_0_XY_MIN__MASK; 3067 } 3068 #define A3XX_TEX_SAMP_0_WRAP_S__MASK 0x000001c0 3069 #define A3XX_TEX_SAMP_0_WRAP_S__SHIFT 6 3070 static inline uint32_t A3XX_TEX_SAMP_0_WRAP_S(enum a3xx_tex_clamp val) 3071 { 3072 return ((val) << A3XX_TEX_SAMP_0_WRAP_S__SHIFT) & A3XX_TEX_SAMP_0_WRAP_S__MASK; 3073 } 3074 #define A3XX_TEX_SAMP_0_WRAP_T__MASK 0x00000e00 3075 #define A3XX_TEX_SAMP_0_WRAP_T__SHIFT 9 3076 static inline uint32_t A3XX_TEX_SAMP_0_WRAP_T(enum a3xx_tex_clamp val) 3077 { 3078 return ((val) << A3XX_TEX_SAMP_0_WRAP_T__SHIFT) & A3XX_TEX_SAMP_0_WRAP_T__MASK; 3079 } 3080 #define A3XX_TEX_SAMP_0_WRAP_R__MASK 0x00007000 3081 #define A3XX_TEX_SAMP_0_WRAP_R__SHIFT 12 3082 static inline uint32_t A3XX_TEX_SAMP_0_WRAP_R(enum a3xx_tex_clamp val) 3083 { 3084 return ((val) << A3XX_TEX_SAMP_0_WRAP_R__SHIFT) & A3XX_TEX_SAMP_0_WRAP_R__MASK; 3085 } 3086 #define A3XX_TEX_SAMP_0_ANISO__MASK 0x00038000 3087 #define A3XX_TEX_SAMP_0_ANISO__SHIFT 15 3088 static inline uint32_t A3XX_TEX_SAMP_0_ANISO(enum a3xx_tex_aniso val) 3089 { 3090 return ((val) << A3XX_TEX_SAMP_0_ANISO__SHIFT) & A3XX_TEX_SAMP_0_ANISO__MASK; 3091 } 3092 #define A3XX_TEX_SAMP_0_COMPARE_FUNC__MASK 0x00700000 3093 #define A3XX_TEX_SAMP_0_COMPARE_FUNC__SHIFT 20 3094 static inline uint32_t A3XX_TEX_SAMP_0_COMPARE_FUNC(enum adreno_compare_func val) 3095 { 3096 return ((val) << A3XX_TEX_SAMP_0_COMPARE_FUNC__SHIFT) & A3XX_TEX_SAMP_0_COMPARE_FUNC__MASK; 3097 } 3098 #define A3XX_TEX_SAMP_0_CUBEMAPSEAMLESSFILTOFF 0x01000000 3099 #define A3XX_TEX_SAMP_0_UNNORM_COORDS 0x80000000 3100 3101 #define REG_A3XX_TEX_SAMP_1 0x00000001 3102 #define A3XX_TEX_SAMP_1_LOD_BIAS__MASK 0x000007ff 3103 #define A3XX_TEX_SAMP_1_LOD_BIAS__SHIFT 0 3104 static inline uint32_t A3XX_TEX_SAMP_1_LOD_BIAS(float val) 3105 { 3106 return ((((int32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_LOD_BIAS__SHIFT) & A3XX_TEX_SAMP_1_LOD_BIAS__MASK; 3107 } 3108 #define A3XX_TEX_SAMP_1_MAX_LOD__MASK 0x003ff000 3109 #define A3XX_TEX_SAMP_1_MAX_LOD__SHIFT 12 3110 static inline uint32_t A3XX_TEX_SAMP_1_MAX_LOD(float val) 3111 { 3112 return ((((uint32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A3XX_TEX_SAMP_1_MAX_LOD__MASK; 3113 } 3114 #define A3XX_TEX_SAMP_1_MIN_LOD__MASK 0xffc00000 3115 #define A3XX_TEX_SAMP_1_MIN_LOD__SHIFT 22 3116 static inline uint32_t A3XX_TEX_SAMP_1_MIN_LOD(float val) 3117 { 3118 return ((((uint32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A3XX_TEX_SAMP_1_MIN_LOD__MASK; 3119 } 3120 3121 #define REG_A3XX_TEX_CONST_0 0x00000000 3122 #define A3XX_TEX_CONST_0_TILED 0x00000001 3123 #define A3XX_TEX_CONST_0_SRGB 0x00000004 3124 #define A3XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070 3125 #define A3XX_TEX_CONST_0_SWIZ_X__SHIFT 4 3126 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_X(enum a3xx_tex_swiz val) 3127 { 3128 return ((val) << A3XX_TEX_CONST_0_SWIZ_X__SHIFT) & A3XX_TEX_CONST_0_SWIZ_X__MASK; 3129 } 3130 #define A3XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380 3131 #define A3XX_TEX_CONST_0_SWIZ_Y__SHIFT 7 3132 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Y(enum a3xx_tex_swiz val) 3133 { 3134 return ((val) << A3XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A3XX_TEX_CONST_0_SWIZ_Y__MASK; 3135 } 3136 #define A3XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00 3137 #define A3XX_TEX_CONST_0_SWIZ_Z__SHIFT 10 3138 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Z(enum a3xx_tex_swiz val) 3139 { 3140 return ((val) << A3XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A3XX_TEX_CONST_0_SWIZ_Z__MASK; 3141 } 3142 #define A3XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000 3143 #define A3XX_TEX_CONST_0_SWIZ_W__SHIFT 13 3144 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_W(enum a3xx_tex_swiz val) 3145 { 3146 return ((val) << A3XX_TEX_CONST_0_SWIZ_W__SHIFT) & A3XX_TEX_CONST_0_SWIZ_W__MASK; 3147 } 3148 #define A3XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000 3149 #define A3XX_TEX_CONST_0_MIPLVLS__SHIFT 16 3150 static inline uint32_t A3XX_TEX_CONST_0_MIPLVLS(uint32_t val) 3151 { 3152 return ((val) << A3XX_TEX_CONST_0_MIPLVLS__SHIFT) & A3XX_TEX_CONST_0_MIPLVLS__MASK; 3153 } 3154 #define A3XX_TEX_CONST_0_MSAATEX__MASK 0x00300000 3155 #define A3XX_TEX_CONST_0_MSAATEX__SHIFT 20 3156 static inline uint32_t A3XX_TEX_CONST_0_MSAATEX(enum a3xx_tex_msaa val) 3157 { 3158 return ((val) << A3XX_TEX_CONST_0_MSAATEX__SHIFT) & A3XX_TEX_CONST_0_MSAATEX__MASK; 3159 } 3160 #define A3XX_TEX_CONST_0_FMT__MASK 0x1fc00000 3161 #define A3XX_TEX_CONST_0_FMT__SHIFT 22 3162 static inline uint32_t A3XX_TEX_CONST_0_FMT(enum a3xx_tex_fmt val) 3163 { 3164 return ((val) << A3XX_TEX_CONST_0_FMT__SHIFT) & A3XX_TEX_CONST_0_FMT__MASK; 3165 } 3166 #define A3XX_TEX_CONST_0_NOCONVERT 0x20000000 3167 #define A3XX_TEX_CONST_0_TYPE__MASK 0xc0000000 3168 #define A3XX_TEX_CONST_0_TYPE__SHIFT 30 3169 static inline uint32_t A3XX_TEX_CONST_0_TYPE(enum a3xx_tex_type val) 3170 { 3171 return ((val) << A3XX_TEX_CONST_0_TYPE__SHIFT) & A3XX_TEX_CONST_0_TYPE__MASK; 3172 } 3173 3174 #define REG_A3XX_TEX_CONST_1 0x00000001 3175 #define A3XX_TEX_CONST_1_HEIGHT__MASK 0x00003fff 3176 #define A3XX_TEX_CONST_1_HEIGHT__SHIFT 0 3177 static inline uint32_t A3XX_TEX_CONST_1_HEIGHT(uint32_t val) 3178 { 3179 return ((val) << A3XX_TEX_CONST_1_HEIGHT__SHIFT) & A3XX_TEX_CONST_1_HEIGHT__MASK; 3180 } 3181 #define A3XX_TEX_CONST_1_WIDTH__MASK 0x0fffc000 3182 #define A3XX_TEX_CONST_1_WIDTH__SHIFT 14 3183 static inline uint32_t A3XX_TEX_CONST_1_WIDTH(uint32_t val) 3184 { 3185 return ((val) << A3XX_TEX_CONST_1_WIDTH__SHIFT) & A3XX_TEX_CONST_1_WIDTH__MASK; 3186 } 3187 #define A3XX_TEX_CONST_1_FETCHSIZE__MASK 0xf0000000 3188 #define A3XX_TEX_CONST_1_FETCHSIZE__SHIFT 28 3189 static inline uint32_t A3XX_TEX_CONST_1_FETCHSIZE(enum a3xx_tex_fetchsize val) 3190 { 3191 return ((val) << A3XX_TEX_CONST_1_FETCHSIZE__SHIFT) & A3XX_TEX_CONST_1_FETCHSIZE__MASK; 3192 } 3193 3194 #define REG_A3XX_TEX_CONST_2 0x00000002 3195 #define A3XX_TEX_CONST_2_INDX__MASK 0x000001ff 3196 #define A3XX_TEX_CONST_2_INDX__SHIFT 0 3197 static inline uint32_t A3XX_TEX_CONST_2_INDX(uint32_t val) 3198 { 3199 return ((val) << A3XX_TEX_CONST_2_INDX__SHIFT) & A3XX_TEX_CONST_2_INDX__MASK; 3200 } 3201 #define A3XX_TEX_CONST_2_PITCH__MASK 0x3ffff000 3202 #define A3XX_TEX_CONST_2_PITCH__SHIFT 12 3203 static inline uint32_t A3XX_TEX_CONST_2_PITCH(uint32_t val) 3204 { 3205 return ((val) << A3XX_TEX_CONST_2_PITCH__SHIFT) & A3XX_TEX_CONST_2_PITCH__MASK; 3206 } 3207 #define A3XX_TEX_CONST_2_SWAP__MASK 0xc0000000 3208 #define A3XX_TEX_CONST_2_SWAP__SHIFT 30 3209 static inline uint32_t A3XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val) 3210 { 3211 return ((val) << A3XX_TEX_CONST_2_SWAP__SHIFT) & A3XX_TEX_CONST_2_SWAP__MASK; 3212 } 3213 3214 #define REG_A3XX_TEX_CONST_3 0x00000003 3215 #define A3XX_TEX_CONST_3_LAYERSZ1__MASK 0x0001ffff 3216 #define A3XX_TEX_CONST_3_LAYERSZ1__SHIFT 0 3217 static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ1(uint32_t val) 3218 { 3219 assert(!(val & 0xfff)); 3220 return ((val >> 12) << A3XX_TEX_CONST_3_LAYERSZ1__SHIFT) & A3XX_TEX_CONST_3_LAYERSZ1__MASK; 3221 } 3222 #define A3XX_TEX_CONST_3_DEPTH__MASK 0x0ffe0000 3223 #define A3XX_TEX_CONST_3_DEPTH__SHIFT 17 3224 static inline uint32_t A3XX_TEX_CONST_3_DEPTH(uint32_t val) 3225 { 3226 return ((val) << A3XX_TEX_CONST_3_DEPTH__SHIFT) & A3XX_TEX_CONST_3_DEPTH__MASK; 3227 } 3228 #define A3XX_TEX_CONST_3_LAYERSZ2__MASK 0xf0000000 3229 #define A3XX_TEX_CONST_3_LAYERSZ2__SHIFT 28 3230 static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ2(uint32_t val) 3231 { 3232 assert(!(val & 0xfff)); 3233 return ((val >> 12) << A3XX_TEX_CONST_3_LAYERSZ2__SHIFT) & A3XX_TEX_CONST_3_LAYERSZ2__MASK; 3234 } 3235 3236 3237 #endif /* A3XX_XML */ 3238
