1 /* ARM assembler/disassembler support. 2 Copyright (C) 2004-2016 Free Software Foundation, Inc. 3 4 This file is part of GDB and GAS. 5 6 GDB and GAS are free software; you can redistribute it and/or 7 modify it under the terms of the GNU General Public License as 8 published by the Free Software Foundation; either version 3, or (at 9 your option) any later version. 10 11 GDB and GAS are distributed in the hope that it will be useful, but 12 WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GDB or GAS; see the file COPYING3. If not, write to the 18 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, 19 MA 02110-1301, USA. */ 20 21 /* The following bitmasks control CPU extensions: */ 22 #define ARM_EXT_V1 0x00000001 /* All processors (core set). */ 23 #define ARM_EXT_V2 0x00000002 /* Multiply instructions. */ 24 #define ARM_EXT_V2S 0x00000004 /* SWP instructions. */ 25 #define ARM_EXT_V3 0x00000008 /* MSR MRS. */ 26 #define ARM_EXT_V3M 0x00000010 /* Allow long multiplies. */ 27 #define ARM_EXT_V4 0x00000020 /* Allow half word loads. */ 28 #define ARM_EXT_V4T 0x00000040 /* Thumb. */ 29 #define ARM_EXT_V5 0x00000080 /* Allow CLZ, etc. */ 30 #define ARM_EXT_V5T 0x00000100 /* Improved interworking. */ 31 #define ARM_EXT_V5ExP 0x00000200 /* DSP core set. */ 32 #define ARM_EXT_V5E 0x00000400 /* DSP Double transfers. */ 33 #define ARM_EXT_V5J 0x00000800 /* Jazelle extension. */ 34 #define ARM_EXT_V6 0x00001000 /* ARM V6. */ 35 #define ARM_EXT_V6K 0x00002000 /* ARM V6K. */ 36 #define ARM_EXT_V8 0x00004000 /* ARMv8 w/o atomics. */ 37 #define ARM_EXT_V6T2 0x00008000 /* Thumb-2. */ 38 #define ARM_EXT_DIV 0x00010000 /* Integer division. */ 39 /* The 'M' in Arm V7M stands for Microcontroller. 40 On earlier architecture variants it stands for Multiply. */ 41 #define ARM_EXT_V5E_NOTM 0x00020000 /* Arm V5E but not Arm V7M. */ 42 #define ARM_EXT_V6_NOTM 0x00040000 /* Arm V6 but not Arm V7M. */ 43 #define ARM_EXT_V7 0x00080000 /* Arm V7. */ 44 #define ARM_EXT_V7A 0x00100000 /* Arm V7A. */ 45 #define ARM_EXT_V7R 0x00200000 /* Arm V7R. */ 46 #define ARM_EXT_V7M 0x00400000 /* Arm V7M. */ 47 #define ARM_EXT_V6M 0x00800000 /* ARM V6M. */ 48 #define ARM_EXT_BARRIER 0x01000000 /* DSB/DMB/ISB. */ 49 #define ARM_EXT_THUMB_MSR 0x02000000 /* Thumb MSR/MRS. */ 50 #define ARM_EXT_V6_DSP 0x04000000 /* ARM v6 (DSP-related), 51 not in v7-M. */ 52 #define ARM_EXT_MP 0x08000000 /* Multiprocessing Extensions. */ 53 #define ARM_EXT_SEC 0x10000000 /* Security extensions. */ 54 #define ARM_EXT_OS 0x20000000 /* OS Extensions. */ 55 #define ARM_EXT_ADIV 0x40000000 /* Integer divide extensions in ARM 56 state. */ 57 #define ARM_EXT_VIRT 0x80000000 /* Virtualization extensions. */ 58 59 #define ARM_EXT2_PAN 0x00000001 /* PAN extension. */ 60 #define ARM_EXT2_V8_2A 0x00000002 /* ARM V8.2A. */ 61 #define ARM_EXT2_V8M 0x00000004 /* ARM V8M. */ 62 #define ARM_EXT2_ATOMICS 0x00000008 /* ARMv8 atomics. */ 63 #define ARM_EXT2_V6T2_V8M 0x00000010 /* V8M Baseline from V6T2. */ 64 #define ARM_EXT2_FP16_INST 0x00000020 /* ARM V8.2A FP16 instructions. */ 65 #define ARM_EXT2_V8M_MAIN 0x00000040 /* ARMv8-M Mainline. */ 66 #define ARM_EXT2_RAS 0x00000080 /* RAS extension. */ 67 68 /* Co-processor space extensions. */ 69 #define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */ 70 #define ARM_CEXT_MAVERICK 0x00000002 /* Use Cirrus/DSP coprocessor. */ 71 #define ARM_CEXT_IWMMXT 0x00000004 /* Intel Wireless MMX technology coprocessor. */ 72 #define ARM_CEXT_IWMMXT2 0x00000008 /* Intel Wireless MMX technology coprocessor version 2. */ 73 74 #define FPU_ENDIAN_PURE 0x80000000 /* Pure-endian doubles. */ 75 #define FPU_ENDIAN_BIG 0 /* Double words-big-endian. */ 76 #define FPU_FPA_EXT_V1 0x40000000 /* Base FPA instruction set. */ 77 #define FPU_FPA_EXT_V2 0x20000000 /* LFM/SFM. */ 78 #define FPU_MAVERICK 0x10000000 /* Cirrus Maverick. */ 79 #define FPU_VFP_EXT_V1xD 0x08000000 /* Base VFP instruction set. */ 80 #define FPU_VFP_EXT_V1 0x04000000 /* Double-precision insns. */ 81 #define FPU_VFP_EXT_V2 0x02000000 /* ARM10E VFPr1. */ 82 #define FPU_VFP_EXT_V3xD 0x01000000 /* VFPv3 single-precision. */ 83 #define FPU_VFP_EXT_V3 0x00800000 /* VFPv3 double-precision. */ 84 #define FPU_NEON_EXT_V1 0x00400000 /* Neon (SIMD) insns. */ 85 #define FPU_VFP_EXT_D32 0x00200000 /* Registers D16-D31. */ 86 #define FPU_VFP_EXT_FP16 0x00100000 /* Half-precision extensions. */ 87 #define FPU_NEON_EXT_FMA 0x00080000 /* Neon fused multiply-add */ 88 #define FPU_VFP_EXT_FMA 0x00040000 /* VFP fused multiply-add */ 89 #define FPU_VFP_EXT_ARMV8 0x00020000 /* Double-precision FP for ARMv8. */ 90 #define FPU_NEON_EXT_ARMV8 0x00010000 /* Neon for ARMv8. */ 91 #define FPU_CRYPTO_EXT_ARMV8 0x00008000 /* Crypto for ARMv8. */ 92 #define CRC_EXT_ARMV8 0x00004000 /* CRC32 for ARMv8. */ 93 #define FPU_VFP_EXT_ARMV8xD 0x00002000 /* Single-precision FP for ARMv8. */ 94 #define FPU_NEON_EXT_RDMA 0x00001000 /* v8.1 Adv.SIMD extensions. */ 95 96 /* Architectures are the sum of the base and extensions. The ARM ARM (rev E) 97 defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T, 98 ARMv5xM, ARMv5, ARMv5TxM, ARMv5T, ARMv5TExP, ARMv5TE. To these we add 99 three more to cover cores prior to ARM6. Finally, there are cores which 100 implement further extensions in the co-processor space. */ 101 #define ARM_AEXT_V1 ARM_EXT_V1 102 #define ARM_AEXT_V2 (ARM_AEXT_V1 | ARM_EXT_V2) 103 #define ARM_AEXT_V2S (ARM_AEXT_V2 | ARM_EXT_V2S) 104 #define ARM_AEXT_V3 (ARM_AEXT_V2S | ARM_EXT_V3) 105 #define ARM_AEXT_V3M (ARM_AEXT_V3 | ARM_EXT_V3M) 106 #define ARM_AEXT_V4xM (ARM_AEXT_V3 | ARM_EXT_V4) 107 #define ARM_AEXT_V4 (ARM_AEXT_V3M | ARM_EXT_V4) 108 #define ARM_AEXT_V4TxM (ARM_AEXT_V4xM | ARM_EXT_V4T) 109 #define ARM_AEXT_V4T (ARM_AEXT_V4 | ARM_EXT_V4T) 110 #define ARM_AEXT_V5xM (ARM_AEXT_V4xM | ARM_EXT_V5) 111 #define ARM_AEXT_V5 (ARM_AEXT_V4 | ARM_EXT_V5) 112 #define ARM_AEXT_V5TxM (ARM_AEXT_V5xM | ARM_EXT_V4T | ARM_EXT_V5T) 113 #define ARM_AEXT_V5T (ARM_AEXT_V5 | ARM_EXT_V4T | ARM_EXT_V5T) 114 #define ARM_AEXT_V5TExP (ARM_AEXT_V5T | ARM_EXT_V5ExP) 115 #define ARM_AEXT_V5TE (ARM_AEXT_V5TExP | ARM_EXT_V5E) 116 #define ARM_AEXT_V5TEJ (ARM_AEXT_V5TE | ARM_EXT_V5J) 117 #define ARM_AEXT_V6 (ARM_AEXT_V5TEJ | ARM_EXT_V6) 118 #define ARM_AEXT_V6K (ARM_AEXT_V6 | ARM_EXT_V6K) 119 #define ARM_AEXT_V6Z (ARM_AEXT_V6K | ARM_EXT_SEC) 120 #define ARM_AEXT_V6KZ (ARM_AEXT_V6K | ARM_EXT_SEC) 121 #define ARM_AEXT_V6T2 (ARM_AEXT_V6 \ 122 | ARM_EXT_V6T2 | ARM_EXT_V6_NOTM | ARM_EXT_THUMB_MSR \ 123 | ARM_EXT_V6_DSP ) 124 #define ARM_AEXT_V6KT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K) 125 #define ARM_AEXT_V6ZT2 (ARM_AEXT_V6T2 | ARM_EXT_SEC) 126 #define ARM_AEXT_V6KZT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K | ARM_EXT_SEC) 127 #define ARM_AEXT_V7_ARM (ARM_AEXT_V6KT2 | ARM_EXT_V7 | ARM_EXT_BARRIER) 128 #define ARM_AEXT_V7A (ARM_AEXT_V7_ARM | ARM_EXT_V7A) 129 #define ARM_AEXT_V7VE (ARM_AEXT_V7A | ARM_EXT_DIV | ARM_EXT_ADIV \ 130 | ARM_EXT_VIRT | ARM_EXT_SEC | ARM_EXT_MP) 131 #define ARM_AEXT_V7R (ARM_AEXT_V7_ARM | ARM_EXT_V7R | ARM_EXT_DIV) 132 #define ARM_AEXT_NOTM \ 133 (ARM_AEXT_V4 | ARM_EXT_V5ExP | ARM_EXT_V5J | ARM_EXT_V6_NOTM \ 134 | ARM_EXT_V6_DSP ) 135 #define ARM_AEXT_V6M_ONLY \ 136 ((ARM_EXT_BARRIER | ARM_EXT_V6M | ARM_EXT_THUMB_MSR) & ~(ARM_AEXT_NOTM)) 137 #define ARM_AEXT_V6M \ 138 ((ARM_AEXT_V6K | ARM_AEXT_V6M_ONLY) & ~(ARM_AEXT_NOTM)) 139 #define ARM_AEXT_V6SM (ARM_AEXT_V6M | ARM_EXT_OS) 140 #define ARM_AEXT_V7M \ 141 ((ARM_AEXT_V7_ARM | ARM_EXT_V6M | ARM_EXT_V7M | ARM_EXT_DIV) \ 142 & ~(ARM_AEXT_NOTM)) 143 #define ARM_AEXT_V7 (ARM_AEXT_V7A & ARM_AEXT_V7R & ARM_AEXT_V7M) 144 #define ARM_AEXT_V7EM \ 145 (ARM_AEXT_V7M | ARM_EXT_V5ExP | ARM_EXT_V6_DSP) 146 #define ARM_AEXT_V8A \ 147 (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC | ARM_EXT_DIV | ARM_EXT_ADIV \ 148 | ARM_EXT_VIRT | ARM_EXT_V8) 149 #define ARM_AEXT2_V8A (ARM_EXT2_V6T2_V8M | ARM_EXT2_ATOMICS) 150 #define ARM_AEXT2_V8_1A (ARM_AEXT2_V8A | ARM_EXT2_PAN) 151 #define ARM_AEXT2_V8_2A (ARM_AEXT2_V8_1A | ARM_EXT2_V8_2A | ARM_EXT2_RAS) 152 #define ARM_AEXT_V8M_BASE (ARM_AEXT_V6SM | ARM_EXT_DIV) 153 #define ARM_AEXT_V8M_MAIN ARM_AEXT_V7M 154 #define ARM_AEXT2_V8M (ARM_EXT2_V8M | ARM_EXT2_ATOMICS | ARM_EXT2_V6T2_V8M) 155 #define ARM_AEXT2_V8M_MAIN (ARM_AEXT2_V8M | ARM_EXT2_V8M_MAIN) 156 157 /* Processors with specific extensions in the co-processor space. */ 158 #define ARM_ARCH_XSCALE ARM_FEATURE_LOW (ARM_AEXT_V5TE, ARM_CEXT_XSCALE) 159 #define ARM_ARCH_IWMMXT \ 160 ARM_FEATURE_LOW (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT) 161 #define ARM_ARCH_IWMMXT2 \ 162 ARM_FEATURE_LOW (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT \ 163 | ARM_CEXT_IWMMXT2) 164 165 #define FPU_VFP_V1xD (FPU_VFP_EXT_V1xD | FPU_ENDIAN_PURE) 166 #define FPU_VFP_V1 (FPU_VFP_V1xD | FPU_VFP_EXT_V1) 167 #define FPU_VFP_V2 (FPU_VFP_V1 | FPU_VFP_EXT_V2) 168 #define FPU_VFP_V3D16 (FPU_VFP_V2 | FPU_VFP_EXT_V3xD | FPU_VFP_EXT_V3) 169 #define FPU_VFP_V3 (FPU_VFP_V3D16 | FPU_VFP_EXT_D32) 170 #define FPU_VFP_V3xD (FPU_VFP_V1xD | FPU_VFP_EXT_V2 | FPU_VFP_EXT_V3xD) 171 #define FPU_VFP_V4D16 (FPU_VFP_V3D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA) 172 #define FPU_VFP_V4 (FPU_VFP_V3 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA) 173 #define FPU_VFP_V4_SP_D16 (FPU_VFP_V3xD | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA) 174 #define FPU_VFP_V5D16 (FPU_VFP_V4D16 | FPU_VFP_EXT_ARMV8xD | FPU_VFP_EXT_ARMV8) 175 #define FPU_VFP_V5_SP_D16 (FPU_VFP_V4_SP_D16 | FPU_VFP_EXT_ARMV8xD) 176 #define FPU_VFP_ARMV8 (FPU_VFP_V4 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD) 177 #define FPU_NEON_ARMV8 (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA | FPU_NEON_EXT_ARMV8) 178 #define FPU_CRYPTO_ARMV8 (FPU_CRYPTO_EXT_ARMV8) 179 #define FPU_VFP_HARD (FPU_VFP_EXT_V1xD | FPU_VFP_EXT_V1 | FPU_VFP_EXT_V2 \ 180 | FPU_VFP_EXT_V3xD | FPU_VFP_EXT_FMA | FPU_NEON_EXT_FMA \ 181 | FPU_VFP_EXT_V3 | FPU_NEON_EXT_V1 | FPU_VFP_EXT_D32) 182 #define FPU_FPA (FPU_FPA_EXT_V1 | FPU_FPA_EXT_V2) 183 184 /* Deprecated. */ 185 #define FPU_ARCH_VFP ARM_FEATURE_COPROC (FPU_ENDIAN_PURE) 186 187 #define FPU_ARCH_FPE ARM_FEATURE_COPROC (FPU_FPA_EXT_V1) 188 #define FPU_ARCH_FPA ARM_FEATURE_COPROC (FPU_FPA) 189 190 #define FPU_ARCH_VFP_V1xD ARM_FEATURE_COPROC (FPU_VFP_V1xD) 191 #define FPU_ARCH_VFP_V1 ARM_FEATURE_COPROC (FPU_VFP_V1) 192 #define FPU_ARCH_VFP_V2 ARM_FEATURE_COPROC (FPU_VFP_V2) 193 #define FPU_ARCH_VFP_V3D16 ARM_FEATURE_COPROC (FPU_VFP_V3D16) 194 #define FPU_ARCH_VFP_V3D16_FP16 \ 195 ARM_FEATURE_COPROC (FPU_VFP_V3D16 | FPU_VFP_EXT_FP16) 196 #define FPU_ARCH_VFP_V3 ARM_FEATURE_COPROC (FPU_VFP_V3) 197 #define FPU_ARCH_VFP_V3_FP16 ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_VFP_EXT_FP16) 198 #define FPU_ARCH_VFP_V3xD ARM_FEATURE_COPROC (FPU_VFP_V3xD) 199 #define FPU_ARCH_VFP_V3xD_FP16 ARM_FEATURE_COPROC (FPU_VFP_V3xD \ 200 | FPU_VFP_EXT_FP16) 201 #define FPU_ARCH_NEON_V1 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1) 202 #define FPU_ARCH_VFP_V3_PLUS_NEON_V1 \ 203 ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1) 204 #define FPU_ARCH_NEON_FP16 \ 205 ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1 | FPU_VFP_EXT_FP16) 206 #define FPU_ARCH_VFP_HARD ARM_FEATURE_COPROC (FPU_VFP_HARD) 207 #define FPU_ARCH_VFP_V4 ARM_FEATURE_COPROC (FPU_VFP_V4) 208 #define FPU_ARCH_VFP_V4D16 ARM_FEATURE_COPROC (FPU_VFP_V4D16) 209 #define FPU_ARCH_VFP_V4_SP_D16 ARM_FEATURE_COPROC (FPU_VFP_V4_SP_D16) 210 #define FPU_ARCH_VFP_V5D16 ARM_FEATURE_COPROC (FPU_VFP_V5D16) 211 #define FPU_ARCH_VFP_V5_SP_D16 ARM_FEATURE_COPROC (FPU_VFP_V5_SP_D16) 212 #define FPU_ARCH_NEON_VFP_V4 \ 213 ARM_FEATURE_COPROC (FPU_VFP_V4 | FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA) 214 #define FPU_ARCH_VFP_ARMV8 ARM_FEATURE_COPROC (FPU_VFP_ARMV8) 215 #define FPU_ARCH_NEON_VFP_ARMV8 ARM_FEATURE_COPROC (FPU_NEON_ARMV8 \ 216 | FPU_VFP_ARMV8) 217 #define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8 \ 218 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8 | FPU_NEON_ARMV8 | FPU_VFP_ARMV8) 219 #define ARCH_CRC_ARMV8 ARM_FEATURE_COPROC (CRC_EXT_ARMV8) 220 #define FPU_ARCH_NEON_VFP_ARMV8_1 \ 221 ARM_FEATURE_COPROC (FPU_NEON_ARMV8 \ 222 | FPU_VFP_ARMV8 \ 223 | FPU_NEON_EXT_RDMA) 224 #define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1 \ 225 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8 | FPU_NEON_ARMV8 | FPU_VFP_ARMV8 \ 226 | FPU_NEON_EXT_RDMA) 227 228 229 #define FPU_ARCH_ENDIAN_PURE ARM_FEATURE_COPROC (FPU_ENDIAN_PURE) 230 231 #define FPU_ARCH_MAVERICK ARM_FEATURE_COPROC (FPU_MAVERICK) 232 233 #define ARM_ARCH_V1 ARM_FEATURE_CORE_LOW (ARM_AEXT_V1) 234 #define ARM_ARCH_V2 ARM_FEATURE_CORE_LOW (ARM_AEXT_V2) 235 #define ARM_ARCH_V2S ARM_FEATURE_CORE_LOW (ARM_AEXT_V2S) 236 #define ARM_ARCH_V3 ARM_FEATURE_CORE_LOW (ARM_AEXT_V3) 237 #define ARM_ARCH_V3M ARM_FEATURE_CORE_LOW (ARM_AEXT_V3M) 238 #define ARM_ARCH_V4xM ARM_FEATURE_CORE_LOW (ARM_AEXT_V4xM) 239 #define ARM_ARCH_V4 ARM_FEATURE_CORE_LOW (ARM_AEXT_V4) 240 #define ARM_ARCH_V4TxM ARM_FEATURE_CORE_LOW (ARM_AEXT_V4TxM) 241 #define ARM_ARCH_V4T ARM_FEATURE_CORE_LOW (ARM_AEXT_V4T) 242 #define ARM_ARCH_V5xM ARM_FEATURE_CORE_LOW (ARM_AEXT_V5xM) 243 #define ARM_ARCH_V5 ARM_FEATURE_CORE_LOW (ARM_AEXT_V5) 244 #define ARM_ARCH_V5TxM ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TxM) 245 #define ARM_ARCH_V5T ARM_FEATURE_CORE_LOW (ARM_AEXT_V5T) 246 #define ARM_ARCH_V5TExP ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TExP) 247 #define ARM_ARCH_V5TE ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TE) 248 #define ARM_ARCH_V5TEJ ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TEJ) 249 #define ARM_ARCH_V6 ARM_FEATURE_CORE_LOW (ARM_AEXT_V6) 250 #define ARM_ARCH_V6K ARM_FEATURE_CORE_LOW (ARM_AEXT_V6K) 251 #define ARM_ARCH_V6Z ARM_FEATURE_CORE_LOW (ARM_AEXT_V6Z) 252 #define ARM_ARCH_V6KZ ARM_FEATURE_CORE_LOW (ARM_AEXT_V6KZ) 253 #define ARM_ARCH_V6T2 ARM_FEATURE_CORE (ARM_AEXT_V6T2, ARM_EXT2_V6T2_V8M) 254 #define ARM_ARCH_V6KT2 ARM_FEATURE_CORE (ARM_AEXT_V6KT2, ARM_EXT2_V6T2_V8M) 255 #define ARM_ARCH_V6ZT2 ARM_FEATURE_CORE (ARM_AEXT_V6ZT2, ARM_EXT2_V6T2_V8M) 256 #define ARM_ARCH_V6KZT2 ARM_FEATURE_CORE (ARM_AEXT_V6KZT2, ARM_EXT2_V6T2_V8M) 257 #define ARM_ARCH_V6M ARM_FEATURE_CORE_LOW (ARM_AEXT_V6M) 258 #define ARM_ARCH_V6SM ARM_FEATURE_CORE_LOW (ARM_AEXT_V6SM) 259 #define ARM_ARCH_V7 ARM_FEATURE_CORE (ARM_AEXT_V7, ARM_EXT2_V6T2_V8M) 260 #define ARM_ARCH_V7A ARM_FEATURE_CORE (ARM_AEXT_V7A, ARM_EXT2_V6T2_V8M) 261 #define ARM_ARCH_V7VE ARM_FEATURE_CORE (ARM_AEXT_V7VE, ARM_EXT2_V6T2_V8M) 262 #define ARM_ARCH_V7R ARM_FEATURE_CORE (ARM_AEXT_V7R, ARM_EXT2_V6T2_V8M) 263 #define ARM_ARCH_V7M ARM_FEATURE_CORE (ARM_AEXT_V7M, ARM_EXT2_V6T2_V8M) 264 #define ARM_ARCH_V7EM ARM_FEATURE_CORE (ARM_AEXT_V7EM, ARM_EXT2_V6T2_V8M) 265 #define ARM_ARCH_V8A ARM_FEATURE_CORE (ARM_AEXT_V8A, ARM_AEXT2_V8A) 266 #define ARM_ARCH_V8_1A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_1A, \ 267 CRC_EXT_ARMV8 | FPU_NEON_EXT_RDMA) 268 #define ARM_ARCH_V8_2A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_2A, \ 269 CRC_EXT_ARMV8 | FPU_NEON_EXT_RDMA) 270 #define ARM_ARCH_V8M_BASE ARM_FEATURE_CORE (ARM_AEXT_V8M_BASE, ARM_AEXT2_V8M) 271 #define ARM_ARCH_V8M_MAIN ARM_FEATURE_CORE (ARM_AEXT_V8M_MAIN, \ 272 ARM_AEXT2_V8M_MAIN) 273 274 /* Some useful combinations: */ 275 #define ARM_ARCH_NONE ARM_FEATURE_LOW (0, 0) 276 #define FPU_NONE ARM_FEATURE_LOW (0, 0) 277 #define ARM_ANY ARM_FEATURE (-1, -1, 0) /* Any basic core. */ 278 #define ARM_FEATURE_ALL ARM_FEATURE (-1, -1, -1)/* All CPU and FPU features. */ 279 #define FPU_ANY_HARD ARM_FEATURE_COPROC (FPU_FPA | FPU_VFP_HARD | FPU_MAVERICK) 280 /* Extensions containing some Thumb-2 instructions. If any is present, Thumb 281 ISA is Thumb-2. */ 282 #define ARM_ARCH_THUMB2 ARM_FEATURE_CORE (ARM_EXT_V6T2 | ARM_EXT_V7 \ 283 | ARM_EXT_DIV | ARM_EXT_V8, \ 284 ARM_EXT2_ATOMICS | ARM_EXT2_V6T2_V8M) 285 /* v7-a+sec. */ 286 #define ARM_ARCH_V7A_SEC \ 287 ARM_FEATURE_CORE (ARM_AEXT_V7A | ARM_EXT_SEC, ARM_EXT2_V6T2_V8M) 288 /* v7-a+mp+sec. */ 289 #define ARM_ARCH_V7A_MP_SEC \ 290 ARM_FEATURE_CORE (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC, ARM_EXT2_V6T2_V8M) 291 /* v7-r+idiv. */ 292 #define ARM_ARCH_V7R_IDIV \ 293 ARM_FEATURE_CORE (ARM_AEXT_V7R | ARM_EXT_ADIV, ARM_EXT2_V6T2_V8M) 294 /* Features that are present in v6M and v6S-M but not other v6 cores. */ 295 #define ARM_ARCH_V6M_ONLY ARM_FEATURE_CORE_LOW (ARM_AEXT_V6M_ONLY) 296 /* v8-a+fp. */ 297 #define ARM_ARCH_V8A_FP \ 298 ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8A, FPU_ARCH_VFP_ARMV8) 299 /* v8-a+simd (implies fp). */ 300 #define ARM_ARCH_V8A_SIMD \ 301 ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8A, FPU_ARCH_NEON_VFP_ARMV8) 302 /* v8-a+crypto (implies simd+fp). */ 303 #define ARM_ARCH_V8A_CRYPTOV1 \ 304 ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8) 305 306 /* v8.1-a+fp. */ 307 #define ARM_ARCH_V8_1A_FP \ 308 ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_1A, FPU_ARCH_VFP_ARMV8) 309 /* v8.1-a+simd (implies fp). */ 310 #define ARM_ARCH_V8_1A_SIMD \ 311 ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_1A, FPU_ARCH_NEON_VFP_ARMV8_1) 312 /* v8.1-a+crypto (implies simd+fp). */ 313 #define ARM_ARCH_V8_1A_CRYPTOV1 \ 314 ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_1A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1) 315 316 317 /* There are too many feature bits to fit in a single word, so use a 318 structure. For simplicity we put all core features in array CORE 319 and everything else in the other. All the bits in element core[0] 320 have been occupied, so new feature should use bit in element core[1] 321 and use macro ARM_FEATURE to initialize the feature set variable. */ 322 typedef struct 323 { 324 unsigned long core[2]; 325 unsigned long coproc; 326 } arm_feature_set; 327 328 /* Test whether CPU and FEAT have any features in common. */ 329 #define ARM_CPU_HAS_FEATURE(CPU,FEAT) \ 330 (((CPU).core[0] & (FEAT).core[0]) != 0 \ 331 || ((CPU).core[1] & (FEAT).core[1]) != 0 \ 332 || ((CPU).coproc & (FEAT).coproc) != 0) 333 334 /* Tests whether the features of A are a subset of B. */ 335 #define ARM_FSET_CPU_SUBSET(A,B) \ 336 (((A).core[0] & (B).core[0]) == (A).core[0] \ 337 && ((A).core[1] & (B).core[1]) == (A).core[1] \ 338 && ((A).coproc & (B).coproc) == (A).coproc) 339 340 #define ARM_CPU_IS_ANY(CPU) \ 341 ((CPU).core[0] == ((arm_feature_set)ARM_ANY).core[0] \ 342 && (CPU).core[1] == ((arm_feature_set)ARM_ANY).core[1]) 343 344 #define ARM_MERGE_FEATURE_SETS(TARG,F1,F2) \ 345 do { \ 346 (TARG).core[0] = (F1).core[0] | (F2).core[0];\ 347 (TARG).core[1] = (F1).core[1] | (F2).core[1];\ 348 (TARG).coproc = (F1).coproc | (F2).coproc; \ 349 } while (0) 350 351 #define ARM_CLEAR_FEATURE(TARG,F1,F2) \ 352 do { \ 353 (TARG).core[0] = (F1).core[0] &~ (F2).core[0];\ 354 (TARG).core[1] = (F1).core[1] &~ (F2).core[1];\ 355 (TARG).coproc = (F1).coproc &~ (F2).coproc; \ 356 } while (0) 357 358 #define ARM_FEATURE_COPY(F1, F2) \ 359 do { \ 360 (F1).core[0] = (F2).core[0]; \ 361 (F1).core[1] = (F2).core[1]; \ 362 (F1).coproc = (F2).coproc; \ 363 } while (0) 364 365 #define ARM_FEATURE_EQUAL(T1,T2) \ 366 ((T1).core[0] == (T2).core[0] \ 367 && (T1).core[1] == (T2).core[1] \ 368 && (T1).coproc == (T2).coproc) 369 370 #define ARM_FEATURE_ZERO(T) \ 371 ((T).core[0] == 0 && (T).core[1] == 0 && (T).coproc == 0) 372 373 #define ARM_FEATURE_CORE_EQUAL(T1, T2) \ 374 ((T1).core[0] == (T2).core[0] && (T1).core[1] == (T2).core[1]) 375 376 #define ARM_FEATURE_LOW(core, coproc) {{(core), 0}, (coproc)} 377 #define ARM_FEATURE_CORE(core1, core2) {{(core1), (core2)}, 0} 378 #define ARM_FEATURE_CORE_LOW(core) {{(core), 0}, 0} 379 #define ARM_FEATURE_CORE_HIGH(core) {{0, (core)}, 0} 380 #define ARM_FEATURE_COPROC(coproc) {{0, 0}, (coproc)} 381 #define ARM_FEATURE(core1, core2, coproc) {{(core1), (core2)}, (coproc)} 382
