1 /** @file 2 * 3 * Copyright (c) 2011-2015, ARM Limited. All rights reserved. 4 * 5 * This program and the accompanying materials 6 * are licensed and made available under the terms and conditions of the BSD License 7 * which accompanies this distribution. The full text of the license may be found at 8 * http://opensource.org/licenses/bsd-license.php 9 * 10 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 * 13 **/ 14 15 #ifndef __ARMGIC_H 16 #define __ARMGIC_H 17 18 #include <Library/ArmGicArchLib.h> 19 20 // 21 // GIC Distributor 22 // 23 #define ARM_GIC_ICDDCR 0x000 // Distributor Control Register 24 #define ARM_GIC_ICDICTR 0x004 // Interrupt Controller Type Register 25 #define ARM_GIC_ICDIIDR 0x008 // Implementer Identification Register 26 27 // Each reg base below repeats for Number of interrupts / 4 (see GIC spec) 28 #define ARM_GIC_ICDISR 0x080 // Interrupt Security Registers 29 #define ARM_GIC_ICDISER 0x100 // Interrupt Set-Enable Registers 30 #define ARM_GIC_ICDICER 0x180 // Interrupt Clear-Enable Registers 31 #define ARM_GIC_ICDSPR 0x200 // Interrupt Set-Pending Registers 32 #define ARM_GIC_ICDICPR 0x280 // Interrupt Clear-Pending Registers 33 #define ARM_GIC_ICDABR 0x300 // Active Bit Registers 34 35 // Each reg base below repeats for Number of interrupts / 4 36 #define ARM_GIC_ICDIPR 0x400 // Interrupt Priority Registers 37 38 // Each reg base below repeats for Number of interrupts 39 #define ARM_GIC_ICDIPTR 0x800 // Interrupt Processor Target Registers 40 #define ARM_GIC_ICDICFR 0xC00 // Interrupt Configuration Registers 41 42 #define ARM_GIC_ICDPPISR 0xD00 // PPI Status register 43 44 // just one of these 45 #define ARM_GIC_ICDSGIR 0xF00 // Software Generated Interrupt Register 46 47 // GICv3 specific registers 48 #define ARM_GICD_IROUTER 0x6100 // Interrupt Routing Registers 49 50 // GICD_CTLR bits 51 #define ARM_GIC_ICDDCR_ARE (1 << 4) // Affinity Routing Enable (ARE) 52 #define ARM_GIC_ICDDCR_DS (1 << 6) // Disable Security (DS) 53 54 // 55 // GIC Redistributor 56 // 57 58 #define ARM_GICR_CTLR_FRAME_SIZE SIZE_64KB 59 #define ARM_GICR_SGI_PPI_FRAME_SIZE SIZE_64KB 60 61 // GIC Redistributor Control frame 62 #define ARM_GICR_TYPER 0x0008 // Redistributor Type Register 63 64 // GIC SGI & PPI Redistributor frame 65 #define ARM_GICR_ISENABLER 0x0100 // Interrupt Set-Enable Registers 66 #define ARM_GICR_ICENABLER 0x0180 // Interrupt Clear-Enable Registers 67 68 // 69 // GIC Cpu interface 70 // 71 #define ARM_GIC_ICCICR 0x00 // CPU Interface Control Register 72 #define ARM_GIC_ICCPMR 0x04 // Interrupt Priority Mask Register 73 #define ARM_GIC_ICCBPR 0x08 // Binary Point Register 74 #define ARM_GIC_ICCIAR 0x0C // Interrupt Acknowledge Register 75 #define ARM_GIC_ICCEIOR 0x10 // End Of Interrupt Register 76 #define ARM_GIC_ICCRPR 0x14 // Running Priority Register 77 #define ARM_GIC_ICCPIR 0x18 // Highest Pending Interrupt Register 78 #define ARM_GIC_ICCABPR 0x1C // Aliased Binary Point Register 79 #define ARM_GIC_ICCIIDR 0xFC // Identification Register 80 81 #define ARM_GIC_ICDSGIR_FILTER_TARGETLIST 0x0 82 #define ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE 0x1 83 #define ARM_GIC_ICDSGIR_FILTER_ITSELF 0x2 84 85 // Bit-masks to configure the CPU Interface Control register 86 #define ARM_GIC_ICCICR_ENABLE_SECURE 0x01 87 #define ARM_GIC_ICCICR_ENABLE_NS 0x02 88 #define ARM_GIC_ICCICR_ACK_CTL 0x04 89 #define ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ 0x08 90 #define ARM_GIC_ICCICR_USE_SBPR 0x10 91 92 // Bit Mask for GICC_IIDR 93 #define ARM_GIC_ICCIIDR_GET_PRODUCT_ID(IccIidr) (((IccIidr) >> 20) & 0xFFF) 94 #define ARM_GIC_ICCIIDR_GET_ARCH_VERSION(IccIidr) (((IccIidr) >> 16) & 0xF) 95 #define ARM_GIC_ICCIIDR_GET_REVISION(IccIidr) (((IccIidr) >> 12) & 0xF) 96 #define ARM_GIC_ICCIIDR_GET_IMPLEMENTER(IccIidr) ((IccIidr) & 0xFFF) 97 98 // Bit Mask for 99 #define ARM_GIC_ICCIAR_ACKINTID 0x3FF 100 101 UINTN 102 EFIAPI 103 ArmGicGetInterfaceIdentification ( 104 IN INTN GicInterruptInterfaceBase 105 ); 106 107 // 108 // GIC Secure interfaces 109 // 110 VOID 111 EFIAPI 112 ArmGicSetupNonSecure ( 113 IN UINTN MpId, 114 IN INTN GicDistributorBase, 115 IN INTN GicInterruptInterfaceBase 116 ); 117 118 VOID 119 EFIAPI 120 ArmGicSetSecureInterrupts ( 121 IN UINTN GicDistributorBase, 122 IN UINTN* GicSecureInterruptMask, 123 IN UINTN GicSecureInterruptMaskSize 124 ); 125 126 VOID 127 EFIAPI 128 ArmGicEnableInterruptInterface ( 129 IN INTN GicInterruptInterfaceBase 130 ); 131 132 VOID 133 EFIAPI 134 ArmGicDisableInterruptInterface ( 135 IN INTN GicInterruptInterfaceBase 136 ); 137 138 VOID 139 EFIAPI 140 ArmGicEnableDistributor ( 141 IN INTN GicDistributorBase 142 ); 143 144 VOID 145 EFIAPI 146 ArmGicDisableDistributor ( 147 IN INTN GicDistributorBase 148 ); 149 150 UINTN 151 EFIAPI 152 ArmGicGetMaxNumInterrupts ( 153 IN INTN GicDistributorBase 154 ); 155 156 VOID 157 EFIAPI 158 ArmGicSendSgiTo ( 159 IN INTN GicDistributorBase, 160 IN INTN TargetListFilter, 161 IN INTN CPUTargetList, 162 IN INTN SgiId 163 ); 164 165 /* 166 * Acknowledge and return the value of the Interrupt Acknowledge Register 167 * 168 * InterruptId is returned separately from the register value because in 169 * the GICv2 the register value contains the CpuId and InterruptId while 170 * in the GICv3 the register value is only the InterruptId. 171 * 172 * @param GicInterruptInterfaceBase Base Address of the GIC CPU Interface 173 * @param InterruptId InterruptId read from the Interrupt Acknowledge Register 174 * 175 * @retval value returned by the Interrupt Acknowledge Register 176 * 177 */ 178 UINTN 179 EFIAPI 180 ArmGicAcknowledgeInterrupt ( 181 IN UINTN GicInterruptInterfaceBase, 182 OUT UINTN *InterruptId 183 ); 184 185 VOID 186 EFIAPI 187 ArmGicEndOfInterrupt ( 188 IN UINTN GicInterruptInterfaceBase, 189 IN UINTN Source 190 ); 191 192 UINTN 193 EFIAPI 194 ArmGicSetPriorityMask ( 195 IN INTN GicInterruptInterfaceBase, 196 IN INTN PriorityMask 197 ); 198 199 VOID 200 EFIAPI 201 ArmGicEnableInterrupt ( 202 IN UINTN GicDistributorBase, 203 IN UINTN GicRedistributorBase, 204 IN UINTN Source 205 ); 206 207 VOID 208 EFIAPI 209 ArmGicDisableInterrupt ( 210 IN UINTN GicDistributorBase, 211 IN UINTN GicRedistributorBase, 212 IN UINTN Source 213 ); 214 215 BOOLEAN 216 EFIAPI 217 ArmGicIsInterruptEnabled ( 218 IN UINTN GicDistributorBase, 219 IN UINTN GicRedistributorBase, 220 IN UINTN Source 221 ); 222 223 // 224 // GIC revision 2 specific declarations 225 // 226 227 // Interrupts from 1020 to 1023 are considered as special interrupts (eg: spurious interrupts) 228 #define ARM_GIC_IS_SPECIAL_INTERRUPTS(Interrupt) (((Interrupt) >= 1020) && ((Interrupt) <= 1023)) 229 230 VOID 231 EFIAPI 232 ArmGicV2SetupNonSecure ( 233 IN UINTN MpId, 234 IN INTN GicDistributorBase, 235 IN INTN GicInterruptInterfaceBase 236 ); 237 238 VOID 239 EFIAPI 240 ArmGicV2EnableInterruptInterface ( 241 IN INTN GicInterruptInterfaceBase 242 ); 243 244 VOID 245 EFIAPI 246 ArmGicV2DisableInterruptInterface ( 247 IN INTN GicInterruptInterfaceBase 248 ); 249 250 UINTN 251 EFIAPI 252 ArmGicV2AcknowledgeInterrupt ( 253 IN UINTN GicInterruptInterfaceBase 254 ); 255 256 VOID 257 EFIAPI 258 ArmGicV2EndOfInterrupt ( 259 IN UINTN GicInterruptInterfaceBase, 260 IN UINTN Source 261 ); 262 263 // 264 // GIC revision 3 specific declarations 265 // 266 267 #define ICC_SRE_EL2_SRE (1 << 0) 268 269 #define ARM_GICD_IROUTER_IRM BIT31 270 271 UINT32 272 EFIAPI 273 ArmGicV3GetControlSystemRegisterEnable ( 274 VOID 275 ); 276 277 VOID 278 EFIAPI 279 ArmGicV3SetControlSystemRegisterEnable ( 280 IN UINT32 ControlSystemRegisterEnable 281 ); 282 283 VOID 284 EFIAPI 285 ArmGicV3EnableInterruptInterface ( 286 VOID 287 ); 288 289 VOID 290 EFIAPI 291 ArmGicV3DisableInterruptInterface ( 292 VOID 293 ); 294 295 UINTN 296 EFIAPI 297 ArmGicV3AcknowledgeInterrupt ( 298 VOID 299 ); 300 301 VOID 302 EFIAPI 303 ArmGicV3EndOfInterrupt ( 304 IN UINTN Source 305 ); 306 307 VOID 308 ArmGicV3SetBinaryPointer ( 309 IN UINTN BinaryPoint 310 ); 311 312 VOID 313 ArmGicV3SetPriorityMask ( 314 IN UINTN Priority 315 ); 316 317 #endif 318
