1 /** 2 3 Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved 4 5 This program and the accompanying materials are licensed and made available under 6 the terms and conditions of the BSD License that accompanies this distribution. 7 The full text of the license may be found at 8 http://opensource.org/licenses/bsd-license.php. 9 10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 13 14 15 @file 16 PchRegsSata.h 17 18 @brief 19 Register names for VLV SATA controllers 20 21 Conventions: 22 23 - Prefixes: 24 Definitions beginning with "R_" are registers 25 Definitions beginning with "B_" are bits within registers 26 Definitions beginning with "V_" are meaningful values of bits within the registers 27 Definitions beginning with "S_" are register sizes 28 Definitions beginning with "N_" are the bit position 29 - In general, PCH registers are denoted by "_PCH_" in register names 30 - Registers / bits that are different between PCH generations are denoted by 31 "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_" 32 - Registers / bits that are different between SKUs are denoted by "_<SKU_name>" 33 at the end of the register/bit names 34 - Registers / bits of new devices introduced in a PCH generation will be just named 35 as "_PCH_" without <generation_name> inserted. 36 37 **/ 38 #ifndef _PCH_REGS_SATA_H_ 39 #define _PCH_REGS_SATA_H_ 40 41 /// 42 /// VLV SATA Message Bus 43 /// 44 #define PCH_SATA_PHY_PORT_ID 0xA3 // SATA PHY Port ID 45 #define PCH_SATA_PHY_MMIO_READ_OPCODE 0x00 // CUnit to SATA PHY MMIO Read Opcode 46 #define PCH_SATA_PHY_MMIO_WRITE_OPCODE 0x01 // CUnit to SATA PHY MMIO Write Opcode 47 48 /// 49 /// SATA Controller Registers (D19:F0) 50 /// 51 #define PCI_DEVICE_NUMBER_PCH_SATA 19 52 #define PCI_FUNCTION_NUMBER_PCH_SATA 0 53 54 #define R_PCH_SATA_ID 0x00 // Identifiers 55 #define B_PCH_SATA_ID_DID 0xFFFF0000 // Device ID 56 #define B_PCH_SATA_ID_VID 0x0000FFFF // Vendor ID 57 #define V_PCH_SATA_VENDOR_ID V_PCH_INTEL_VENDOR_ID 58 #define V_PCH_SATA_DEVICE_ID_D_IDE 0x0F20 // Desktop IDE Mode (Ports 0 and 1) 59 #define V_PCH_SATA_DEVICE_ID_D_AHCI 0x0F22 // Desktop AHCI Mode (Ports 0 and 1) 60 #define V_PCH_SATA_DEVICE_ID_D_RAID 0x2822 // Desktop RAID 0/1/5/10 Mode, based on D19:F0:9Ch[7] 61 62 #define V_PCH_SATA_DEVICE_ID_M_IDE 0x0F21 // Mobile IDE Mode (Ports 0 and 1) 63 #define V_PCH_SATA_DEVICE_ID_M_AHCI 0x0F23 // Mobile AHCI Mode (Ports 0 and 1) 64 #define V_PCH_SATA_DEVICE_ID_M_RAID 0x282A // Mobile RAID 0/1/5/10 Mode, based on D19:F0:9Ch[7] 65 66 #define R_PCH_SATA_COMMAND 0x04 // Command 67 #define B_PCH_SATA_COMMAND_INT_DIS BIT10 // Interrupt Disable 68 #define B_PCH_SATA_COMMAND_FBE BIT9 // Fast Back-to-back Enable 69 #define B_PCH_SATA_COMMAND_SERR_EN BIT8 // SERR# Enable 70 #define B_PCH_SATA_COMMAND_WCC BIT7 // Wait Cycle Enable 71 #define B_PCH_SATA_COMMAND_PER BIT6 // Parity Error Response Enable 72 #define B_PCH_SATA_COMMAND_VPS BIT5 // VGA Palette Snooping Enable 73 #define B_PCH_SATA_COMMAND_PMWE BIT4 // Memory Write and Invalidate Enable 74 #define B_PCH_SATA_COMMAND_SCE BIT3 // Special Cycle Enable 75 #define B_PCH_SATA_COMMAND_BME BIT2 // Bus Master Enable 76 #define B_PCH_SATA_COMMAND_MSE BIT1 // Memory Space Enable 77 #define B_PCH_SATA_COMMAND_IOSE BIT0 // I/O Space Enable 78 79 #define R_PCH_SATA_PCISTS 0x06 // Device Status 80 #define B_PCH_SATA_PCISTS_DPE BIT15 // Detected Parity Error 81 #define B_PCH_SATA_PCISTS_SSE BIT14 // Signaled System Error 82 #define B_PCH_SATA_PCISTS_RMA BIT13 // Received Master-Abort Status 83 #define B_PCH_SATA_PCISTS_RTA BIT12 // Received Target-Abort Status 84 #define B_PCH_SATA_PCISTS_STA BIT11 // Signaled Target-Abort Status 85 #define B_PCH_SATA_PCISTS_DEV_STS_MASK (BIT10 | BIT9) // DEVSEL# Timing Status 86 #define B_PCH_SATA_PCISTS_DPED BIT8 // Master Data Parity Error Detected 87 #define B_PCH_SATA_PCISTS_CAP_LIST BIT4 // Capabilities List 88 #define B_PCH_SATA_PCISTS_ITNS BIT3 // Interrupt Status 89 90 #define R_PCH_SATA_RID 0x08 // Revision ID (8 bits) 91 92 #define R_PCH_SATA_PI_REGISTER 0x09 // Programming Interface (8 bits) 93 #define B_PCH_SATA_PI_REGISTER_SNC BIT3 // Secondary Mode Native Capable 94 #define B_PCH_SATA_PI_REGISTER_SNE BIT2 // Secondary Mode Native Enable 95 #define B_PCH_SATA_PI_REGISTER_PNC BIT1 // Primary Mode Native Capable 96 #define B_PCH_SATA_PI_REGISTER_PNE BIT0 // Primary Mode Native Enable 97 98 #define R_PCH_SATA_CC 0x0A // Class Code 99 #define B_PCH_SATA_CC_BCC 0xFF00 // Base Class Code 100 #define B_PCH_SATA_CC_SCC 0x00FF // Sub Class Code 101 #define V_PCH_SATA_CC_SCC_IDE 0x01 102 #define V_PCH_SATA_CC_SCC_AHCI 0x06 103 #define V_PCH_SATA_CC_SCC_RAID 0x04 104 105 #define R_PCH_SATA_CLS 0x0C // Cache Line Size (8 bits) 106 #define B_PCH_SATA_CLS 0xFF 107 108 #define R_PCH_SATA_MLT 0x0D // Master Latency Timer (8 bits) 109 #define B_PCH_SATA_MLT 0xFF 110 111 #define R_PCH_SATA_HTYPE 0x0E // Header Type 112 #define B_PCH_SATA_HTYPE_MFD BIT7 // Multi-function Device 113 #define B_PCH_SATA_HTYPE_HL 0x7F // Header Layout 114 115 #define R_PCH_SATA_PCMD_BAR 0x10 // Primary Command Block Base Address 116 #define B_PCH_SATA_PCMD_BAR_BA 0x0000FFF8 // Base Address 117 #define B_PCH_SATA_PCMD_BAR_RTE BIT0 // Resource Type Indicator 118 119 #define R_PCH_SATA_PCTL_BAR 0x14 // Primary Control Block Base Address 120 #define B_PCH_SATA_PCTL_BAR_BA 0x0000FFFC // Base Address 121 #define B_PCH_SATA_PCTL_BAR_RTE BIT0 // Resource Type Indicator 122 123 #define R_PCH_SATA_SCMD_BAR 0x18 // Secondary Command Block Base Address 124 #define B_PCH_SATA_SCMD_BAR_BA 0x0000FFF8 // Base Address 125 #define B_PCH_SATA_SCMD_BAR_RTE BIT0 // Resource Type Indicator 126 127 #define R_PCH_SATA_SCTL_BAR 0x1C // Secondary Control Block Base Address 128 #define B_PCH_SATA_SCTL_BAR_BA 0x0000FFFC // Base Address 129 #define B_PCH_SATA_SCTL_BAR_RTE BIT0 // Resource Type Indicator 130 131 #define R_PCH_SATA_LBAR 0x20 // Legacy IDE Base Address / AHCI Index Data Pair Base Address 132 #define B_PCH_SATA_LBAR_BA 0x0000FFE0 // Base Address 133 #define B_PCH_SATA_LBAR_BA4 BIT4 // Base Address 4 134 #define B_PCH_SATA_LBAR_RTE BIT0 // Resource Type Indicator 135 136 #define R_PCH_SATA_SIDPBA 0x24 // Serial ATA Index Data Pair Base Address 137 #define R_PCH_SATA_ABAR 0x24 // AHCI Base Address 138 #define B_PCH_SATA_ABAR_BA 0xFFFFF800 // AHCI Memory Base Address (When CC.SCC not equal 0x01) 139 #define V_PCH_SATA_ABAR_LENGTH 0x800 // AHCI Memory Length (When CC.SCC not equal 0x01) 140 #define N_PCH_SATA_ABAR_ALIGNMENT 11 // AHCI Base Address Alignment (When CC.SCC not equal 0x01) 141 #define B_PCH_SATA_SIDPBA_BA 0x0000FFF0 // Serial ATA Index Data Pair IO Base Address (When CC.SCC equal 0x01) 142 #define V_PCH_SATA_SIDPBA_LENGTH 0x10 // Serial ATA Index Data Pair IO Length (When CC.SCC equal 0x01) 143 #define N_PCH_SATA_SIDPBA_ALIGNMENT 4 // Serial ATA Index Data Pair Base Address Alignment (When CC.SCC not equal 0x01) 144 #define B_PCH_SATA_ABAR_PF BIT3 // Prefetchable 145 #define B_PCH_SATA_ABAR_TP (BIT2 | BIT1) // Type 146 #define B_PCH_SATA_ABAR_RTE BIT0 // Resource Type Indicator 147 148 #define R_PCH_SATA_SS 0x2C // Sub System Identifiers 149 #define B_PCH_SATA_SS_SSID 0xFFFF0000 // Subsystem ID 150 #define B_PCH_SATA_SS_SSVID 0x0000FFFF // Subsystem Vendor ID 151 152 #define R_PCH_SATA_AHCI_CAP_PTR 0x34 // Capabilities Pointer (8 bits) 153 #define B_PCH_SATA_AHCI_CAP_PTR 0xFF 154 155 #define R_PCH_SATA_INTR 0x3C // Interrupt Information 156 #define B_PCH_SATA_INTR_IPIN 0xFFFF0000 // Interrupt Pin 157 #define B_PCH_SATA_INTR_ILINE 0x0000FFFF // Interrupt Line 158 159 #define R_PCH_SATA_PMCS 0x74 // PCI Power Management Control and Status 160 #define B_PCH_SATA_PMCS_PMES BIT15 // PME Status 161 #define B_PCH_SATA_PMCS_PMEE BIT8 // PME Enable 162 #define B_PCH_SATA_PMCS_NSFRST BIT3 // No Soft Reset 163 #define V_PCH_SATA_PMCS_NSFRST_1 0x01 164 #define V_PCH_SATA_PMCS_NSFRST_0 0x00 165 #define B_PCH_SATA_PMCS_PS (BIT1 | BIT0) // Power State 166 #define V_PCH_SATA_PMCS_PS_3 0x03 167 #define V_PCH_SATA_PMCS_PS_0 0x00 168 169 #define R_PCH_SATA_MAP 0x90 // Port Mapping Register 170 #define B_PCH_SATA_MAP_SPD (BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8) // SATA Port Disable 171 #define B_PCH_SATA_PORT6_DISABLED BIT14 172 #define B_PCH_SATA_PORT5_DISABLED BIT13 173 #define B_PCH_SATA_PORT4_DISABLED BIT12 174 #define B_PCH_SATA_PORT3_DISABLED BIT11 175 #define B_PCH_SATA_PORT2_DISABLED BIT10 176 #define B_PCH_SATA_PORT1_DISABLED BIT9 177 #define B_PCH_SATA_PORT0_DISABLED BIT8 178 #define B_PCH_SATA_MAP_SMS_MASK (BIT7 | BIT6) // SATA Mode Select 179 #define V_PCH_SATA_MAP_SMS_IDE 0x00 180 #define V_PCH_SATA_MAP_SMS_AHCI 0x40 181 #define V_PCH_SATA_MAP_SMS_RAID 0x80 182 #define B_PCH_SATA_PORT_TO_CONTROLLER_CFG BIT5 // SATA Port-to-Controller Configuration 183 184 #define R_PCH_SATA_PCS 0x92 // Port Control and Status 185 #define S_PCH_SATA_PCS 0x2 186 #define B_PCH_SATA_PCS_OOB_RETRY BIT15 // OOB Retry Mode 187 #define B_PCH_SATA_PCS_PORT6_DET BIT14 // Port 6 Present 188 #define B_PCH_SATA_PCS_PORT5_DET BIT13 // Port 5 Present 189 #define B_PCH_SATA_PCS_PORT4_DET BIT12 // Port 4 Present 190 #define B_PCH_SATA_PCS_PORT3_DET BIT11 // Port 3 Present 191 #define B_PCH_SATA_PCS_PORT2_DET BIT10 // Port 2 Present 192 #define B_PCH_SATA_PCS_PORT1_DET BIT9 // Port 1 Present 193 #define B_PCH_SATA_PCS_PORT0_DET BIT8 // Port 0 Present 194 #define B_PCH_SATA_PCS_PORT5_EN BIT5 // Port 5 Enabled 195 #define B_PCH_SATA_PCS_PORT4_EN BIT4 // Port 4 Enabled 196 #define B_PCH_SATA_PCS_PORT3_EN BIT3 // Port 3 Enabled 197 #define B_PCH_SATA_PCS_PORT2_EN BIT2 // Port 2 Enabled 198 #define B_PCH_SATA_PCS_PORT1_EN BIT1 // Port 1 Enabled 199 #define B_PCH_SATA_PCS_PORT0_EN BIT0 // Port 0 Enabled 200 201 #define R_PCH_SATA_AHCI_PI 0x0C // Ports Implemented 202 #define B_PCH_SATA_PORT_MASK 0x3F 203 #define B_PCH_SATA_PORT5_IMPLEMENTED BIT5 // Port 5 Implemented 204 #define B_PCH_SATA_PORT4_IMPLEMENTED BIT4 // Port 4 Implemented 205 #define B_PCH_SATA_PORT3_IMPLEMENTED BIT3 // Port 3 Implemented 206 #define B_PCH_SATA_PORT2_IMPLEMENTED BIT2 // Port 2 Implemented 207 #define B_PCH_SATA_PORT1_IMPLEMENTED BIT1 // Port 1 Implemented 208 #define B_PCH_SATA_PORT0_IMPLEMENTED BIT0 // Port 0 Implemented 209 210 #define R_PCH_SATA_AHCI_P0SSTS 0x128 // Port 0 Serial ATA Status 211 #define R_PCH_SATA_AHCI_P1SSTS 0x1A8 // Port 1 Serial ATA Status 212 #define B_PCH_SATA_AHCI_PXSSTS_IPM 0x00000F00 // Interface Power Management 213 #define B_PCH_SATA_AHCI_PXSSTS_IPM_0 0x00000000 214 #define B_PCH_SATA_AHCI_PXSSTS_IPM_1 0x00000100 215 #define B_PCH_SATA_AHCI_PXSSTS_IPM_2 0x00000200 216 #define B_PCH_SATA_AHCI_PXSSTS_IPM_6 0x00000600 217 #define B_PCH_SATA_AHCI_PXSSTS_SPD 0x000000F0 // Current Interface Speed 218 #define B_PCH_SATA_AHCI_PXSSTS_SPD_0 0x00000000 219 #define B_PCH_SATA_AHCI_PXSSTS_SPD_1 0x00000010 220 #define B_PCH_SATA_AHCI_PXSSTS_SPD_2 0x00000020 221 #define B_PCH_SATA_AHCI_PXSSTS_SPD_3 0x00000030 222 #define B_PCH_SATA_AHCI_PXSSTS_DET 0x0000000F // Device Detection 223 #define B_PCH_SATA_AHCI_PXSSTS_DET_0 0x00000000 224 #define B_PCH_SATA_AHCI_PXSSTS_DET_1 0x00000001 225 #define B_PCH_SATA_AHCI_PXSSTS_DET_3 0x00000003 226 #define B_PCH_SATA_AHCI_PXSSTS_DET_4 0x00000004 227 228 // 229 // Macros of VLV capabilities for SATA controller which are used by SATA controller driver 230 // 231 // 232 // 233 // Define the individual capabilities of each SATA controller 234 // 235 #define PCH_SATA_MAX_CONTROLLERS 1 // Max SATA controllers number supported 236 #define PCH_SATA_MAX_DEVICES 2 // Max SATA devices number of single SATA channel 237 #define PCH_IDE_MAX_CHANNELS 2 // Max IDE channels number of single SATA controller 238 #define PCH_IDE_MAX_DEVICES 2 // Max IDE devices number of single SATA channel 239 #define PCH_AHCI_MAX_PORTS 2 // Max number of SATA ports in VLV 240 #define PCH_IDE_MAX_PORTS 2 // Max number of IDE ports in VLV 241 242 // 243 // GPIOS_14 SATA0GP is the SATA port 0 reset pin. 244 // 245 #define PCH_GPIO_SATA_PORT0_RESET 14 246 // 247 // GPIOS_15 SATA1GP is the SATA port 1 reset pin. 248 // 249 #define PCH_GPIO_SATA_PORT1_RESET 15 250 251 #endif 252
