1 /* tc-v850.c -- Assembler code for the NEC V850 2 Copyright (C) 1996-2016 Free Software Foundation, Inc. 3 4 This file is part of GAS, the GNU Assembler. 5 6 GAS is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 GAS is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GAS; see the file COPYING. If not, write to 18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, 19 Boston, MA 02110-1301, USA. */ 20 21 #include "as.h" 22 #include "safe-ctype.h" 23 #include "subsegs.h" 24 #include "opcode/v850.h" 25 #include "dwarf2dbg.h" 26 27 /* Sign-extend a 16-bit number. */ 28 #define SEXT16(x) ((((x) & 0xffff) ^ (~0x7fff)) + 0x8000) 29 30 /* Set to TRUE if we want to be pedantic about signed overflows. */ 31 static bfd_boolean warn_signed_overflows = FALSE; 32 static bfd_boolean warn_unsigned_overflows = FALSE; 33 34 /* Non-zero if floating point insns are not being used. */ 35 static signed int soft_float = -1; 36 37 /* Indicates the target BFD machine number. */ 38 static int machine = -1; 39 40 41 /* Indiciates the target BFD architecture. */ 42 enum bfd_architecture v850_target_arch = bfd_arch_v850_rh850; 43 const char * v850_target_format = "elf32-v850-rh850"; 44 static flagword v850_e_flags = 0; 45 46 /* Indicates the target processor(s) for the assemble. */ 47 static int processor_mask = 0; 48 49 /* Structure to hold information about predefined registers. */ 51 struct reg_name 52 { 53 const char *name; 54 int value; 55 unsigned int processors; 56 }; 57 58 /* Generic assembler global variables which must be defined by all 59 targets. */ 60 61 /* Characters which always start a comment. */ 62 const char comment_chars[] = "#"; 63 64 /* Characters which start a comment at the beginning of a line. */ 65 const char line_comment_chars[] = ";#"; 66 67 /* Characters which may be used to separate multiple commands on a 68 single line. */ 69 const char line_separator_chars[] = ";"; 70 71 /* Characters which are used to indicate an exponent in a floating 72 point number. */ 73 const char EXP_CHARS[] = "eE"; 74 75 /* Characters which mean that a number is a floating point constant, 76 as in 0d1.0. */ 77 const char FLT_CHARS[] = "dD"; 78 79 const relax_typeS md_relax_table[] = 81 { 82 /* Conditional branches.(V850/V850E, max 22bit) */ 83 #define SUBYPTE_COND_9_22 0 84 {0xfe, -0x100, 2, SUBYPTE_COND_9_22 + 1}, 85 {0x1ffffe + 2, -0x200000 + 2, 6, 0}, 86 /* Conditional branches.(V850/V850E, max 22bit) */ 87 #define SUBYPTE_SA_9_22 2 88 {0xfe, -0x100, 2, SUBYPTE_SA_9_22 + 1}, 89 {0x1ffffe + 4, -0x200000 + 4, 8, 0}, 90 /* Unconditional branches.(V850/V850E, max 22bit) */ 91 #define SUBYPTE_UNCOND_9_22 4 92 {0xfe, -0x100, 2, SUBYPTE_UNCOND_9_22 + 1}, 93 {0x1ffffe, -0x200000, 4, 0}, 94 /* Conditional branches.(V850E2, max 32bit) */ 95 #define SUBYPTE_COND_9_22_32 6 96 {0xfe, -0x100, 2, SUBYPTE_COND_9_22_32 + 1}, 97 {0x1fffff + 2, -0x200000 + 2, 6, SUBYPTE_COND_9_22_32 + 2}, 98 {0x7ffffffe, -0x80000000, 8, 0}, 99 /* Conditional branches.(V850E2, max 32bit) */ 100 #define SUBYPTE_SA_9_22_32 9 101 {0xfe, -0x100, 2, SUBYPTE_SA_9_22_32 + 1}, 102 {0x1ffffe + 4, -0x200000 + 4, 8, SUBYPTE_SA_9_22_32 + 2}, 103 {0x7ffffffe, -0x80000000, 10, 0}, 104 /* Unconditional branches.(V850E2, max 32bit) */ 105 #define SUBYPTE_UNCOND_9_22_32 12 106 {0xfe, -0x100, 2, SUBYPTE_UNCOND_9_22_32 + 1}, 107 {0x1ffffe, -0x200000, 4, SUBYPTE_UNCOND_9_22_32 + 2}, 108 {0x7ffffffe, -0x80000000, 6, 0}, 109 /* Conditional branches.(V850E2R max 22bit) */ 110 #define SUBYPTE_COND_9_17_22 15 111 {0xfe, -0x100, 2, SUBYPTE_COND_9_17_22 + 1}, 112 {0xfffe, -0x10000, 4, SUBYPTE_COND_9_17_22 + 2}, 113 {0x1ffffe + 2, -0x200000 + 2, 6, 0}, 114 /* Conditional branches.(V850E2R max 22bit) */ 115 #define SUBYPTE_SA_9_17_22 18 116 {0xfe, -0x100, 2, SUBYPTE_SA_9_17_22 + 1}, 117 {0xfffe, -0x10000, 4, SUBYPTE_SA_9_17_22 + 2}, 118 {0x1ffffe + 4, -0x200000 + 4, 8, 0}, 119 /* Conditional branches.(V850E2R max 32bit) */ 120 #define SUBYPTE_COND_9_17_22_32 21 121 {0xfe, -0x100, 2, SUBYPTE_COND_9_17_22_32 + 1}, 122 {0xfffe, -0x10000, 4, SUBYPTE_COND_9_17_22_32 + 2}, 123 {0x1ffffe + 2, -0x200000 + 2, 6, SUBYPTE_COND_9_17_22_32 + 3}, 124 {0x7ffffffe, -0x80000000, 8, 0}, 125 /* Conditional branches.(V850E2R max 32bit) */ 126 #define SUBYPTE_SA_9_17_22_32 25 127 {0xfe, -0x100, 2, SUBYPTE_SA_9_17_22_32 + 1}, 128 {0xfffe, -0x10000, 4, SUBYPTE_SA_9_17_22_32 + 2}, 129 {0x1ffffe + 4, -0x200000 + 4, 8, SUBYPTE_SA_9_17_22_32 + 3}, 130 {0x7ffffffe, -0x80000000, 10, 0}, 131 /* Loop. (V850E2V4_UP, max 22-bit). */ 132 #define SUBYPTE_LOOP_16_22 29 133 {0x0, -0x0fffe, 4, SUBYPTE_LOOP_16_22 + 1}, 134 {0x1ffffe + 2, -0x200000 + 2, 6, 0}, 135 }; 136 137 static int v850_relax = 0; 138 139 /* Default branch disp size 22 or 32. */ 140 static int default_disp_size = 22; 141 142 /* Default no using bcond17. */ 143 static int no_bcond17 = 0; 144 145 /* Default no using ld/st 23bit offset. */ 146 static int no_stld23 = 0; 147 148 /* Fixups. */ 149 #define MAX_INSN_FIXUPS 5 150 151 struct v850_fixup 152 { 153 expressionS exp; 154 int opindex; 155 bfd_reloc_code_real_type reloc; 156 }; 157 158 struct v850_fixup fixups[MAX_INSN_FIXUPS]; 159 static int fc; 160 161 struct v850_seg_entry 162 { 163 segT s; 164 const char *name; 165 flagword flags; 166 }; 167 168 struct v850_seg_entry v850_seg_table[] = 169 { 170 { NULL, ".sdata", 171 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS 172 | SEC_SMALL_DATA }, 173 { NULL, ".tdata", 174 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS }, 175 { NULL, ".zdata", 176 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS }, 177 { NULL, ".sbss", 178 SEC_ALLOC | SEC_SMALL_DATA }, 179 { NULL, ".tbss", 180 SEC_ALLOC }, 181 { NULL, ".zbss", 182 SEC_ALLOC}, 183 { NULL, ".rosdata", 184 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_READONLY | SEC_DATA 185 | SEC_HAS_CONTENTS | SEC_SMALL_DATA }, 186 { NULL, ".rozdata", 187 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_READONLY | SEC_DATA 188 | SEC_HAS_CONTENTS }, 189 { NULL, ".scommon", 190 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS 191 | SEC_SMALL_DATA | SEC_IS_COMMON }, 192 { NULL, ".tcommon", 193 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS 194 | SEC_IS_COMMON }, 195 { NULL, ".zcommon", 196 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS 197 | SEC_IS_COMMON }, 198 { NULL, ".call_table_data", 199 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS }, 200 { NULL, ".call_table_text", 201 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_READONLY | SEC_CODE 202 | SEC_HAS_CONTENTS}, 203 { NULL, ".bss", 204 SEC_ALLOC } 205 }; 206 207 #define SDATA_SECTION 0 208 #define TDATA_SECTION 1 209 #define ZDATA_SECTION 2 210 #define SBSS_SECTION 3 211 #define TBSS_SECTION 4 212 #define ZBSS_SECTION 5 213 #define ROSDATA_SECTION 6 214 #define ROZDATA_SECTION 7 215 #define SCOMMON_SECTION 8 216 #define TCOMMON_SECTION 9 217 #define ZCOMMON_SECTION 10 218 #define CALL_TABLE_DATA_SECTION 11 219 #define CALL_TABLE_TEXT_SECTION 12 220 #define BSS_SECTION 13 221 222 static void 223 do_v850_seg (int i, subsegT sub) 224 { 225 struct v850_seg_entry *seg = v850_seg_table + i; 226 227 obj_elf_section_change_hook (); 228 229 if (seg->s != NULL) 230 subseg_set (seg->s, sub); 231 else 232 { 233 seg->s = subseg_new (seg->name, sub); 234 bfd_set_section_flags (stdoutput, seg->s, seg->flags); 235 if ((seg->flags & SEC_LOAD) == 0) 236 seg_info (seg->s)->bss = 1; 237 } 238 } 239 240 static void 241 v850_seg (int i) 242 { 243 subsegT sub = get_absolute_expression (); 244 245 do_v850_seg (i, sub); 246 demand_empty_rest_of_line (); 247 } 248 249 static void 250 v850_offset (int ignore ATTRIBUTE_UNUSED) 251 { 252 char *pfrag; 253 int temp = get_absolute_expression (); 254 255 pfrag = frag_var (rs_org, 1, 1, (relax_substateT)0, (symbolS *)0, 256 (offsetT) temp, (char *) 0); 257 *pfrag = 0; 258 259 demand_empty_rest_of_line (); 260 } 261 262 /* Copied from obj_elf_common() in gas/config/obj-elf.c. */ 263 264 static void 265 v850_comm (int area) 266 { 267 char *name; 268 char c; 269 char *p; 270 int temp; 271 unsigned int size; 272 symbolS *symbolP; 273 int have_align; 274 275 c = get_symbol_name (&name); 276 277 /* Just after name is now '\0'. */ 278 p = input_line_pointer; 279 *p = c; 280 281 SKIP_WHITESPACE (); 282 283 if (*input_line_pointer != ',') 284 { 285 as_bad (_("Expected comma after symbol-name")); 286 ignore_rest_of_line (); 287 return; 288 } 289 290 /* Skip ','. */ 291 input_line_pointer++; 292 293 if ((temp = get_absolute_expression ()) < 0) 294 { 295 /* xgettext:c-format */ 296 as_bad (_(".COMMon length (%d.) < 0! Ignored."), temp); 297 ignore_rest_of_line (); 298 return; 299 } 300 301 size = temp; 302 *p = 0; 303 symbolP = symbol_find_or_make (name); 304 *p = c; 305 306 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP)) 307 { 308 as_bad (_("Ignoring attempt to re-define symbol")); 309 ignore_rest_of_line (); 310 return; 311 } 312 313 if (S_GET_VALUE (symbolP) != 0) 314 { 315 if (S_GET_VALUE (symbolP) != size) 316 /* xgettext:c-format */ 317 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %d."), 318 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), size); 319 } 320 321 know (symbol_get_frag (symbolP) == &zero_address_frag); 322 323 if (*input_line_pointer != ',') 324 have_align = 0; 325 else 326 { 327 have_align = 1; 328 input_line_pointer++; 329 SKIP_WHITESPACE (); 330 } 331 332 if (! have_align || *input_line_pointer != '"') 333 { 334 if (! have_align) 335 temp = 0; 336 else 337 { 338 temp = get_absolute_expression (); 339 340 if (temp < 0) 341 { 342 temp = 0; 343 as_warn (_("Common alignment negative; 0 assumed")); 344 } 345 } 346 347 if (symbol_get_obj (symbolP)->local) 348 { 349 segT old_sec; 350 int old_subsec; 351 char *pfrag; 352 int align; 353 flagword applicable; 354 355 old_sec = now_seg; 356 old_subsec = now_subseg; 357 358 applicable = bfd_applicable_section_flags (stdoutput); 359 360 applicable &= SEC_ALLOC; 361 362 switch (area) 363 { 364 case SCOMMON_SECTION: 365 do_v850_seg (SBSS_SECTION, 0); 366 break; 367 368 case ZCOMMON_SECTION: 369 do_v850_seg (ZBSS_SECTION, 0); 370 break; 371 372 case TCOMMON_SECTION: 373 do_v850_seg (TBSS_SECTION, 0); 374 break; 375 } 376 377 if (temp) 378 { 379 /* Convert to a power of 2 alignment. */ 380 for (align = 0; (temp & 1) == 0; temp >>= 1, ++align) 381 ; 382 383 if (temp != 1) 384 { 385 as_bad (_("Common alignment not a power of 2")); 386 ignore_rest_of_line (); 387 return; 388 } 389 } 390 else 391 align = 0; 392 393 record_alignment (now_seg, align); 394 395 if (align) 396 frag_align (align, 0, 0); 397 398 switch (area) 399 { 400 case SCOMMON_SECTION: 401 if (S_GET_SEGMENT (symbolP) == v850_seg_table[SBSS_SECTION].s) 402 symbol_get_frag (symbolP)->fr_symbol = 0; 403 break; 404 405 case ZCOMMON_SECTION: 406 if (S_GET_SEGMENT (symbolP) == v850_seg_table[ZBSS_SECTION].s) 407 symbol_get_frag (symbolP)->fr_symbol = 0; 408 break; 409 410 case TCOMMON_SECTION: 411 if (S_GET_SEGMENT (symbolP) == v850_seg_table[TBSS_SECTION].s) 412 symbol_get_frag (symbolP)->fr_symbol = 0; 413 break; 414 415 default: 416 abort (); 417 } 418 419 symbol_set_frag (symbolP, frag_now); 420 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, 421 (offsetT) size, (char *) 0); 422 *pfrag = 0; 423 S_SET_SIZE (symbolP, size); 424 425 switch (area) 426 { 427 case SCOMMON_SECTION: 428 S_SET_SEGMENT (symbolP, v850_seg_table[SBSS_SECTION].s); 429 break; 430 431 case ZCOMMON_SECTION: 432 S_SET_SEGMENT (symbolP, v850_seg_table[ZBSS_SECTION].s); 433 break; 434 435 case TCOMMON_SECTION: 436 S_SET_SEGMENT (symbolP, v850_seg_table[TBSS_SECTION].s); 437 break; 438 439 default: 440 abort (); 441 } 442 443 S_CLEAR_EXTERNAL (symbolP); 444 obj_elf_section_change_hook (); 445 subseg_set (old_sec, old_subsec); 446 } 447 else 448 { 449 segT old_sec; 450 int old_subsec; 451 452 allocate_common: 453 old_sec = now_seg; 454 old_subsec = now_subseg; 455 456 S_SET_VALUE (symbolP, (valueT) size); 457 S_SET_ALIGN (symbolP, temp); 458 S_SET_EXTERNAL (symbolP); 459 460 switch (area) 461 { 462 case SCOMMON_SECTION: 463 case ZCOMMON_SECTION: 464 case TCOMMON_SECTION: 465 do_v850_seg (area, 0); 466 S_SET_SEGMENT (symbolP, v850_seg_table[area].s); 467 break; 468 469 default: 470 abort (); 471 } 472 473 obj_elf_section_change_hook (); 474 subseg_set (old_sec, old_subsec); 475 } 476 } 477 else 478 { 479 input_line_pointer++; 480 481 /* @@ Some use the dot, some don't. Can we get some consistency?? */ 482 if (*input_line_pointer == '.') 483 input_line_pointer++; 484 485 /* @@ Some say data, some say bss. */ 486 if (strncmp (input_line_pointer, "bss\"", 4) 487 && strncmp (input_line_pointer, "data\"", 5)) 488 { 489 while (*--input_line_pointer != '"') 490 ; 491 input_line_pointer--; 492 goto bad_common_segment; 493 } 494 495 while (*input_line_pointer++ != '"') 496 ; 497 498 goto allocate_common; 499 } 500 501 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT; 502 503 demand_empty_rest_of_line (); 504 return; 505 506 { 507 bad_common_segment: 508 p = input_line_pointer; 509 while (*p && *p != '\n') 510 p++; 511 c = *p; 512 *p = '\0'; 513 as_bad (_("bad .common segment %s"), input_line_pointer + 1); 514 *p = c; 515 input_line_pointer = p; 516 ignore_rest_of_line (); 517 return; 518 } 519 } 520 521 static void 522 set_machine (int number) 523 { 524 machine = number; 525 bfd_set_arch_mach (stdoutput, v850_target_arch, machine); 526 527 switch (machine) 528 { 529 case 0: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850); break; 530 case bfd_mach_v850: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850); break; 531 case bfd_mach_v850e: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E); break; 532 case bfd_mach_v850e1: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E); break; 533 case bfd_mach_v850e2: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2); break; 534 case bfd_mach_v850e2v3:SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2V3); break; 535 case bfd_mach_v850e3v5: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5); break; 536 } 537 } 538 539 static void 540 v850_longcode (int type) 541 { 542 expressionS ex; 543 544 if (! v850_relax) 545 { 546 if (type == 1) 547 as_warn (_(".longcall pseudo-op seen when not relaxing")); 548 else 549 as_warn (_(".longjump pseudo-op seen when not relaxing")); 550 } 551 552 expression (&ex); 553 554 if (ex.X_op != O_symbol || ex.X_add_number != 0) 555 { 556 as_bad (_("bad .longcall format")); 557 ignore_rest_of_line (); 558 559 return; 560 } 561 562 if (type == 1) 563 fix_new_exp (frag_now, frag_now_fix (), 4, & ex, 1, 564 BFD_RELOC_V850_LONGCALL); 565 else 566 fix_new_exp (frag_now, frag_now_fix (), 4, & ex, 1, 567 BFD_RELOC_V850_LONGJUMP); 568 569 demand_empty_rest_of_line (); 570 } 571 572 /* The target specific pseudo-ops which we support. */ 573 const pseudo_typeS md_pseudo_table[] = 574 { 575 { "sdata", v850_seg, SDATA_SECTION }, 576 { "tdata", v850_seg, TDATA_SECTION }, 577 { "zdata", v850_seg, ZDATA_SECTION }, 578 { "sbss", v850_seg, SBSS_SECTION }, 579 { "tbss", v850_seg, TBSS_SECTION }, 580 { "zbss", v850_seg, ZBSS_SECTION }, 581 { "rosdata", v850_seg, ROSDATA_SECTION }, 582 { "rozdata", v850_seg, ROZDATA_SECTION }, 583 { "bss", v850_seg, BSS_SECTION }, 584 { "offset", v850_offset, 0 }, 585 { "word", cons, 4 }, 586 { "zcomm", v850_comm, ZCOMMON_SECTION }, 587 { "scomm", v850_comm, SCOMMON_SECTION }, 588 { "tcomm", v850_comm, TCOMMON_SECTION }, 589 { "v850", set_machine, 0 }, 590 { "call_table_data", v850_seg, CALL_TABLE_DATA_SECTION }, 591 { "call_table_text", v850_seg, CALL_TABLE_TEXT_SECTION }, 592 { "v850e", set_machine, bfd_mach_v850e }, 593 { "v850e1", set_machine, bfd_mach_v850e1 }, 594 { "v850e2", set_machine, bfd_mach_v850e2 }, 595 { "v850e2v3", set_machine, bfd_mach_v850e2v3 }, 596 { "v850e2v4", set_machine, bfd_mach_v850e3v5 }, 597 { "v850e3v5", set_machine, bfd_mach_v850e3v5 }, 598 { "longcall", v850_longcode, 1 }, 599 { "longjump", v850_longcode, 2 }, 600 { NULL, NULL, 0 } 601 }; 602 603 /* Opcode hash table. */ 604 static struct hash_control *v850_hash; 605 606 /* This table is sorted. Suitable for searching by a binary search. */ 607 static const struct reg_name pre_defined_registers[] = 608 { 609 { "ep", 30, PROCESSOR_ALL }, /* ep - element ptr. */ 610 { "gp", 4, PROCESSOR_ALL }, /* gp - global ptr. */ 611 { "hp", 2, PROCESSOR_ALL }, /* hp - handler stack ptr. */ 612 { "lp", 31, PROCESSOR_ALL }, /* lp - link ptr. */ 613 { "r0", 0, PROCESSOR_ALL }, 614 { "r1", 1, PROCESSOR_ALL }, 615 { "r10", 10, PROCESSOR_ALL }, 616 { "r11", 11, PROCESSOR_ALL }, 617 { "r12", 12, PROCESSOR_ALL }, 618 { "r13", 13, PROCESSOR_ALL }, 619 { "r14", 14, PROCESSOR_ALL }, 620 { "r15", 15, PROCESSOR_ALL }, 621 { "r16", 16, PROCESSOR_ALL }, 622 { "r17", 17, PROCESSOR_ALL }, 623 { "r18", 18, PROCESSOR_ALL }, 624 { "r19", 19, PROCESSOR_ALL }, 625 { "r2", 2, PROCESSOR_ALL }, 626 { "r20", 20, PROCESSOR_ALL }, 627 { "r21", 21, PROCESSOR_ALL }, 628 { "r22", 22, PROCESSOR_ALL }, 629 { "r23", 23, PROCESSOR_ALL }, 630 { "r24", 24, PROCESSOR_ALL }, 631 { "r25", 25, PROCESSOR_ALL }, 632 { "r26", 26, PROCESSOR_ALL }, 633 { "r27", 27, PROCESSOR_ALL }, 634 { "r28", 28, PROCESSOR_ALL }, 635 { "r29", 29, PROCESSOR_ALL }, 636 { "r3", 3, PROCESSOR_ALL }, 637 { "r30", 30, PROCESSOR_ALL }, 638 { "r31", 31, PROCESSOR_ALL }, 639 { "r4", 4, PROCESSOR_ALL }, 640 { "r5", 5, PROCESSOR_ALL }, 641 { "r6", 6, PROCESSOR_ALL }, 642 { "r7", 7, PROCESSOR_ALL }, 643 { "r8", 8, PROCESSOR_ALL }, 644 { "r9", 9, PROCESSOR_ALL }, 645 { "sp", 3, PROCESSOR_ALL }, /* sp - stack ptr. */ 646 { "tp", 5, PROCESSOR_ALL }, /* tp - text ptr. */ 647 { "zero", 0, PROCESSOR_ALL }, 648 }; 649 650 #define REG_NAME_CNT \ 651 (sizeof (pre_defined_registers) / sizeof (struct reg_name)) 652 653 static const struct reg_name system_registers[] = 654 { 655 { "asid", 23, PROCESSOR_NOT_V850 }, 656 { "bpam", 25, PROCESSOR_NOT_V850 }, 657 { "bpav", 24, PROCESSOR_NOT_V850 }, 658 { "bpc", 22, PROCESSOR_NOT_V850 }, 659 { "bpdm", 27, PROCESSOR_NOT_V850 }, 660 { "bpdv", 26, PROCESSOR_NOT_V850 }, 661 { "bsel", 31, PROCESSOR_V850E2_UP }, 662 { "cfg", 7, PROCESSOR_V850E2V3_UP }, 663 { "ctbp", 20, PROCESSOR_NOT_V850 }, 664 { "ctpc", 16, PROCESSOR_NOT_V850 }, 665 { "ctpsw", 17, PROCESSOR_NOT_V850 }, 666 { "dbic", 15, PROCESSOR_V850E2_UP }, 667 { "dbpc", 18, PROCESSOR_NOT_V850 }, 668 { "dbpsw", 19, PROCESSOR_NOT_V850 }, 669 { "dbwr", 30, PROCESSOR_V850E2_UP }, 670 { "dir", 21, PROCESSOR_NOT_V850 }, 671 { "dpa0l", 16, PROCESSOR_V850E2V3_UP }, 672 { "dpa0u", 17, PROCESSOR_V850E2V3_UP }, 673 { "dpa1l", 18, PROCESSOR_V850E2V3_UP }, 674 { "dpa1u", 19, PROCESSOR_V850E2V3_UP }, 675 { "dpa2l", 20, PROCESSOR_V850E2V3_UP }, 676 { "dpa2u", 21, PROCESSOR_V850E2V3_UP }, 677 { "dpa3l", 22, PROCESSOR_V850E2V3_UP }, 678 { "dpa3u", 23, PROCESSOR_V850E2V3_UP }, 679 { "dpa4l", 24, PROCESSOR_V850E2V3_UP }, 680 { "dpa4u", 25, PROCESSOR_V850E2V3_UP }, 681 { "dpa5l", 26, PROCESSOR_V850E2V3_UP }, 682 { "dpa5u", 27, PROCESSOR_V850E2V3_UP }, 683 { "ecr", 4, PROCESSOR_ALL }, 684 { "eh_base", 3, PROCESSOR_V850E2V3_UP }, 685 { "eh_cfg", 1, PROCESSOR_V850E2V3_UP }, 686 { "eh_reset", 2, PROCESSOR_V850E2V3_UP }, 687 { "eiic", 13, PROCESSOR_V850E2_UP }, 688 { "eipc", 0, PROCESSOR_ALL }, 689 { "eipsw", 1, PROCESSOR_ALL }, 690 { "eiwr", 28, PROCESSOR_V850E2_UP }, 691 { "feic", 14, PROCESSOR_V850E2_UP }, 692 { "fepc", 2, PROCESSOR_ALL }, 693 { "fepsw", 3, PROCESSOR_ALL }, 694 { "fewr", 29, PROCESSOR_V850E2_UP }, 695 { "fpcc", 9, PROCESSOR_V850E2V3_UP }, 696 { "fpcfg", 10, PROCESSOR_V850E2V3_UP }, 697 { "fpec", 11, PROCESSOR_V850E2V3_UP }, 698 { "fpepc", 7, PROCESSOR_V850E2V3_UP }, 699 { "fpspc", 27, PROCESSOR_V850E2V3_UP }, 700 { "fpsr", 6, PROCESSOR_V850E2V3_UP }, 701 { "fpst", 8, PROCESSOR_V850E2V3_UP }, 702 { "ipa0l", 6, PROCESSOR_V850E2V3_UP }, 703 { "ipa0u", 7, PROCESSOR_V850E2V3_UP }, 704 { "ipa1l", 8, PROCESSOR_V850E2V3_UP }, 705 { "ipa1u", 9, PROCESSOR_V850E2V3_UP }, 706 { "ipa2l", 10, PROCESSOR_V850E2V3_UP }, 707 { "ipa2u", 11, PROCESSOR_V850E2V3_UP }, 708 { "ipa3l", 12, PROCESSOR_V850E2V3_UP }, 709 { "ipa3u", 13, PROCESSOR_V850E2V3_UP }, 710 { "ipa4l", 14, PROCESSOR_V850E2V3_UP }, 711 { "ipa4u", 15, PROCESSOR_V850E2V3_UP }, 712 { "mca", 24, PROCESSOR_V850E2V3_UP }, 713 { "mcc", 26, PROCESSOR_V850E2V3_UP }, 714 { "mcr", 27, PROCESSOR_V850E2V3_UP }, 715 { "mcs", 25, PROCESSOR_V850E2V3_UP }, 716 { "mpc", 1, PROCESSOR_V850E2V3_UP }, 717 { "mpm", 0, PROCESSOR_V850E2V3_UP }, 718 { "mpu10_dpa0l", 16, PROCESSOR_V850E2V3_UP }, 719 { "mpu10_dpa0u", 17, PROCESSOR_V850E2V3_UP }, 720 { "mpu10_dpa1l", 18, PROCESSOR_V850E2V3_UP }, 721 { "mpu10_dpa1u", 19, PROCESSOR_V850E2V3_UP }, 722 { "mpu10_dpa2l", 20, PROCESSOR_V850E2V3_UP }, 723 { "mpu10_dpa2u", 21, PROCESSOR_V850E2V3_UP }, 724 { "mpu10_dpa3l", 22, PROCESSOR_V850E2V3_UP }, 725 { "mpu10_dpa3u", 23, PROCESSOR_V850E2V3_UP }, 726 { "mpu10_dpa4l", 24, PROCESSOR_V850E2V3_UP }, 727 { "mpu10_dpa4u", 25, PROCESSOR_V850E2V3_UP }, 728 { "mpu10_dpa5l", 26, PROCESSOR_V850E2V3_UP }, 729 { "mpu10_dpa5u", 27, PROCESSOR_V850E2V3_UP }, 730 { "mpu10_ipa0l", 6, PROCESSOR_V850E2V3_UP }, 731 { "mpu10_ipa0u", 7, PROCESSOR_V850E2V3_UP }, 732 { "mpu10_ipa1l", 8, PROCESSOR_V850E2V3_UP }, 733 { "mpu10_ipa1u", 9, PROCESSOR_V850E2V3_UP }, 734 { "mpu10_ipa2l", 10, PROCESSOR_V850E2V3_UP }, 735 { "mpu10_ipa2u", 11, PROCESSOR_V850E2V3_UP }, 736 { "mpu10_ipa3l", 12, PROCESSOR_V850E2V3_UP }, 737 { "mpu10_ipa3u", 13, PROCESSOR_V850E2V3_UP }, 738 { "mpu10_ipa4l", 14, PROCESSOR_V850E2V3_UP }, 739 { "mpu10_ipa4u", 15, PROCESSOR_V850E2V3_UP }, 740 { "mpu10_mpc", 1, PROCESSOR_V850E2V3_UP }, 741 { "mpu10_mpm", 0, PROCESSOR_V850E2V3_UP }, 742 { "mpu10_tid", 2, PROCESSOR_V850E2V3_UP }, 743 { "mpu10_vmadr", 5, PROCESSOR_V850E2V3_UP }, 744 { "mpu10_vmecr", 3, PROCESSOR_V850E2V3_UP }, 745 { "mpu10_vmtid", 4, PROCESSOR_V850E2V3_UP }, 746 { "pid", 6, PROCESSOR_V850E2V3_UP }, 747 { "pmcr0", 4, PROCESSOR_V850E2V3_UP }, 748 { "pmis2", 14, PROCESSOR_V850E2V3_UP }, 749 { "psw", 5, PROCESSOR_ALL }, 750 { "scbp", 12, PROCESSOR_V850E2V3_UP }, 751 { "sccfg", 11, PROCESSOR_V850E2V3_UP }, 752 { "sr0", 0, PROCESSOR_ALL }, 753 { "sr1", 1, PROCESSOR_ALL }, 754 { "sr10", 10, PROCESSOR_ALL }, 755 { "sr11", 11, PROCESSOR_ALL }, 756 { "sr12", 12, PROCESSOR_ALL }, 757 { "sr13", 13, PROCESSOR_ALL }, 758 { "sr14", 14, PROCESSOR_ALL }, 759 { "sr15", 15, PROCESSOR_ALL }, 760 { "sr16", 16, PROCESSOR_ALL }, 761 { "sr17", 17, PROCESSOR_ALL }, 762 { "sr18", 18, PROCESSOR_ALL }, 763 { "sr19", 19, PROCESSOR_ALL }, 764 { "sr2", 2, PROCESSOR_ALL }, 765 { "sr20", 20, PROCESSOR_ALL }, 766 { "sr21", 21, PROCESSOR_ALL }, 767 { "sr22", 22, PROCESSOR_ALL }, 768 { "sr23", 23, PROCESSOR_ALL }, 769 { "sr24", 24, PROCESSOR_ALL }, 770 { "sr25", 25, PROCESSOR_ALL }, 771 { "sr26", 26, PROCESSOR_ALL }, 772 { "sr27", 27, PROCESSOR_ALL }, 773 { "sr28", 28, PROCESSOR_ALL }, 774 { "sr29", 29, PROCESSOR_ALL }, 775 { "sr3", 3, PROCESSOR_ALL }, 776 { "sr30", 30, PROCESSOR_ALL }, 777 { "sr31", 31, PROCESSOR_ALL }, 778 { "sr4", 4, PROCESSOR_ALL }, 779 { "sr5", 5, PROCESSOR_ALL }, 780 { "sr6", 6, PROCESSOR_ALL }, 781 { "sr7", 7, PROCESSOR_ALL }, 782 { "sr8", 8, PROCESSOR_ALL }, 783 { "sr9", 9, PROCESSOR_ALL }, 784 { "sw_base", 3, PROCESSOR_V850E2V3_UP }, 785 { "sw_cfg", 1, PROCESSOR_V850E2V3_UP }, 786 { "sw_ctl", 0, PROCESSOR_V850E2V3_UP }, 787 { "tid", 2, PROCESSOR_V850E2V3_UP }, 788 { "vmadr", 6, PROCESSOR_V850E2V3_UP }, 789 { "vmecr", 4, PROCESSOR_V850E2V3_UP }, 790 { "vmtid", 5, PROCESSOR_V850E2V3_UP }, 791 { "vsadr", 2, PROCESSOR_V850E2V3_UP }, 792 { "vsecr", 0, PROCESSOR_V850E2V3_UP }, 793 { "vstid", 1, PROCESSOR_V850E2V3_UP }, 794 }; 795 796 #define SYSREG_NAME_CNT \ 797 (sizeof (system_registers) / sizeof (struct reg_name)) 798 799 800 static const struct reg_name cc_names[] = 801 { 802 { "c", 0x1, PROCESSOR_ALL }, 803 { "e", 0x2, PROCESSOR_ALL }, 804 { "ge", 0xe, PROCESSOR_ALL }, 805 { "gt", 0xf, PROCESSOR_ALL }, 806 { "h", 0xb, PROCESSOR_ALL }, 807 { "l", 0x1, PROCESSOR_ALL }, 808 { "le", 0x7, PROCESSOR_ALL }, 809 { "lt", 0x6, PROCESSOR_ALL }, 810 { "n", 0x4, PROCESSOR_ALL }, 811 { "nc", 0x9, PROCESSOR_ALL }, 812 { "ne", 0xa, PROCESSOR_ALL }, 813 { "nh", 0x3, PROCESSOR_ALL }, 814 { "nl", 0x9, PROCESSOR_ALL }, 815 { "ns", 0xc, PROCESSOR_ALL }, 816 { "nv", 0x8, PROCESSOR_ALL }, 817 { "nz", 0xa, PROCESSOR_ALL }, 818 { "p", 0xc, PROCESSOR_ALL }, 819 { "s", 0x4, PROCESSOR_ALL }, 820 #define COND_SA_NUM 0xd 821 { "sa", COND_SA_NUM, PROCESSOR_ALL }, 822 { "t", 0x5, PROCESSOR_ALL }, 823 { "v", 0x0, PROCESSOR_ALL }, 824 { "z", 0x2, PROCESSOR_ALL }, 825 }; 826 827 #define CC_NAME_CNT \ 828 (sizeof (cc_names) / sizeof (struct reg_name)) 829 830 static const struct reg_name float_cc_names[] = 831 { 832 { "eq", 0x2, PROCESSOR_V850E2V3_UP }, /* true. */ 833 { "f", 0x0, PROCESSOR_V850E2V3_UP }, /* true. */ 834 { "ge", 0xd, PROCESSOR_V850E2V3_UP }, /* false. */ 835 { "gl", 0xb, PROCESSOR_V850E2V3_UP }, /* false. */ 836 { "gle", 0x9, PROCESSOR_V850E2V3_UP }, /* false. */ 837 { "gt", 0xf, PROCESSOR_V850E2V3_UP }, /* false. */ 838 { "le", 0xe, PROCESSOR_V850E2V3_UP }, /* true. */ 839 { "lt", 0xc, PROCESSOR_V850E2V3_UP }, /* true. */ 840 { "neq", 0x2, PROCESSOR_V850E2V3_UP }, /* false. */ 841 { "nge", 0xd, PROCESSOR_V850E2V3_UP }, /* true. */ 842 { "ngl", 0xb, PROCESSOR_V850E2V3_UP }, /* true. */ 843 { "ngle",0x9, PROCESSOR_V850E2V3_UP }, /* true. */ 844 { "ngt", 0xf, PROCESSOR_V850E2V3_UP }, /* true. */ 845 { "nle", 0xe, PROCESSOR_V850E2V3_UP }, /* false. */ 846 { "nlt", 0xc, PROCESSOR_V850E2V3_UP }, /* false. */ 847 { "oge", 0x5, PROCESSOR_V850E2V3_UP }, /* false. */ 848 { "ogl", 0x3, PROCESSOR_V850E2V3_UP }, /* false. */ 849 { "ogt", 0x7, PROCESSOR_V850E2V3_UP }, /* false. */ 850 { "ole", 0x6, PROCESSOR_V850E2V3_UP }, /* true. */ 851 { "olt", 0x4, PROCESSOR_V850E2V3_UP }, /* true. */ 852 { "or", 0x1, PROCESSOR_V850E2V3_UP }, /* false. */ 853 { "seq", 0xa, PROCESSOR_V850E2V3_UP }, /* true. */ 854 { "sf", 0x8, PROCESSOR_V850E2V3_UP }, /* true. */ 855 { "sne", 0xa, PROCESSOR_V850E2V3_UP }, /* false. */ 856 { "st", 0x8, PROCESSOR_V850E2V3_UP }, /* false. */ 857 { "t", 0x0, PROCESSOR_V850E2V3_UP }, /* false. */ 858 { "ueq", 0x3, PROCESSOR_V850E2V3_UP }, /* true. */ 859 { "uge", 0x4, PROCESSOR_V850E2V3_UP }, /* false. */ 860 { "ugt", 0x6, PROCESSOR_V850E2V3_UP }, /* false. */ 861 { "ule", 0x7, PROCESSOR_V850E2V3_UP }, /* true. */ 862 { "ult", 0x5, PROCESSOR_V850E2V3_UP }, /* true. */ 863 { "un", 0x1, PROCESSOR_V850E2V3_UP }, /* true. */ 864 }; 865 866 #define FLOAT_CC_NAME_CNT \ 867 (sizeof (float_cc_names) / sizeof (struct reg_name)) 868 869 870 static const struct reg_name cacheop_names[] = 871 { 872 { "cfald", 0x44, PROCESSOR_V850E3V5_UP }, 873 { "cfali", 0x40, PROCESSOR_V850E3V5_UP }, 874 { "chbid", 0x04, PROCESSOR_V850E3V5_UP }, 875 { "chbii", 0x00, PROCESSOR_V850E3V5_UP }, 876 { "chbiwbd", 0x06, PROCESSOR_V850E3V5_UP }, 877 { "chbwbd", 0x07, PROCESSOR_V850E3V5_UP }, 878 { "cibid", 0x24, PROCESSOR_V850E3V5_UP }, 879 { "cibii", 0x20, PROCESSOR_V850E3V5_UP }, 880 { "cibiwbd", 0x26, PROCESSOR_V850E3V5_UP }, 881 { "cibwbd", 0x27, PROCESSOR_V850E3V5_UP }, 882 { "cildd", 0x65, PROCESSOR_V850E3V5_UP }, 883 { "cildi", 0x61, PROCESSOR_V850E3V5_UP }, 884 { "cistd", 0x64, PROCESSOR_V850E3V5_UP }, 885 { "cisti", 0x60, PROCESSOR_V850E3V5_UP }, 886 }; 887 888 #define CACHEOP_NAME_CNT \ 889 (sizeof (cacheop_names) / sizeof (struct reg_name)) 890 891 static const struct reg_name prefop_names[] = 892 { 893 { "prefd", 0x04, PROCESSOR_V850E3V5_UP }, 894 { "prefi", 0x00, PROCESSOR_V850E3V5_UP }, 895 }; 896 897 #define PREFOP_NAME_CNT \ 898 (sizeof (prefop_names) / sizeof (struct reg_name)) 899 900 static const struct reg_name vector_registers[] = 901 { 902 { "vr0", 0, PROCESSOR_V850E3V5_UP }, 903 { "vr1", 1, PROCESSOR_V850E3V5_UP }, 904 { "vr10", 10, PROCESSOR_V850E3V5_UP }, 905 { "vr11", 11, PROCESSOR_V850E3V5_UP }, 906 { "vr12", 12, PROCESSOR_V850E3V5_UP }, 907 { "vr13", 13, PROCESSOR_V850E3V5_UP }, 908 { "vr14", 14, PROCESSOR_V850E3V5_UP }, 909 { "vr15", 15, PROCESSOR_V850E3V5_UP }, 910 { "vr16", 16, PROCESSOR_V850E3V5_UP }, 911 { "vr17", 17, PROCESSOR_V850E3V5_UP }, 912 { "vr18", 18, PROCESSOR_V850E3V5_UP }, 913 { "vr19", 19, PROCESSOR_V850E3V5_UP }, 914 { "vr2", 2, PROCESSOR_V850E3V5_UP }, 915 { "vr20", 20, PROCESSOR_V850E3V5_UP }, 916 { "vr21", 21, PROCESSOR_V850E3V5_UP }, 917 { "vr22", 22, PROCESSOR_V850E3V5_UP }, 918 { "vr23", 23, PROCESSOR_V850E3V5_UP }, 919 { "vr24", 24, PROCESSOR_V850E3V5_UP }, 920 { "vr25", 25, PROCESSOR_V850E3V5_UP }, 921 { "vr26", 26, PROCESSOR_V850E3V5_UP }, 922 { "vr27", 27, PROCESSOR_V850E3V5_UP }, 923 { "vr28", 28, PROCESSOR_V850E3V5_UP }, 924 { "vr29", 29, PROCESSOR_V850E3V5_UP }, 925 { "vr3", 3, PROCESSOR_V850E3V5_UP }, 926 { "vr30", 30, PROCESSOR_V850E3V5_UP }, 927 { "vr31", 31, PROCESSOR_V850E3V5_UP }, 928 { "vr4", 4, PROCESSOR_V850E3V5_UP }, 929 { "vr5", 5, PROCESSOR_V850E3V5_UP }, 930 { "vr6", 6, PROCESSOR_V850E3V5_UP }, 931 { "vr7", 7, PROCESSOR_V850E3V5_UP }, 932 { "vr8", 8, PROCESSOR_V850E3V5_UP }, 933 { "vr9", 9, PROCESSOR_V850E3V5_UP }, 934 }; 935 936 #define VREG_NAME_CNT \ 937 (sizeof (vector_registers) / sizeof (struct reg_name)) 938 939 /* Do a binary search of the given register table to see if NAME is a 940 valid regiter name. Return the register number from the array on 941 success, or -1 on failure. */ 942 943 static int 944 reg_name_search (const struct reg_name *regs, 945 int regcount, 946 const char *name, 947 bfd_boolean accept_numbers) 948 { 949 int middle, low, high; 950 int cmp; 951 symbolS *symbolP; 952 953 /* If the register name is a symbol, then evaluate it. */ 954 if ((symbolP = symbol_find (name)) != NULL) 955 { 956 /* If the symbol is an alias for another name then use that. 957 If the symbol is an alias for a number, then return the number. */ 958 if (symbol_equated_p (symbolP)) 959 name 960 = S_GET_NAME (symbol_get_value_expression (symbolP)->X_add_symbol); 961 else if (accept_numbers) 962 { 963 int reg = S_GET_VALUE (symbolP); 964 return reg; 965 } 966 967 /* Otherwise drop through and try parsing name normally. */ 968 } 969 970 low = 0; 971 high = regcount - 1; 972 973 do 974 { 975 middle = (low + high) / 2; 976 cmp = strcasecmp (name, regs[middle].name); 977 if (cmp < 0) 978 high = middle - 1; 979 else if (cmp > 0) 980 low = middle + 1; 981 else 982 return ((regs[middle].processors & processor_mask) 983 ? regs[middle].value 984 : -1); 985 } 986 while (low <= high); 987 return -1; 988 } 989 990 /* Summary of register_name(). 991 992 in: Input_line_pointer points to 1st char of operand. 993 994 out: An expressionS. 995 The operand may have been a register: in this case, X_op == O_register, 996 X_add_number is set to the register number, and truth is returned. 997 Input_line_pointer->(next non-blank) char after operand, or is in 998 its original state. */ 999 1000 static bfd_boolean 1001 register_name (expressionS *expressionP) 1002 { 1003 int reg_number; 1004 char *name; 1005 char *start; 1006 char c; 1007 1008 /* Find the spelling of the operand. */ 1009 start = input_line_pointer; 1010 c = get_symbol_name (&name); 1011 1012 reg_number = reg_name_search (pre_defined_registers, REG_NAME_CNT, 1013 name, FALSE); 1014 1015 /* Put back the delimiting char. */ 1016 (void) restore_line_pointer (c); 1017 1018 expressionP->X_add_symbol = NULL; 1019 expressionP->X_op_symbol = NULL; 1020 1021 /* Look to see if it's in the register table. */ 1022 if (reg_number >= 0) 1023 { 1024 expressionP->X_op = O_register; 1025 expressionP->X_add_number = reg_number; 1026 1027 return TRUE; 1028 } 1029 1030 /* Reset the line as if we had not done anything. */ 1031 input_line_pointer = start; 1032 1033 expressionP->X_op = O_illegal; 1034 1035 return FALSE; 1036 } 1037 1038 /* Summary of system_register_name(). 1039 1040 in: INPUT_LINE_POINTER points to 1st char of operand. 1041 EXPRESSIONP points to an expression structure to be filled in. 1042 ACCEPT_NUMBERS is true iff numerical register names may be used. 1043 1044 out: An expressionS structure in expressionP. 1045 The operand may have been a register: in this case, X_op == O_register, 1046 X_add_number is set to the register number, and truth is returned. 1047 Input_line_pointer->(next non-blank) char after operand, or is in 1048 its original state. */ 1049 1050 static bfd_boolean 1051 system_register_name (expressionS *expressionP, 1052 bfd_boolean accept_numbers) 1053 { 1054 int reg_number; 1055 char *name; 1056 char *start; 1057 char c; 1058 1059 /* Find the spelling of the operand. */ 1060 start = input_line_pointer; 1061 c = get_symbol_name (&name); 1062 reg_number = reg_name_search (system_registers, SYSREG_NAME_CNT, name, 1063 accept_numbers); 1064 1065 /* Put back the delimiting char. */ 1066 (void) restore_line_pointer (c); 1067 1068 if (reg_number < 0 1069 && accept_numbers) 1070 { 1071 /* Reset input_line pointer. */ 1072 input_line_pointer = start; 1073 1074 if (ISDIGIT (*input_line_pointer)) 1075 { 1076 reg_number = strtol (input_line_pointer, &input_line_pointer, 0); 1077 } 1078 } 1079 1080 expressionP->X_add_symbol = NULL; 1081 expressionP->X_op_symbol = NULL; 1082 1083 /* Look to see if it's in the register table. */ 1084 if (reg_number >= 0) 1085 { 1086 expressionP->X_op = O_register; 1087 expressionP->X_add_number = reg_number; 1088 1089 return TRUE; 1090 } 1091 1092 /* Reset the line as if we had not done anything. */ 1093 input_line_pointer = start; 1094 1095 expressionP->X_op = O_illegal; 1096 1097 return FALSE; 1098 } 1099 1100 /* Summary of cc_name(). 1101 1102 in: INPUT_LINE_POINTER points to 1st char of operand. 1103 1104 out: An expressionS. 1105 The operand may have been a register: in this case, X_op == O_register, 1106 X_add_number is set to the register number, and truth is returned. 1107 Input_line_pointer->(next non-blank) char after operand, or is in 1108 its original state. */ 1109 1110 static bfd_boolean 1111 cc_name (expressionS *expressionP, 1112 bfd_boolean accept_numbers) 1113 { 1114 int reg_number; 1115 char *name; 1116 char *start; 1117 char c; 1118 1119 /* Find the spelling of the operand. */ 1120 start = input_line_pointer; 1121 c = get_symbol_name (&name); 1122 reg_number = reg_name_search (cc_names, CC_NAME_CNT, name, accept_numbers); 1123 1124 /* Put back the delimiting char. */ 1125 (void) restore_line_pointer (c); 1126 1127 if (reg_number < 0 1128 && accept_numbers) 1129 { 1130 /* Reset input_line pointer. */ 1131 input_line_pointer = start; 1132 1133 if (ISDIGIT (*input_line_pointer)) 1134 { 1135 reg_number = strtol (input_line_pointer, &input_line_pointer, 0); 1136 } 1137 } 1138 1139 expressionP->X_add_symbol = NULL; 1140 expressionP->X_op_symbol = NULL; 1141 1142 /* Look to see if it's in the register table. */ 1143 if (reg_number >= 0) 1144 { 1145 expressionP->X_op = O_constant; 1146 expressionP->X_add_number = reg_number; 1147 1148 return TRUE; 1149 } 1150 1151 /* Reset the line as if we had not done anything. */ 1152 input_line_pointer = start; 1153 1154 expressionP->X_op = O_illegal; 1155 expressionP->X_add_number = 0; 1156 1157 return FALSE; 1158 } 1159 1160 static bfd_boolean 1161 float_cc_name (expressionS *expressionP, 1162 bfd_boolean accept_numbers) 1163 { 1164 int reg_number; 1165 char *name; 1166 char *start; 1167 char c; 1168 1169 /* Find the spelling of the operand. */ 1170 start = input_line_pointer; 1171 c = get_symbol_name (&name); 1172 reg_number = reg_name_search (float_cc_names, FLOAT_CC_NAME_CNT, name, accept_numbers); 1173 1174 /* Put back the delimiting char. */ 1175 (void) restore_line_pointer (c); 1176 1177 if (reg_number < 0 1178 && accept_numbers) 1179 { 1180 /* Reset input_line pointer. */ 1181 input_line_pointer = start; 1182 1183 if (ISDIGIT (*input_line_pointer)) 1184 { 1185 reg_number = strtol (input_line_pointer, &input_line_pointer, 0); 1186 } 1187 } 1188 1189 expressionP->X_add_symbol = NULL; 1190 expressionP->X_op_symbol = NULL; 1191 1192 /* Look to see if it's in the register table. */ 1193 if (reg_number >= 0) 1194 { 1195 expressionP->X_op = O_constant; 1196 expressionP->X_add_number = reg_number; 1197 1198 return TRUE; 1199 } 1200 1201 /* Reset the line as if we had not done anything. */ 1202 input_line_pointer = start; 1203 1204 expressionP->X_op = O_illegal; 1205 expressionP->X_add_number = 0; 1206 1207 return FALSE; 1208 } 1209 1210 static bfd_boolean 1211 cacheop_name (expressionS * expressionP, 1212 bfd_boolean accept_numbers) 1213 { 1214 int reg_number; 1215 char *name; 1216 char *start; 1217 char c; 1218 1219 /* Find the spelling of the operand. */ 1220 start = input_line_pointer; 1221 c = get_symbol_name (&name); 1222 reg_number = reg_name_search (cacheop_names, CACHEOP_NAME_CNT, name, accept_numbers); 1223 1224 /* Put back the delimiting char. */ 1225 (void) restore_line_pointer (c); 1226 1227 if (reg_number < 0 1228 && accept_numbers) 1229 { 1230 /* Reset input_line pointer. */ 1231 input_line_pointer = start; 1232 1233 if (ISDIGIT (*input_line_pointer)) 1234 reg_number = strtol (input_line_pointer, &input_line_pointer, 0); 1235 } 1236 1237 expressionP->X_add_symbol = NULL; 1238 expressionP->X_op_symbol = NULL; 1239 1240 /* Look to see if it's in the register table. */ 1241 if (reg_number >= 0) 1242 { 1243 expressionP->X_op = O_constant; 1244 expressionP->X_add_number = reg_number; 1245 1246 return TRUE; 1247 } 1248 1249 /* Reset the line as if we had not done anything. */ 1250 input_line_pointer = start; 1251 1252 expressionP->X_op = O_illegal; 1253 expressionP->X_add_number = 0; 1254 1255 return FALSE; 1256 } 1257 1258 static bfd_boolean 1259 prefop_name (expressionS * expressionP, 1260 bfd_boolean accept_numbers) 1261 { 1262 int reg_number; 1263 char *name; 1264 char *start; 1265 char c; 1266 1267 /* Find the spelling of the operand. */ 1268 start = input_line_pointer; 1269 c = get_symbol_name (&name); 1270 reg_number = reg_name_search (prefop_names, PREFOP_NAME_CNT, name, accept_numbers); 1271 1272 /* Put back the delimiting char. */ 1273 (void) restore_line_pointer (c); 1274 1275 if (reg_number < 0 1276 && accept_numbers) 1277 { 1278 /* Reset input_line pointer. */ 1279 input_line_pointer = start; 1280 1281 if (ISDIGIT (*input_line_pointer)) 1282 reg_number = strtol (input_line_pointer, &input_line_pointer, 0); 1283 } 1284 1285 expressionP->X_add_symbol = NULL; 1286 expressionP->X_op_symbol = NULL; 1287 1288 /* Look to see if it's in the register table. */ 1289 if (reg_number >= 0) 1290 { 1291 expressionP->X_op = O_constant; 1292 expressionP->X_add_number = reg_number; 1293 1294 return TRUE; 1295 } 1296 1297 /* Reset the line as if we had not done anything. */ 1298 input_line_pointer = start; 1299 1300 expressionP->X_op = O_illegal; 1301 expressionP->X_add_number = 0; 1302 1303 return FALSE; 1304 } 1305 1306 static bfd_boolean 1307 vector_register_name (expressionS *expressionP) 1308 { 1309 int reg_number; 1310 char *name; 1311 char *start; 1312 char c; 1313 1314 /* Find the spelling of the operand. */ 1315 start = input_line_pointer; 1316 c = get_symbol_name (&name); 1317 1318 reg_number = reg_name_search (vector_registers, VREG_NAME_CNT, 1319 name, FALSE); 1320 1321 /* Put back the delimiting char. */ 1322 (void) restore_line_pointer (c); 1323 1324 expressionP->X_add_symbol = NULL; 1325 expressionP->X_op_symbol = NULL; 1326 1327 /* Look to see if it's in the register table. */ 1328 if (reg_number >= 0) 1329 { 1330 expressionP->X_op = O_register; 1331 expressionP->X_add_number = reg_number; 1332 1333 return TRUE; 1334 } 1335 1336 /* Reset the line as if we had not done anything. */ 1337 input_line_pointer = start; 1338 1339 expressionP->X_op = O_illegal; 1340 1341 return FALSE; 1342 } 1343 1344 static void 1345 skip_white_space (void) 1346 { 1347 while (*input_line_pointer == ' ' 1348 || *input_line_pointer == '\t') 1349 ++input_line_pointer; 1350 } 1351 1352 /* Summary of parse_register_list (). 1353 1354 in: INPUT_LINE_POINTER points to 1st char of a list of registers. 1355 INSN is the partially constructed instruction. 1356 OPERAND is the operand being inserted. 1357 1358 out: NULL if the parse completed successfully, otherwise a 1359 pointer to an error message is returned. If the parse 1360 completes the correct bit fields in the instruction 1361 will be filled in. 1362 1363 Parses register lists with the syntax: 1364 1365 { rX } 1366 { rX, rY } 1367 { rX - rY } 1368 { rX - rY, rZ } 1369 etc 1370 1371 and also parses constant expressions whoes bits indicate the 1372 registers in the lists. The LSB in the expression refers to 1373 the lowest numbered permissible register in the register list, 1374 and so on upwards. System registers are considered to be very 1375 high numbers. */ 1376 1377 static const char * 1378 parse_register_list (unsigned long *insn, 1379 const struct v850_operand *operand) 1380 { 1381 static int type1_regs[32] = 1382 { 1383 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1384 0, 0, 0, 0, 0, 31, 29, 28, 23, 22, 21, 20, 27, 26, 25, 24 1385 }; 1386 1387 int *regs; 1388 expressionS exp; 1389 1390 /* Select a register array to parse. */ 1391 switch (operand->shift) 1392 { 1393 case 0xffe00001: regs = type1_regs; break; 1394 default: 1395 as_bad (_("unknown operand shift: %x\n"), operand->shift); 1396 return _("internal failure in parse_register_list"); 1397 } 1398 1399 skip_white_space (); 1400 1401 /* If the expression starts with a curly brace it is a register list. 1402 Otherwise it is a constant expression, whoes bits indicate which 1403 registers are to be included in the list. */ 1404 if (*input_line_pointer != '{') 1405 { 1406 int reg; 1407 int i; 1408 1409 expression (&exp); 1410 1411 if (exp.X_op != O_constant) 1412 return _("constant expression or register list expected"); 1413 1414 if (regs == type1_regs) 1415 { 1416 if (exp.X_add_number & 0xFFFFF000) 1417 return _("high bits set in register list expression"); 1418 1419 for (reg = 20; reg < 32; reg++) 1420 if (exp.X_add_number & (1 << (reg - 20))) 1421 { 1422 for (i = 0; i < 32; i++) 1423 if (regs[i] == reg) 1424 *insn |= (1 << i); 1425 } 1426 } 1427 1428 return NULL; 1429 } 1430 1431 input_line_pointer++; 1432 1433 /* Parse the register list until a terminator (closing curly brace or 1434 new-line) is found. */ 1435 for (;;) 1436 { 1437 skip_white_space (); 1438 1439 if (register_name (&exp)) 1440 { 1441 int i; 1442 1443 /* Locate the given register in the list, and if it is there, 1444 insert the corresponding bit into the instruction. */ 1445 for (i = 0; i < 32; i++) 1446 { 1447 if (regs[i] == exp.X_add_number) 1448 { 1449 *insn |= (1 << i); 1450 break; 1451 } 1452 } 1453 1454 if (i == 32) 1455 return _("illegal register included in list"); 1456 } 1457 else if (system_register_name (&exp, TRUE)) 1458 { 1459 if (regs == type1_regs) 1460 { 1461 return _("system registers cannot be included in list"); 1462 } 1463 } 1464 1465 if (*input_line_pointer == '}') 1466 { 1467 input_line_pointer++; 1468 break; 1469 } 1470 else if (*input_line_pointer == ',') 1471 { 1472 input_line_pointer++; 1473 continue; 1474 } 1475 else if (*input_line_pointer == '-') 1476 { 1477 /* We have encountered a range of registers: rX - rY. */ 1478 int j; 1479 expressionS exp2; 1480 1481 /* Skip the dash. */ 1482 ++input_line_pointer; 1483 1484 /* Get the second register in the range. */ 1485 if (! register_name (&exp2)) 1486 { 1487 return _("second register should follow dash in register list"); 1488 } 1489 1490 if (exp.X_add_number > exp2.X_add_number) 1491 { 1492 return _("second register should be greater than first register"); 1493 } 1494 1495 /* Add the rest of the registers in the range. */ 1496 for (j = exp.X_add_number + 1; j <= exp2.X_add_number; j++) 1497 { 1498 int i; 1499 1500 /* Locate the given register in the list, and if it is there, 1501 insert the corresponding bit into the instruction. */ 1502 for (i = 0; i < 32; i++) 1503 { 1504 if (regs[i] == j) 1505 { 1506 *insn |= (1 << i); 1507 break; 1508 } 1509 } 1510 1511 if (i == 32) 1512 return _("illegal register included in list"); 1513 } 1514 1515 exp = exp2; 1516 } 1517 else 1518 break; 1519 } 1520 1521 return NULL; 1522 } 1523 1524 const char *md_shortopts = "m:"; 1525 1526 struct option md_longopts[] = 1527 { 1528 #define OPTION_DISP_SIZE_DEFAULT_22 (OPTION_MD_BASE) 1529 {"disp-size-default-22", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_22}, 1530 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 1) 1531 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32}, 1532 {NULL, no_argument, NULL, 0} 1533 }; 1534 1535 size_t md_longopts_size = sizeof (md_longopts); 1536 1537 static bfd_boolean v850_data_8 = FALSE; 1538 1539 void 1540 md_show_usage (FILE *stream) 1541 { 1542 fprintf (stream, _(" V850 options:\n")); 1543 fprintf (stream, _(" -mwarn-signed-overflow Warn if signed immediate values overflow\n")); 1544 fprintf (stream, _(" -mwarn-unsigned-overflow Warn if unsigned immediate values overflow\n")); 1545 fprintf (stream, _(" -mv850 The code is targeted at the v850\n")); 1546 fprintf (stream, _(" -mv850e The code is targeted at the v850e\n")); 1547 fprintf (stream, _(" -mv850e1 The code is targeted at the v850e1\n")); 1548 fprintf (stream, _(" -mv850e2 The code is targeted at the v850e2\n")); 1549 fprintf (stream, _(" -mv850e2v3 The code is targeted at the v850e2v3\n")); 1550 fprintf (stream, _(" -mv850e2v4 Alias for -mv850e3v5\n")); 1551 fprintf (stream, _(" -mv850e3v5 The code is targeted at the v850e3v5\n")); 1552 fprintf (stream, _(" -mrelax Enable relaxation\n")); 1553 fprintf (stream, _(" --disp-size-default-22 branch displacement with unknown size is 22 bits (default)\n")); 1554 fprintf (stream, _(" --disp-size-default-32 branch displacement with unknown size is 32 bits\n")); 1555 fprintf (stream, _(" -mextension enable extension opcode support\n")); 1556 fprintf (stream, _(" -mno-bcond17 disable b<cond> disp17 instruction\n")); 1557 fprintf (stream, _(" -mno-stld23 disable st/ld offset23 instruction\n")); 1558 fprintf (stream, _(" -mgcc-abi Mark the binary as using the old GCC ABI\n")); 1559 fprintf (stream, _(" -mrh850-abi Mark the binary as using the RH850 ABI (default)\n")); 1560 fprintf (stream, _(" -m8byte-align Mark the binary as using 64-bit alignment\n")); 1561 fprintf (stream, _(" -m4byte-align Mark the binary as using 32-bit alignment (default)\n")); 1562 fprintf (stream, _(" -msoft-float Mark the binary as not using FP insns (default for pre e2v3)\n")); 1563 fprintf (stream, _(" -mhard-float Mark the binary as using FP insns (default for e2v3 and up)\n")); 1564 } 1565 1566 int 1567 md_parse_option (int c, const char *arg) 1568 { 1569 if (c != 'm') 1570 { 1571 switch (c) 1572 { 1573 case OPTION_DISP_SIZE_DEFAULT_22: 1574 default_disp_size = 22; 1575 return 1; 1576 1577 case OPTION_DISP_SIZE_DEFAULT_32: 1578 default_disp_size = 32; 1579 return 1; 1580 } 1581 return 0; 1582 } 1583 1584 if (strcmp (arg, "warn-signed-overflow") == 0) 1585 warn_signed_overflows = TRUE; 1586 1587 else if (strcmp (arg, "warn-unsigned-overflow") == 0) 1588 warn_unsigned_overflows = TRUE; 1589 1590 else if (strcmp (arg, "v850") == 0) 1591 { 1592 machine = 0; 1593 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850); 1594 } 1595 else if (strcmp (arg, "v850e") == 0) 1596 { 1597 machine = bfd_mach_v850e; 1598 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E); 1599 } 1600 else if (strcmp (arg, "v850e1") == 0) 1601 { 1602 machine = bfd_mach_v850e1; 1603 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E1); 1604 } 1605 else if (strcmp (arg, "v850e2") == 0) 1606 { 1607 machine = bfd_mach_v850e2; 1608 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2); 1609 } 1610 else if (strcmp (arg, "v850e2v3") == 0) 1611 { 1612 machine = bfd_mach_v850e2v3; 1613 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2V3); 1614 } 1615 else if (strcmp (arg, "v850e2v4") == 0) 1616 { 1617 machine = bfd_mach_v850e3v5; 1618 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5); 1619 } 1620 else if (strcmp (arg, "v850e3v5") == 0) 1621 { 1622 machine = bfd_mach_v850e3v5; 1623 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5); 1624 } 1625 else if (strcmp (arg, "extension") == 0) 1626 { 1627 processor_mask |= PROCESSOR_OPTION_EXTENSION | PROCESSOR_OPTION_ALIAS; 1628 } 1629 else if (strcmp (arg, "no-bcond17") == 0) 1630 { 1631 no_bcond17 = 1; 1632 } 1633 else if (strcmp (arg, "no-stld23") == 0) 1634 { 1635 no_stld23 = 1; 1636 } 1637 else if (strcmp (arg, "relax") == 0) 1638 v850_relax = 1; 1639 else if (strcmp (arg, "gcc-abi") == 0) 1640 { 1641 v850_target_arch = bfd_arch_v850; 1642 v850_target_format = "elf32-v850"; 1643 } 1644 else if (strcmp (arg, "rh850-abi") == 0) 1645 { 1646 v850_target_arch = bfd_arch_v850_rh850; 1647 v850_target_format = "elf32-v850-rh850"; 1648 } 1649 else if (strcmp (arg, "8byte-align") == 0) 1650 { 1651 v850_data_8 = TRUE; 1652 v850_e_flags |= EF_RH850_DATA_ALIGN8; 1653 } 1654 else if (strcmp (arg, "4byte-align") == 0) 1655 { 1656 v850_data_8 = FALSE; 1657 v850_e_flags &= ~ EF_RH850_DATA_ALIGN8; 1658 } 1659 else if (strcmp (arg, "soft-float") == 0) 1660 soft_float = 1; 1661 else if (strcmp (arg, "hard-float") == 0) 1662 soft_float = 0; 1663 else 1664 return 0; 1665 1666 return 1; 1667 } 1668 1669 symbolS * 1670 md_undefined_symbol (char *name ATTRIBUTE_UNUSED) 1671 { 1672 return 0; 1673 } 1674 1675 const char * 1676 md_atof (int type, char *litp, int *sizep) 1677 { 1678 return ieee_md_atof (type, litp, sizep, FALSE); 1679 } 1680 1681 /* Very gross. */ 1682 1683 void 1684 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, 1685 asection *sec, 1686 fragS *fragP) 1687 { 1688 union u 1689 { 1690 bfd_reloc_code_real_type fx_r_type; 1691 char * fr_opcode; 1692 } 1693 opcode_converter; 1694 subseg_change (sec, 0); 1695 1696 opcode_converter.fr_opcode = fragP->fr_opcode; 1697 1698 subseg_change (sec, 0); 1699 1700 if (fragP->fr_subtype == SUBYPTE_LOOP_16_22) 1701 { 1702 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 1703 fragP->fr_offset, 1, 1704 BFD_RELOC_UNUSED + opcode_converter.fx_r_type); 1705 fragP->fr_fix += 4; 1706 } 1707 else if (fragP->fr_subtype == SUBYPTE_LOOP_16_22 + 1) 1708 { 1709 unsigned char * buffer = 1710 (unsigned char *) (fragP->fr_fix + fragP->fr_literal); 1711 int loop_reg = (buffer[0] & 0x1f); 1712 1713 /* Add -1.reg. */ 1714 md_number_to_chars ((char *) buffer, 0x025f | (loop_reg << 11), 2); 1715 /* Now create the conditional branch + fixup to the final target. */ 1716 /* 0x000107ea = bne LBL(disp17). */ 1717 md_number_to_chars ((char *) buffer + 2, 0x000107ea, 4); 1718 fix_new (fragP, fragP->fr_fix+2, 4, fragP->fr_symbol, 1719 fragP->fr_offset, 1, 1720 BFD_RELOC_V850_17_PCREL); 1721 fragP->fr_fix += 6; 1722 } 1723 /* In range conditional or unconditional branch. */ 1724 else if (fragP->fr_subtype == SUBYPTE_COND_9_22 1725 || fragP->fr_subtype == SUBYPTE_UNCOND_9_22 1726 || fragP->fr_subtype == SUBYPTE_COND_9_22_32 1727 || fragP->fr_subtype == SUBYPTE_UNCOND_9_22_32 1728 || fragP->fr_subtype == SUBYPTE_COND_9_17_22 1729 || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32 1730 || fragP->fr_subtype == SUBYPTE_SA_9_22 1731 || fragP->fr_subtype == SUBYPTE_SA_9_22_32 1732 || fragP->fr_subtype == SUBYPTE_SA_9_17_22 1733 || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32) 1734 1735 { 1736 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, 1737 fragP->fr_offset, 1, 1738 BFD_RELOC_UNUSED + opcode_converter.fx_r_type); 1739 fragP->fr_fix += 2; 1740 } 1741 /* V850e2r-v3 17bit conditional branch. */ 1742 else if (fragP->fr_subtype == SUBYPTE_COND_9_17_22 + 1 1743 || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32 + 1 1744 || fragP->fr_subtype == SUBYPTE_SA_9_17_22 + 1 1745 || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32 + 1) 1746 { 1747 unsigned char *buffer = 1748 (unsigned char *) (fragP->fr_fix + fragP->fr_literal); 1749 1750 buffer[0] &= 0x0f; /* Use condition. */ 1751 buffer[0] |= 0xe0; 1752 buffer[1] = 0x07; 1753 1754 /* Now create the unconditional branch + fixup to the final 1755 target. */ 1756 md_number_to_chars ((char *) buffer + 2, 0x0001, 2); 1757 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 1758 fragP->fr_offset, 1, BFD_RELOC_V850_17_PCREL); 1759 fragP->fr_fix += 4; 1760 } 1761 /* Out of range conditional branch. Emit a branch around a 22bit jump. */ 1762 else if (fragP->fr_subtype == SUBYPTE_COND_9_22 + 1 1763 || fragP->fr_subtype == SUBYPTE_COND_9_22_32 + 1 1764 || fragP->fr_subtype == SUBYPTE_COND_9_17_22 + 2 1765 || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32 + 2) 1766 { 1767 unsigned char *buffer = 1768 (unsigned char *) (fragP->fr_fix + fragP->fr_literal); 1769 1770 /* Reverse the condition of the first branch. */ 1771 buffer[0] ^= 0x08; 1772 /* Mask off all the displacement bits. */ 1773 buffer[0] &= 0x8f; 1774 buffer[1] &= 0x07; 1775 /* Now set the displacement bits so that we branch 1776 around the unconditional branch. */ 1777 buffer[0] |= 0x30; 1778 1779 /* Now create the unconditional branch + fixup to the final 1780 target. */ 1781 md_number_to_chars ((char *) buffer + 2, 0x00000780, 4); 1782 fix_new (fragP, fragP->fr_fix + 2, 4, fragP->fr_symbol, 1783 fragP->fr_offset, 1, BFD_RELOC_V850_22_PCREL); 1784 fragP->fr_fix += 6; 1785 } 1786 /* Out of range conditional branch. Emit a branch around a 32bit jump. */ 1787 else if (fragP->fr_subtype == SUBYPTE_COND_9_22_32 + 2 1788 || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32 + 3) 1789 { 1790 unsigned char *buffer = 1791 (unsigned char *) (fragP->fr_fix + fragP->fr_literal); 1792 1793 /* Reverse the condition of the first branch. */ 1794 buffer[0] ^= 0x08; 1795 /* Mask off all the displacement bits. */ 1796 buffer[0] &= 0x8f; 1797 buffer[1] &= 0x07; 1798 /* Now set the displacement bits so that we branch 1799 around the unconditional branch. */ 1800 buffer[0] |= 0x40; 1801 1802 /* Now create the unconditional branch + fixup to the final 1803 target. */ 1804 md_number_to_chars ((char *) buffer + 2, 0x02e0, 2); 1805 fix_new (fragP, fragP->fr_fix + 4, 4, fragP->fr_symbol, 1806 fragP->fr_offset + 2, 1, BFD_RELOC_V850_32_PCREL); 1807 fragP->fr_fix += 8; 1808 } 1809 /* Out of range unconditional branch. Emit a 22bit jump. */ 1810 else if (fragP->fr_subtype == SUBYPTE_UNCOND_9_22 + 1 1811 || fragP->fr_subtype == SUBYPTE_UNCOND_9_22_32 + 1) 1812 { 1813 md_number_to_chars (fragP->fr_fix + fragP->fr_literal, 0x00000780, 4); 1814 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 1815 fragP->fr_offset, 1, BFD_RELOC_V850_22_PCREL); 1816 fragP->fr_fix += 4; 1817 } 1818 /* Out of range unconditional branch. Emit a 32bit jump. */ 1819 else if (fragP->fr_subtype == SUBYPTE_UNCOND_9_22_32 + 2) 1820 { 1821 md_number_to_chars (fragP->fr_fix + fragP->fr_literal, 0x02e0, 2); 1822 fix_new (fragP, fragP->fr_fix + 4, 4, fragP->fr_symbol, 1823 fragP->fr_offset + 2, 1, BFD_RELOC_V850_32_PCREL); 1824 fragP->fr_fix += 6; 1825 } 1826 /* Out of range SA conditional branch. Emit a branch to a 22bit jump. */ 1827 else if (fragP->fr_subtype == SUBYPTE_SA_9_22 + 1 1828 || fragP->fr_subtype == SUBYPTE_SA_9_22_32 + 1 1829 || fragP->fr_subtype == SUBYPTE_SA_9_17_22 + 2 1830 || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32 + 2) 1831 { 1832 unsigned char *buffer = 1833 (unsigned char *) (fragP->fr_fix + fragP->fr_literal); 1834 1835 /* bsa .+4 */ 1836 buffer[0] &= 0x8f; 1837 buffer[0] |= 0x20; 1838 buffer[1] &= 0x07; 1839 1840 /* br .+6 */ 1841 md_number_to_chars ((char *) buffer + 2, 0x05b5, 2); 1842 1843 /* Now create the unconditional branch + fixup to the final 1844 target. */ 1845 /* jr SYM */ 1846 md_number_to_chars ((char *) buffer + 4, 0x00000780, 4); 1847 fix_new (fragP, fragP->fr_fix + 4, 4, fragP->fr_symbol, 1848 fragP->fr_offset, 1, 1849 BFD_RELOC_V850_22_PCREL); 1850 fragP->fr_fix += 8; 1851 } 1852 /* Out of range SA conditional branch. Emit a branch around a 32bit jump. */ 1853 else if (fragP->fr_subtype == SUBYPTE_SA_9_22_32 + 2 1854 || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32 + 3) 1855 { 1856 unsigned char *buffer = 1857 (unsigned char *) (fragP->fr_fix + fragP->fr_literal); 1858 1859 /* bsa .+2 */ 1860 buffer[0] &= 0x8f; 1861 buffer[0] |= 0x20; 1862 buffer[1] &= 0x07; 1863 1864 /* br .+8 */ 1865 md_number_to_chars ((char *) buffer + 2, 0x05c5, 2); 1866 1867 /* Now create the unconditional branch + fixup to the final 1868 target. */ 1869 /* jr SYM */ 1870 md_number_to_chars ((char *) buffer + 4, 0x02e0, 2); 1871 fix_new (fragP, fragP->fr_fix + 6, 4, fragP->fr_symbol, 1872 fragP->fr_offset + 2, 1, BFD_RELOC_V850_32_PCREL); 1873 1874 fragP->fr_fix += 10; 1875 } 1876 else 1877 abort (); 1878 } 1879 1880 valueT 1881 md_section_align (asection *seg, valueT addr) 1882 { 1883 int align = bfd_get_section_alignment (stdoutput, seg); 1884 return ((addr + (1 << align) - 1) & -(1 << align)); 1885 } 1886 1887 void 1888 md_begin (void) 1889 { 1890 const char *prev_name = ""; 1891 const struct v850_opcode *op; 1892 1893 if (strncmp (TARGET_CPU, "v850e3v5", 8) == 0) 1894 { 1895 if (machine == -1) 1896 machine = bfd_mach_v850e3v5; 1897 1898 if (!processor_mask) 1899 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5); 1900 } 1901 else if (strncmp (TARGET_CPU, "v850e2v4", 8) == 0) 1902 { 1903 if (machine == -1) 1904 machine = bfd_mach_v850e3v5; 1905 1906 if (!processor_mask) 1907 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5); 1908 } 1909 else if (strncmp (TARGET_CPU, "v850e2v3", 8) == 0) 1910 { 1911 if (machine == -1) 1912 machine = bfd_mach_v850e2v3; 1913 1914 if (!processor_mask) 1915 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2V3); 1916 } 1917 else if (strncmp (TARGET_CPU, "v850e2", 6) == 0) 1918 { 1919 if (machine == -1) 1920 machine = bfd_mach_v850e2; 1921 1922 if (!processor_mask) 1923 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2); 1924 } 1925 else if (strncmp (TARGET_CPU, "v850e1", 6) == 0) 1926 { 1927 if (machine == -1) 1928 machine = bfd_mach_v850e1; 1929 1930 if (!processor_mask) 1931 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E1); 1932 } 1933 else if (strncmp (TARGET_CPU, "v850e", 5) == 0) 1934 { 1935 if (machine == -1) 1936 machine = bfd_mach_v850e; 1937 1938 if (!processor_mask) 1939 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E); 1940 } 1941 else if (strncmp (TARGET_CPU, "v850", 4) == 0) 1942 { 1943 if (machine == -1) 1944 machine = 0; 1945 1946 if (!processor_mask) 1947 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850); 1948 } 1949 else 1950 /* xgettext:c-format */ 1951 as_bad (_("Unable to determine default target processor from string: %s"), 1952 TARGET_CPU); 1953 1954 if (soft_float == -1) 1955 soft_float = machine < bfd_mach_v850e2v3; 1956 1957 v850_hash = hash_new (); 1958 1959 /* Insert unique names into hash table. The V850 instruction set 1960 has many identical opcode names that have different opcodes based 1961 on the operands. This hash table then provides a quick index to 1962 the first opcode with a particular name in the opcode table. */ 1963 op = v850_opcodes; 1964 while (op->name) 1965 { 1966 if (strcmp (prev_name, op->name)) 1967 { 1968 prev_name = (char *) op->name; 1969 hash_insert (v850_hash, op->name, (char *) op); 1970 } 1971 op++; 1972 } 1973 1974 v850_seg_table[BSS_SECTION].s = bss_section; 1975 bfd_set_arch_mach (stdoutput, v850_target_arch, machine); 1976 bfd_set_private_flags (stdoutput, v850_e_flags); 1977 } 1978 1979 1980 static bfd_reloc_code_real_type 1981 handle_hi016 (const struct v850_operand *operand, const char **errmsg) 1982 { 1983 if (operand == NULL) 1984 return BFD_RELOC_HI16; 1985 1986 if (operand->default_reloc == BFD_RELOC_HI16) 1987 return BFD_RELOC_HI16; 1988 1989 if (operand->default_reloc == BFD_RELOC_HI16_S) 1990 return BFD_RELOC_HI16; 1991 1992 if (operand->default_reloc == BFD_RELOC_16) 1993 return BFD_RELOC_HI16; 1994 1995 *errmsg = _("hi0() relocation used on an instruction which does " 1996 "not support it"); 1997 return BFD_RELOC_64; /* Used to indicate an error condition. */ 1998 } 1999 2000 static bfd_reloc_code_real_type 2001 handle_hi16 (const struct v850_operand *operand, const char **errmsg) 2002 { 2003 if (operand == NULL) 2004 return BFD_RELOC_HI16_S; 2005 2006 if (operand->default_reloc == BFD_RELOC_HI16_S) 2007 return BFD_RELOC_HI16_S; 2008 2009 if (operand->default_reloc == BFD_RELOC_HI16) 2010 return BFD_RELOC_HI16_S; 2011 2012 if (operand->default_reloc == BFD_RELOC_16) 2013 return BFD_RELOC_HI16_S; 2014 2015 *errmsg = _("hi() relocation used on an instruction which does " 2016 "not support it"); 2017 return BFD_RELOC_64; /* Used to indicate an error condition. */ 2018 } 2019 2020 static bfd_reloc_code_real_type 2021 handle_lo16 (const struct v850_operand *operand, const char **errmsg) 2022 { 2023 if (operand == NULL) 2024 return BFD_RELOC_LO16; 2025 2026 if (operand->default_reloc == BFD_RELOC_LO16) 2027 return BFD_RELOC_LO16; 2028 2029 if (operand->default_reloc == BFD_RELOC_V850_16_SPLIT_OFFSET) 2030 return BFD_RELOC_V850_LO16_SPLIT_OFFSET; 2031 2032 if (operand->default_reloc == BFD_RELOC_V850_16_S1) 2033 return BFD_RELOC_V850_LO16_S1; 2034 2035 if (operand->default_reloc == BFD_RELOC_16) 2036 return BFD_RELOC_LO16; 2037 2038 *errmsg = _("lo() relocation used on an instruction which does " 2039 "not support it"); 2040 return BFD_RELOC_64; /* Used to indicate an error condition. */ 2041 } 2042 2043 static bfd_reloc_code_real_type 2044 handle_ctoff (const struct v850_operand *operand, const char **errmsg) 2045 { 2046 if (v850_target_arch == bfd_arch_v850_rh850) 2047 { 2048 *errmsg = _("ctoff() is not supported by the rh850 ABI. Use -mgcc-abi instead"); 2049 return BFD_RELOC_64; /* Used to indicate an error condition. */ 2050 } 2051 2052 if (operand == NULL) 2053 return BFD_RELOC_V850_CALLT_16_16_OFFSET; 2054 2055 if (operand->default_reloc == BFD_RELOC_V850_CALLT_6_7_OFFSET) 2056 return operand->default_reloc; 2057 2058 if (operand->default_reloc == BFD_RELOC_V850_16_S1) 2059 return BFD_RELOC_V850_CALLT_15_16_OFFSET; 2060 2061 if (operand->default_reloc == BFD_RELOC_16) 2062 return BFD_RELOC_V850_CALLT_16_16_OFFSET; 2063 2064 *errmsg = _("ctoff() relocation used on an instruction which does not support it"); 2065 return BFD_RELOC_64; /* Used to indicate an error condition. */ 2066 } 2067 2068 static bfd_reloc_code_real_type 2069 handle_sdaoff (const struct v850_operand *operand, const char **errmsg) 2070 { 2071 if (operand == NULL) 2072 return BFD_RELOC_V850_SDA_16_16_OFFSET; 2073 2074 if (operand->default_reloc == BFD_RELOC_V850_16_SPLIT_OFFSET) 2075 return BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET; 2076 2077 if (operand->default_reloc == BFD_RELOC_16) 2078 return BFD_RELOC_V850_SDA_16_16_OFFSET; 2079 2080 if (operand->default_reloc == BFD_RELOC_V850_16_S1) 2081 return BFD_RELOC_V850_SDA_15_16_OFFSET; 2082 2083 *errmsg = _("sdaoff() relocation used on an instruction which does not support it"); 2084 return BFD_RELOC_64; /* Used to indicate an error condition. */ 2085 } 2086 2087 static bfd_reloc_code_real_type 2088 handle_zdaoff (const struct v850_operand *operand, const char **errmsg) 2089 { 2090 if (operand == NULL) 2091 return BFD_RELOC_V850_ZDA_16_16_OFFSET; 2092 2093 if (operand->default_reloc == BFD_RELOC_V850_16_SPLIT_OFFSET) 2094 return BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET; 2095 2096 if (operand->default_reloc == BFD_RELOC_16) 2097 return BFD_RELOC_V850_ZDA_16_16_OFFSET; 2098 2099 if (operand->default_reloc == BFD_RELOC_V850_16_S1) 2100 return BFD_RELOC_V850_ZDA_15_16_OFFSET; 2101 2102 *errmsg = _("zdaoff() relocation used on an instruction which does not support it"); 2103 return BFD_RELOC_64; /* Used to indicate an error condition. */ 2104 } 2105 2106 static bfd_reloc_code_real_type 2107 handle_tdaoff (const struct v850_operand *operand, const char **errmsg) 2108 { 2109 if (operand == NULL) 2110 /* Data item, not an instruction. */ 2111 return BFD_RELOC_V850_TDA_16_16_OFFSET; 2112 2113 switch (operand->default_reloc) 2114 { 2115 /* sld.hu, operand: D5-4. */ 2116 case BFD_RELOC_V850_TDA_4_5_OFFSET: 2117 /* sld.bu, operand: D4. */ 2118 case BFD_RELOC_V850_TDA_4_4_OFFSET: 2119 /* sld.w/sst.w, operand: D8_6. */ 2120 case BFD_RELOC_V850_TDA_6_8_OFFSET: 2121 /* sld.h/sst.h, operand: D8_7. */ 2122 case BFD_RELOC_V850_TDA_7_8_OFFSET: 2123 /* sld.b/sst.b, operand: D7. */ 2124 case BFD_RELOC_V850_TDA_7_7_OFFSET: 2125 return operand->default_reloc; 2126 default: 2127 break; 2128 } 2129 2130 if (operand->default_reloc == BFD_RELOC_16 && operand->shift == 16) 2131 /* set1 & chums, operands: D16. */ 2132 return BFD_RELOC_V850_TDA_16_16_OFFSET; 2133 2134 *errmsg = _("tdaoff() relocation used on an instruction which does not support it"); 2135 /* Used to indicate an error condition. */ 2136 return BFD_RELOC_64; 2137 } 2138 2139 /* Warning: The code in this function relies upon the definitions 2140 in the v850_operands[] array (defined in opcodes/v850-opc.c) 2141 matching the hard coded values contained herein. */ 2142 2143 static bfd_reloc_code_real_type 2144 v850_reloc_prefix (const struct v850_operand *operand, const char **errmsg) 2145 { 2146 bfd_boolean paren_skipped = FALSE; 2147 2148 /* Skip leading opening parenthesis. */ 2149 if (*input_line_pointer == '(') 2150 { 2151 ++input_line_pointer; 2152 paren_skipped = TRUE; 2153 } 2154 2155 #define CHECK_(name, reloc) \ 2156 if (strncmp (input_line_pointer, name "(", strlen (name) + 1) == 0) \ 2157 { \ 2158 input_line_pointer += strlen (name); \ 2159 return reloc; \ 2160 } 2161 2162 CHECK_ ("hi0", handle_hi016(operand, errmsg) ); 2163 CHECK_ ("hi", handle_hi16(operand, errmsg) ); 2164 CHECK_ ("lo", handle_lo16 (operand, errmsg) ); 2165 CHECK_ ("sdaoff", handle_sdaoff (operand, errmsg)); 2166 CHECK_ ("zdaoff", handle_zdaoff (operand, errmsg)); 2167 CHECK_ ("tdaoff", handle_tdaoff (operand, errmsg)); 2168 CHECK_ ("hilo", BFD_RELOC_32); 2169 CHECK_ ("lo23", BFD_RELOC_V850_23); 2170 CHECK_ ("ctoff", handle_ctoff (operand, errmsg) ); 2171 2172 /* Restore skipped parenthesis. */ 2173 if (paren_skipped) 2174 --input_line_pointer; 2175 2176 return BFD_RELOC_NONE; 2177 } 2178 2179 /* Insert an operand value into an instruction. */ 2180 2181 static unsigned long 2182 v850_insert_operand (unsigned long insn, 2183 const struct v850_operand *operand, 2184 offsetT val, 2185 const char **errmsg) 2186 { 2187 if (operand->insert) 2188 { 2189 const char *message = NULL; 2190 2191 insn = operand->insert (insn, val, &message); 2192 if (message != NULL) 2193 { 2194 if ((operand->flags & V850_OPERAND_SIGNED) 2195 && ! warn_signed_overflows 2196 && v850_msg_is_out_of_range (message)) 2197 { 2198 /* Skip warning... */ 2199 } 2200 else if ((operand->flags & V850_OPERAND_SIGNED) == 0 2201 && ! warn_unsigned_overflows 2202 && v850_msg_is_out_of_range (message)) 2203 { 2204 /* Skip warning... */ 2205 } 2206 else 2207 { 2208 if (errmsg != NULL) 2209 *errmsg = message; 2210 } 2211 } 2212 } 2213 else if (operand->bits == -1 2214 || operand->flags & V850E_IMMEDIATE16 2215 || operand->flags & V850E_IMMEDIATE23 2216 || operand->flags & V850E_IMMEDIATE32) 2217 { 2218 abort (); 2219 } 2220 else 2221 { 2222 if (operand->bits < 32) 2223 { 2224 long min, max; 2225 2226 if ((operand->flags & V850_OPERAND_SIGNED) != 0) 2227 { 2228 if (! warn_signed_overflows) 2229 max = (1 << operand->bits) - 1; 2230 else 2231 max = (1 << (operand->bits - 1)) - 1; 2232 2233 min = -(1 << (operand->bits - 1)); 2234 } 2235 else 2236 { 2237 max = (1 << operand->bits) - 1; 2238 2239 if (! warn_unsigned_overflows) 2240 min = -(1 << (operand->bits - 1)); 2241 else 2242 min = 0; 2243 } 2244 2245 /* Some people write constants with the sign extension done by 2246 hand but only up to 32 bits. This shouldn't really be valid, 2247 but, to permit this code to assemble on a 64-bit host, we 2248 sign extend the 32-bit value to 64 bits if so doing makes the 2249 value valid. */ 2250 if (val > max 2251 && (offsetT) (val - 0x80000000 - 0x80000000) >= min 2252 && (offsetT) (val - 0x80000000 - 0x80000000) <= max) 2253 val = val - 0x80000000 - 0x80000000; 2254 2255 /* Similarly, people write expressions like ~(1<<15), and expect 2256 this to be OK for a 32-bit unsigned value. */ 2257 else if (val < min 2258 && (offsetT) (val + 0x80000000 + 0x80000000) >= min 2259 && (offsetT) (val + 0x80000000 + 0x80000000) <= max) 2260 val = val + 0x80000000 + 0x80000000; 2261 2262 else if (val < (offsetT) min || val > (offsetT) max) 2263 { 2264 static char buf [128]; 2265 2266 /* Restore min and mix to expected values for decimal ranges. */ 2267 if ((operand->flags & V850_OPERAND_SIGNED) 2268 && ! warn_signed_overflows) 2269 max = (1 << (operand->bits - 1)) - 1; 2270 2271 if (! (operand->flags & V850_OPERAND_SIGNED) 2272 && ! warn_unsigned_overflows) 2273 min = 0; 2274 2275 sprintf (buf, _("operand out of range (%d is not between %d and %d)"), 2276 (int) val, (int) min, (int) max); 2277 *errmsg = buf; 2278 } 2279 2280 insn |= (((long) val & ((1 << operand->bits) - 1)) << operand->shift); 2281 } 2282 else 2283 { 2284 insn |= (((long) val) << operand->shift); 2285 } 2286 } 2287 2288 return insn; 2289 } 2290 2291 static char copy_of_instruction[128]; 2293 2294 void 2295 md_assemble (char *str) 2296 { 2297 char *s; 2298 char *start_of_operands; 2299 struct v850_opcode *opcode; 2300 struct v850_opcode *next_opcode; 2301 const unsigned char *opindex_ptr; 2302 int next_opindex; 2303 int relaxable = 0; 2304 unsigned long insn; 2305 unsigned long insn_size; 2306 char *f = NULL; 2307 int i; 2308 int match; 2309 bfd_boolean extra_data_after_insn = FALSE; 2310 unsigned extra_data_len = 0; 2311 unsigned long extra_data = 0; 2312 char *saved_input_line_pointer; 2313 char most_match_errmsg[1024]; 2314 int most_match_count = -1; 2315 2316 strncpy (copy_of_instruction, str, sizeof (copy_of_instruction) - 1); 2317 most_match_errmsg[0] = 0; 2318 2319 /* Get the opcode. */ 2320 for (s = str; *s != '\0' && ! ISSPACE (*s); s++) 2321 continue; 2322 2323 if (*s != '\0') 2324 *s++ = '\0'; 2325 2326 /* Find the first opcode with the proper name. */ 2327 opcode = (struct v850_opcode *) hash_find (v850_hash, str); 2328 if (opcode == NULL) 2329 { 2330 /* xgettext:c-format */ 2331 as_bad (_("Unrecognized opcode: `%s'"), str); 2332 ignore_rest_of_line (); 2333 return; 2334 } 2335 2336 str = s; 2337 while (ISSPACE (*str)) 2338 ++str; 2339 2340 start_of_operands = str; 2341 2342 saved_input_line_pointer = input_line_pointer; 2343 2344 for (;;) 2345 { 2346 const char *errmsg = NULL; 2347 const char *warningmsg = NULL; 2348 2349 match = 0; 2350 opindex_ptr = opcode->operands; 2351 2352 if (no_stld23) 2353 { 2354 if ((strncmp (opcode->name, "st.", 3) == 0 2355 && v850_operands[opcode->operands[1]].bits == 23) 2356 || (strncmp (opcode->name, "ld.", 3) == 0 2357 && v850_operands[opcode->operands[0]].bits == 23)) 2358 { 2359 errmsg = _("st/ld offset 23 instruction was disabled ."); 2360 goto error; 2361 } 2362 } 2363 2364 if ((opcode->processors & processor_mask & PROCESSOR_MASK) == 0 2365 || (((opcode->processors & ~PROCESSOR_MASK) != 0) 2366 && ((opcode->processors & processor_mask & ~PROCESSOR_MASK) == 0))) 2367 { 2368 errmsg = _("Target processor does not support this instruction."); 2369 goto error; 2370 } 2371 2372 relaxable = 0; 2373 fc = 0; 2374 next_opindex = 0; 2375 insn = opcode->opcode; 2376 extra_data_len = 0; 2377 extra_data_after_insn = FALSE; 2378 2379 input_line_pointer = str = start_of_operands; 2380 2381 for (opindex_ptr = opcode->operands; *opindex_ptr != 0; opindex_ptr++) 2382 { 2383 const struct v850_operand *operand; 2384 char *hold; 2385 expressionS ex; 2386 bfd_reloc_code_real_type reloc; 2387 2388 if (next_opindex == 0) 2389 operand = &v850_operands[*opindex_ptr]; 2390 else 2391 { 2392 operand = &v850_operands[next_opindex]; 2393 next_opindex = 0; 2394 } 2395 2396 errmsg = NULL; 2397 2398 while (*str == ' ') 2399 ++str; 2400 2401 if (operand->flags & V850_OPERAND_BANG 2402 && *str == '!') 2403 ++str; 2404 else if (operand->flags & V850_OPERAND_PERCENT 2405 && *str == '%') 2406 ++str; 2407 2408 if (*str == ',' || *str == '[' || *str == ']') 2409 ++str; 2410 2411 while (*str == ' ') 2412 ++str; 2413 2414 if ( (strcmp (opcode->name, "pushsp") == 0 2415 || strcmp (opcode->name, "popsp") == 0 2416 || strcmp (opcode->name, "dbpush") == 0) 2417 && (*str == '-')) 2418 ++str; 2419 2420 if (operand->flags & V850_OPERAND_RELAX) 2421 relaxable = 1; 2422 2423 /* Gather the operand. */ 2424 hold = input_line_pointer; 2425 input_line_pointer = str; 2426 2427 /* lo(), hi(), hi0(), etc... */ 2428 if ((reloc = v850_reloc_prefix (operand, &errmsg)) != BFD_RELOC_NONE) 2429 { 2430 /* This is a fake reloc, used to indicate an error condition. */ 2431 if (reloc == BFD_RELOC_64) 2432 { 2433 /* match = 1; */ 2434 goto error; 2435 } 2436 2437 expression (&ex); 2438 2439 if (ex.X_op == O_constant) 2440 { 2441 switch (reloc) 2442 { 2443 case BFD_RELOC_V850_ZDA_16_16_OFFSET: 2444 case BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET: 2445 case BFD_RELOC_V850_ZDA_15_16_OFFSET: 2446 /* To cope with "not1 7, zdaoff(0xfffff006)[r0]" 2447 and the like. */ 2448 /* Fall through. */ 2449 2450 case BFD_RELOC_LO16: 2451 case BFD_RELOC_V850_LO16_S1: 2452 case BFD_RELOC_V850_LO16_SPLIT_OFFSET: 2453 { 2454 /* Truncate, then sign extend the value. */ 2455 ex.X_add_number = SEXT16 (ex.X_add_number); 2456 break; 2457 } 2458 2459 case BFD_RELOC_HI16: 2460 { 2461 /* Truncate, then sign extend the value. */ 2462 ex.X_add_number = SEXT16 (ex.X_add_number >> 16); 2463 break; 2464 } 2465 2466 case BFD_RELOC_HI16_S: 2467 { 2468 /* Truncate, then sign extend the value. */ 2469 int temp = (ex.X_add_number >> 16) & 0xffff; 2470 2471 temp += (ex.X_add_number >> 15) & 1; 2472 2473 ex.X_add_number = SEXT16 (temp); 2474 break; 2475 } 2476 2477 case BFD_RELOC_V850_23: 2478 if ((operand->flags & V850E_IMMEDIATE23) == 0) 2479 { 2480 errmsg = _("immediate operand is too large"); 2481 goto error; 2482 } 2483 break; 2484 2485 case BFD_RELOC_32: 2486 case BFD_RELOC_V850_32_ABS: 2487 case BFD_RELOC_V850_32_PCREL: 2488 if ((operand->flags & V850E_IMMEDIATE32) == 0) 2489 { 2490 errmsg = _("immediate operand is too large"); 2491 goto error; 2492 } 2493 2494 break; 2495 2496 default: 2497 as_bad (_("AAARG -> unhandled constant reloc: %d"), reloc); 2498 break; 2499 } 2500 2501 if (operand->flags & V850E_IMMEDIATE32) 2502 { 2503 extra_data_after_insn = TRUE; 2504 extra_data_len = 4; 2505 extra_data = 0; 2506 } 2507 else if (operand->flags & V850E_IMMEDIATE23) 2508 { 2509 if (reloc != BFD_RELOC_V850_23) 2510 { 2511 errmsg = _("immediate operand is too large"); 2512 goto error; 2513 } 2514 extra_data_after_insn = TRUE; 2515 extra_data_len = 2; 2516 extra_data = 0; 2517 } 2518 else if ((operand->flags & V850E_IMMEDIATE16) 2519 || (operand->flags & V850E_IMMEDIATE16HI)) 2520 { 2521 if (operand->flags & V850E_IMMEDIATE16HI 2522 && reloc != BFD_RELOC_HI16 2523 && reloc != BFD_RELOC_HI16_S) 2524 { 2525 errmsg = _("immediate operand is too large"); 2526 goto error; 2527 } 2528 else if (operand->flags & V850E_IMMEDIATE16 2529 && reloc != BFD_RELOC_LO16) 2530 { 2531 errmsg = _("immediate operand is too large"); 2532 goto error; 2533 } 2534 2535 extra_data_after_insn = TRUE; 2536 extra_data_len = 2; 2537 extra_data = 0; 2538 } 2539 2540 if (fc > MAX_INSN_FIXUPS) 2541 as_fatal (_("too many fixups")); 2542 2543 fixups[fc].exp = ex; 2544 fixups[fc].opindex = *opindex_ptr; 2545 fixups[fc].reloc = reloc; 2546 fc++; 2547 } 2548 else /* ex.X_op != O_constant. */ 2549 { 2550 if ((reloc == BFD_RELOC_32 2551 || reloc == BFD_RELOC_V850_32_ABS 2552 || reloc == BFD_RELOC_V850_32_PCREL) 2553 && operand->bits < 32) 2554 { 2555 errmsg = _("immediate operand is too large"); 2556 goto error; 2557 } 2558 else if (reloc == BFD_RELOC_V850_23 2559 && (operand->flags & V850E_IMMEDIATE23) == 0) 2560 { 2561 errmsg = _("immediate operand is too large"); 2562 goto error; 2563 } 2564 else if ((reloc == BFD_RELOC_HI16 2565 || reloc == BFD_RELOC_HI16_S) 2566 && operand->bits < 16) 2567 { 2568 errmsg = _("immediate operand is too large"); 2569 goto error; 2570 } 2571 2572 if (operand->flags & V850E_IMMEDIATE32) 2573 { 2574 extra_data_after_insn = TRUE; 2575 extra_data_len = 4; 2576 extra_data = 0; 2577 } 2578 else if (operand->flags & V850E_IMMEDIATE23) 2579 { 2580 if (reloc != BFD_RELOC_V850_23) 2581 { 2582 errmsg = _("immediate operand is too large"); 2583 goto error; 2584 } 2585 extra_data_after_insn = TRUE; 2586 extra_data_len = 2; 2587 extra_data = 0; 2588 } 2589 else if ((operand->flags & V850E_IMMEDIATE16) 2590 || (operand->flags & V850E_IMMEDIATE16HI)) 2591 { 2592 if (operand->flags & V850E_IMMEDIATE16HI 2593 && reloc != BFD_RELOC_HI16 2594 && reloc != BFD_RELOC_HI16_S) 2595 { 2596 errmsg = _("immediate operand is too large"); 2597 goto error; 2598 } 2599 else if (operand->flags & V850E_IMMEDIATE16 2600 && reloc != BFD_RELOC_LO16) 2601 { 2602 errmsg = _("immediate operand is too large"); 2603 goto error; 2604 } 2605 2606 extra_data_after_insn = TRUE; 2607 extra_data_len = 2; 2608 extra_data = 0; 2609 } 2610 2611 if (fc > MAX_INSN_FIXUPS) 2612 as_fatal (_("too many fixups")); 2613 2614 fixups[fc].exp = ex; 2615 fixups[fc].opindex = *opindex_ptr; 2616 fixups[fc].reloc = reloc; 2617 fc++; 2618 } 2619 } 2620 else if (operand->flags & V850E_IMMEDIATE16 2621 || operand->flags & V850E_IMMEDIATE16HI) 2622 { 2623 expression (&ex); 2624 2625 switch (ex.X_op) 2626 { 2627 case O_constant: 2628 if (operand->flags & V850E_IMMEDIATE16HI) 2629 { 2630 if (ex.X_add_number & 0xffff) 2631 { 2632 errmsg = _("constant too big to fit into instruction"); 2633 goto error; 2634 } 2635 2636 ex.X_add_number >>= 16; 2637 } 2638 if (operand->flags & V850E_IMMEDIATE16) 2639 { 2640 if ((ex.X_add_number & 0xffff8000) 2641 && ((ex.X_add_number & 0xffff8000) != 0xffff8000)) 2642 { 2643 errmsg = _("constant too big to fit into instruction"); 2644 goto error; 2645 } 2646 } 2647 break; 2648 2649 case O_illegal: 2650 errmsg = _("illegal operand"); 2651 goto error; 2652 2653 case O_absent: 2654 errmsg = _("missing operand"); 2655 goto error; 2656 2657 default: 2658 if (fc >= MAX_INSN_FIXUPS) 2659 as_fatal (_("too many fixups")); 2660 2661 fixups[fc].exp = ex; 2662 fixups[fc].opindex = *opindex_ptr; 2663 fixups[fc].reloc = operand->default_reloc; 2664 ++fc; 2665 2666 ex.X_add_number = 0; 2667 break; 2668 } 2669 2670 extra_data_after_insn = TRUE; 2671 extra_data_len = 2; 2672 extra_data = ex.X_add_number; 2673 } 2674 else if (operand->flags & V850E_IMMEDIATE23) 2675 { 2676 expression (&ex); 2677 2678 switch (ex.X_op) 2679 { 2680 case O_constant: 2681 break; 2682 2683 case O_illegal: 2684 errmsg = _("illegal operand"); 2685 goto error; 2686 2687 case O_absent: 2688 errmsg = _("missing operand"); 2689 goto error; 2690 2691 default: 2692 break; 2693 } 2694 2695 if (fc >= MAX_INSN_FIXUPS) 2696 as_fatal (_("too many fixups")); 2697 2698 fixups[fc].exp = ex; 2699 fixups[fc].opindex = *opindex_ptr; 2700 fixups[fc].reloc = operand->default_reloc; 2701 ++fc; 2702 2703 extra_data_after_insn = TRUE; 2704 extra_data_len = 2; 2705 extra_data = 0; 2706 } 2707 else if (operand->flags & V850E_IMMEDIATE32) 2708 { 2709 expression (&ex); 2710 2711 switch (ex.X_op) 2712 { 2713 case O_constant: 2714 if ((operand->default_reloc == BFD_RELOC_V850_32_ABS 2715 || operand->default_reloc == BFD_RELOC_V850_32_PCREL) 2716 && (ex.X_add_number & 1)) 2717 { 2718 errmsg = _("odd number cannot be used here"); 2719 goto error; 2720 } 2721 break; 2722 2723 case O_illegal: 2724 errmsg = _("illegal operand"); 2725 goto error; 2726 2727 case O_absent: 2728 errmsg = _("missing operand"); 2729 goto error; 2730 2731 default: 2732 if (fc >= MAX_INSN_FIXUPS) 2733 as_fatal (_("too many fixups")); 2734 2735 fixups[fc].exp = ex; 2736 fixups[fc].opindex = *opindex_ptr; 2737 fixups[fc].reloc = operand->default_reloc; 2738 ++fc; 2739 2740 ex.X_add_number = 0; 2741 break; 2742 } 2743 2744 extra_data_after_insn = TRUE; 2745 extra_data_len = 4; 2746 extra_data = ex.X_add_number; 2747 } 2748 else if (operand->flags & V850E_OPERAND_REG_LIST) 2749 { 2750 errmsg = parse_register_list (&insn, operand); 2751 2752 if (errmsg) 2753 goto error; 2754 } 2755 else 2756 { 2757 errmsg = NULL; 2758 2759 if ((operand->flags & V850_OPERAND_REG) != 0) 2760 { 2761 if (!register_name (&ex)) 2762 { 2763 errmsg = _("invalid register name"); 2764 } 2765 2766 if ((operand->flags & V850_NOT_R0) 2767 && ex.X_add_number == 0) 2768 { 2769 errmsg = _("register r0 cannot be used here"); 2770 } 2771 2772 if (operand->flags & V850_REG_EVEN) 2773 { 2774 if (ex.X_add_number % 2) 2775 errmsg = _("odd register cannot be used here"); 2776 ex.X_add_number = ex.X_add_number / 2; 2777 } 2778 2779 } 2780 else if ((operand->flags & V850_OPERAND_SRG) != 0) 2781 { 2782 if (!system_register_name (&ex, TRUE)) 2783 { 2784 errmsg = _("invalid system register name"); 2785 } 2786 } 2787 else if ((operand->flags & V850_OPERAND_EP) != 0) 2788 { 2789 char *start = input_line_pointer; 2790 char *name; 2791 char c = get_symbol_name (&name); 2792 2793 if (strcmp (name, "ep") != 0 && strcmp (name, "r30") != 0) 2794 { 2795 /* Put things back the way we found them. */ 2796 (void) restore_line_pointer (c); 2797 input_line_pointer = start; 2798 errmsg = _("expected EP register"); 2799 goto error; 2800 } 2801 2802 (void) restore_line_pointer (c); 2803 str = input_line_pointer; 2804 input_line_pointer = hold; 2805 2806 while (*str == ' ' || *str == ',' 2807 || *str == '[' || *str == ']') 2808 ++str; 2809 continue; 2810 } 2811 else if ((operand->flags & V850_OPERAND_CC) != 0) 2812 { 2813 if (!cc_name (&ex, TRUE)) 2814 { 2815 errmsg = _("invalid condition code name"); 2816 } 2817 2818 if ((operand->flags & V850_NOT_SA) 2819 && ex.X_add_number == COND_SA_NUM) 2820 { 2821 errmsg = _("condition sa cannot be used here"); 2822 } 2823 } 2824 else if ((operand->flags & V850_OPERAND_FLOAT_CC) != 0) 2825 { 2826 if (!float_cc_name (&ex, TRUE)) 2827 { 2828 errmsg = _("invalid condition code name"); 2829 } 2830 } 2831 else if ((operand->flags & V850_OPERAND_CACHEOP) != 0) 2832 { 2833 if (!cacheop_name (&ex, TRUE)) 2834 errmsg = _("invalid cache oparation name"); 2835 } 2836 else if ((operand->flags & V850_OPERAND_PREFOP) != 0) 2837 { 2838 if (!prefop_name (&ex, TRUE)) 2839 errmsg = _("invalid pref oparation name"); 2840 } 2841 else if ((operand->flags & V850_OPERAND_VREG) != 0) 2842 { 2843 if (!vector_register_name (&ex)) 2844 errmsg = _("invalid vector register name"); 2845 } 2846 else if ((register_name (&ex) 2847 && (operand->flags & V850_OPERAND_REG) == 0)) 2848 { 2849 char *name; 2850 char c; 2851 int exists = 0; 2852 2853 /* It is possible that an alias has been defined that 2854 matches a register name. For example the code may 2855 include a ".set ZERO, 0" directive, which matches 2856 the register name "zero". Attempt to reparse the 2857 field as an expression, and only complain if we 2858 cannot generate a constant. */ 2859 2860 input_line_pointer = str; 2861 2862 c = get_symbol_name (&name); 2863 2864 if (symbol_find (name) != NULL) 2865 exists = 1; 2866 2867 (void) restore_line_pointer (c); 2868 input_line_pointer = str; 2869 2870 expression (&ex); 2871 2872 if (ex.X_op != O_constant) 2873 { 2874 /* If this register is actually occurring too early on 2875 the parsing of the instruction, (because another 2876 field is missing) then report this. */ 2877 if (opindex_ptr[1] != 0 2878 && ((v850_operands[opindex_ptr[1]].flags 2879 & V850_OPERAND_REG) 2880 ||(v850_operands[opindex_ptr[1]].flags 2881 & V850_OPERAND_VREG))) 2882 errmsg = _("syntax error: value is missing before the register name"); 2883 else 2884 errmsg = _("syntax error: register not expected"); 2885 2886 /* If we created a symbol in the process of this 2887 test then delete it now, so that it will not 2888 be output with the real symbols... */ 2889 if (exists == 0 2890 && ex.X_op == O_symbol) 2891 symbol_remove (ex.X_add_symbol, 2892 &symbol_rootP, &symbol_lastP); 2893 } 2894 } 2895 else if (system_register_name (&ex, FALSE) 2896 && (operand->flags & V850_OPERAND_SRG) == 0) 2897 { 2898 errmsg = _("syntax error: system register not expected"); 2899 } 2900 else if (cc_name (&ex, FALSE) 2901 && (operand->flags & V850_OPERAND_CC) == 0) 2902 { 2903 errmsg = _("syntax error: condition code not expected"); 2904 } 2905 else if (float_cc_name (&ex, FALSE) 2906 && (operand->flags & V850_OPERAND_FLOAT_CC) == 0) 2907 { 2908 errmsg = _("syntax error: condition code not expected"); 2909 } 2910 else if (vector_register_name (&ex) 2911 && (operand->flags & V850_OPERAND_VREG) == 0) 2912 { 2913 errmsg = _("syntax error: vector register not expected"); 2914 } 2915 else 2916 { 2917 expression (&ex); 2918 2919 if ((operand->flags & V850_NOT_IMM0) 2920 && ex.X_op == O_constant 2921 && ex.X_add_number == 0) 2922 { 2923 errmsg = _("immediate 0 cannot be used here"); 2924 } 2925 2926 /* Special case: 2927 If we are assembling a MOV/JARL/JR instruction and the immediate 2928 value does not fit into the bits available then create a 2929 fake error so that the next MOV/JARL/JR instruction will be 2930 selected. This one has a 32 bit immediate field. */ 2931 2932 if ((strcmp (opcode->name, "mov") == 0 2933 || strcmp (opcode->name, "jarl") == 0 2934 || strcmp (opcode->name, "jr") == 0) 2935 && ex.X_op == O_constant 2936 && (ex.X_add_number < (-(1 << (operand->bits - 1))) 2937 || ex.X_add_number > ((1 << (operand->bits - 1)) - 1))) 2938 { 2939 errmsg = _("immediate operand is too large"); 2940 } 2941 2942 if ((strcmp (opcode->name, "jarl") == 0 2943 || strcmp (opcode->name, "jr") == 0) 2944 && ex.X_op != O_constant 2945 && operand->bits != default_disp_size) 2946 { 2947 errmsg = _("immediate operand is not match"); 2948 } 2949 2950 /* Special case2 : 2951 If we are assembling a ld/st instruction and the immediate 2952 value does not fit into the bits available then create a 2953 fake error so that the next ld/st instruction will be 2954 selected. */ 2955 if ( ( (strncmp (opcode->name, "st.", 3) == 0) 2956 || (strncmp (opcode->name, "ld.", 3) == 0)) 2957 && ex.X_op == O_constant 2958 && (ex.X_add_number < (-(1 << (operand->bits - 1))) 2959 || ex.X_add_number > ((1 << (operand->bits - 1)) - 1))) 2960 errmsg = _("displacement is too large"); 2961 } 2962 2963 if (errmsg) 2964 goto error; 2965 2966 switch (ex.X_op) 2967 { 2968 case O_illegal: 2969 errmsg = _("illegal operand"); 2970 goto error; 2971 case O_absent: 2972 errmsg = _("missing operand"); 2973 goto error; 2974 case O_register: 2975 if ((operand->flags 2976 & (V850_OPERAND_REG | V850_OPERAND_SRG | V850_OPERAND_VREG)) == 0) 2977 { 2978 errmsg = _("invalid operand"); 2979 goto error; 2980 } 2981 2982 insn = v850_insert_operand (insn, operand, 2983 ex.X_add_number, 2984 &warningmsg); 2985 2986 break; 2987 2988 case O_constant: 2989 insn = v850_insert_operand (insn, operand, ex.X_add_number, 2990 &warningmsg); 2991 break; 2992 2993 default: 2994 /* We need to generate a fixup for this expression. */ 2995 if (fc >= MAX_INSN_FIXUPS) 2996 as_fatal (_("too many fixups")); 2997 2998 fixups[fc].exp = ex; 2999 fixups[fc].opindex = *opindex_ptr; 3000 fixups[fc].reloc = BFD_RELOC_NONE; 3001 ++fc; 3002 break; 3003 } 3004 } 3005 3006 str = input_line_pointer; 3007 input_line_pointer = hold; 3008 3009 while (*str == ' ' || *str == ',' || *str == '[' || *str == ']' 3010 || *str == ')') 3011 ++str; 3012 } 3013 3014 while (ISSPACE (*str)) 3015 ++str; 3016 3017 if (*str == '\0') 3018 match = 1; 3019 3020 error: 3021 if (match == 0) 3022 { 3023 if ((opindex_ptr - opcode->operands) >= most_match_count) 3024 { 3025 most_match_count = opindex_ptr - opcode->operands; 3026 if (errmsg != NULL) 3027 strncpy (most_match_errmsg, errmsg, sizeof (most_match_errmsg)-1); 3028 } 3029 3030 next_opcode = opcode + 1; 3031 if (next_opcode->name != NULL 3032 && strcmp (next_opcode->name, opcode->name) == 0) 3033 { 3034 opcode = next_opcode; 3035 3036 /* Skip versions that are not supported by the target 3037 processor. */ 3038 if ((opcode->processors & processor_mask) == 0) 3039 goto error; 3040 3041 continue; 3042 } 3043 3044 if (most_match_errmsg[0] == 0) 3045 /* xgettext:c-format. */ 3046 as_bad (_("junk at end of line: `%s'"), str); 3047 else 3048 as_bad ("%s: %s", copy_of_instruction, most_match_errmsg); 3049 3050 if (*input_line_pointer == ']') 3051 ++input_line_pointer; 3052 3053 ignore_rest_of_line (); 3054 input_line_pointer = saved_input_line_pointer; 3055 return; 3056 } 3057 3058 if (warningmsg != NULL) 3059 as_warn ("%s", warningmsg); 3060 break; 3061 } 3062 3063 input_line_pointer = str; 3064 3065 /* Tie dwarf2 debug info to the address at the start of the insn. 3066 We can't do this after the insn has been output as the current 3067 frag may have been closed off. eg. by frag_var. */ 3068 dwarf2_emit_insn (0); 3069 3070 /* Write out the instruction. */ 3071 3072 if (relaxable && fc > 0) 3073 { 3074 insn_size = 2; 3075 fc = 0; 3076 3077 if (strcmp (opcode->name, "loop") == 0) 3078 { 3079 if (((processor_mask & PROCESSOR_V850E3V5_UP) == 0) || default_disp_size == 22) 3080 { 3081 insn_size = 4; 3082 f = frag_var (rs_machine_dependent, 6, 2, SUBYPTE_LOOP_16_22, 3083 fixups[0].exp.X_add_symbol, 3084 fixups[0].exp.X_add_number, 3085 (char *)(size_t) fixups[0].opindex); 3086 md_number_to_chars (f, insn, insn_size); 3087 md_number_to_chars (f+4, 0, 4); 3088 } 3089 else 3090 { 3091 as_bad (_("loop: 32-bit displacement not supported")); 3092 } 3093 } 3094 else if (strcmp (opcode->name, "br") == 0 3095 || strcmp (opcode->name, "jbr") == 0) 3096 { 3097 if ((processor_mask & PROCESSOR_V850E2_UP) == 0 || default_disp_size == 22) 3098 { 3099 f = frag_var (rs_machine_dependent, 4, 2, SUBYPTE_UNCOND_9_22, 3100 fixups[0].exp.X_add_symbol, 3101 fixups[0].exp.X_add_number, 3102 (char *)(size_t) fixups[0].opindex); 3103 md_number_to_chars (f, insn, insn_size); 3104 md_number_to_chars (f + 2, 0, 2); 3105 } 3106 else 3107 { 3108 f = frag_var (rs_machine_dependent, 6, 4, SUBYPTE_UNCOND_9_22_32, 3109 fixups[0].exp.X_add_symbol, 3110 fixups[0].exp.X_add_number, 3111 (char *)(size_t) fixups[0].opindex); 3112 md_number_to_chars (f, insn, insn_size); 3113 md_number_to_chars (f + 2, 0, 4); 3114 } 3115 } 3116 else /* b<cond>, j<cond>. */ 3117 { 3118 if (default_disp_size == 22 3119 || (processor_mask & PROCESSOR_V850E2_UP) == 0) 3120 { 3121 if (processor_mask & PROCESSOR_V850E2V3_UP && !no_bcond17) 3122 { 3123 if (strcmp (opcode->name, "bsa") == 0) 3124 { 3125 f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_SA_9_17_22, 3126 fixups[0].exp.X_add_symbol, 3127 fixups[0].exp.X_add_number, 3128 (char *)(size_t) fixups[0].opindex); 3129 md_number_to_chars (f, insn, insn_size); 3130 md_number_to_chars (f + 2, 0, 6); 3131 } 3132 else 3133 { 3134 f = frag_var (rs_machine_dependent, 6, 4, SUBYPTE_COND_9_17_22, 3135 fixups[0].exp.X_add_symbol, 3136 fixups[0].exp.X_add_number, 3137 (char *)(size_t) fixups[0].opindex); 3138 md_number_to_chars (f, insn, insn_size); 3139 md_number_to_chars (f + 2, 0, 4); 3140 } 3141 } 3142 else 3143 { 3144 if (strcmp (opcode->name, "bsa") == 0) 3145 { 3146 f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_SA_9_22, 3147 fixups[0].exp.X_add_symbol, 3148 fixups[0].exp.X_add_number, 3149 (char *)(size_t) fixups[0].opindex); 3150 md_number_to_chars (f, insn, insn_size); 3151 md_number_to_chars (f + 2, 0, 6); 3152 } 3153 else 3154 { 3155 f = frag_var (rs_machine_dependent, 6, 4, SUBYPTE_COND_9_22, 3156 fixups[0].exp.X_add_symbol, 3157 fixups[0].exp.X_add_number, 3158 (char *)(size_t) fixups[0].opindex); 3159 md_number_to_chars (f, insn, insn_size); 3160 md_number_to_chars (f + 2, 0, 4); 3161 } 3162 } 3163 } 3164 else 3165 { 3166 if (processor_mask & PROCESSOR_V850E2V3_UP && !no_bcond17) 3167 { 3168 if (strcmp (opcode->name, "bsa") == 0) 3169 { 3170 f = frag_var (rs_machine_dependent, 10, 8, SUBYPTE_SA_9_17_22_32, 3171 fixups[0].exp.X_add_symbol, 3172 fixups[0].exp.X_add_number, 3173 (char *)(size_t) fixups[0].opindex); 3174 md_number_to_chars (f, insn, insn_size); 3175 md_number_to_chars (f + 2, 0, 8); 3176 } 3177 else 3178 { 3179 f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_COND_9_17_22_32, 3180 fixups[0].exp.X_add_symbol, 3181 fixups[0].exp.X_add_number, 3182 (char *)(size_t) fixups[0].opindex); 3183 md_number_to_chars (f, insn, insn_size); 3184 md_number_to_chars (f + 2, 0, 6); 3185 } 3186 } 3187 else 3188 { 3189 if (strcmp (opcode->name, "bsa") == 0) 3190 { 3191 f = frag_var (rs_machine_dependent, 10, 8, SUBYPTE_SA_9_22_32, 3192 fixups[0].exp.X_add_symbol, 3193 fixups[0].exp.X_add_number, 3194 (char *)(size_t) fixups[0].opindex); 3195 md_number_to_chars (f, insn, insn_size); 3196 md_number_to_chars (f + 2, 0, 8); 3197 } 3198 else 3199 { 3200 f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_COND_9_22_32, 3201 fixups[0].exp.X_add_symbol, 3202 fixups[0].exp.X_add_number, 3203 (char *)(size_t) fixups[0].opindex); 3204 md_number_to_chars (f, insn, insn_size); 3205 md_number_to_chars (f + 2, 0, 6); 3206 } 3207 } 3208 } 3209 } 3210 } 3211 else 3212 { 3213 /* Four byte insns have an opcode with the two high bits on. */ 3214 if ((insn & 0x0600) == 0x0600) 3215 insn_size = 4; 3216 else 3217 insn_size = 2; 3218 3219 /* Special case: 32 bit MOV. */ 3220 if ((insn & 0xffe0) == 0x0620) 3221 insn_size = 2; 3222 3223 /* Special case: 32 bit JARL,JMP,JR. */ 3224 if ((insn & 0x1ffe0) == 0x2e0 /* JARL. */ 3225 || (insn & 0x1ffe0) == 0x6e0 /* JMP. */ 3226 || (insn & 0x1ffff) == 0x2e0) /* JR. */ 3227 insn_size = 2; 3228 3229 if (obstack_room (& frchain_now->frch_obstack) < (insn_size + extra_data_len)) 3230 { 3231 frag_wane (frag_now); 3232 frag_new (0); 3233 } 3234 3235 f = frag_more (insn_size); 3236 md_number_to_chars (f, insn, insn_size); 3237 3238 if (extra_data_after_insn) 3239 { 3240 f = frag_more (extra_data_len); 3241 md_number_to_chars (f, extra_data, extra_data_len); 3242 3243 extra_data_after_insn = FALSE; 3244 } 3245 } 3246 3247 /* Create any fixups. At this point we do not use a 3248 bfd_reloc_code_real_type, but instead just use the 3249 BFD_RELOC_UNUSED plus the operand index. This lets us easily 3250 handle fixups for any operand type, although that is admittedly 3251 not a very exciting feature. We pick a BFD reloc type in 3252 md_apply_fix. */ 3253 for (i = 0; i < fc; i++) 3254 { 3255 const struct v850_operand *operand; 3256 bfd_reloc_code_real_type reloc; 3257 3258 operand = &v850_operands[fixups[i].opindex]; 3259 3260 reloc = fixups[i].reloc; 3261 3262 if (reloc != BFD_RELOC_NONE) 3263 { 3264 reloc_howto_type *reloc_howto = 3265 bfd_reloc_type_lookup (stdoutput, reloc); 3266 int size; 3267 int address; 3268 fixS *fixP; 3269 3270 if (!reloc_howto) 3271 abort (); 3272 3273 size = bfd_get_reloc_size (reloc_howto); 3274 3275 /* XXX This will abort on an R_V850_8 reloc - 3276 is this reloc actually used? */ 3277 if (size != 2 && size != 4) 3278 abort (); 3279 3280 if (extra_data_len == 0) 3281 { 3282 address = (f - frag_now->fr_literal) + insn_size - size; 3283 } 3284 else 3285 { 3286 address = (f - frag_now->fr_literal) + extra_data_len - size; 3287 } 3288 3289 if ((operand->flags & V850E_IMMEDIATE32) && (operand->flags & V850_PCREL)) 3290 { 3291 fixups[i].exp.X_add_number += 2; 3292 } 3293 else if (operand->default_reloc == BFD_RELOC_V850_16_PCREL) 3294 { 3295 fixups[i].exp.X_add_number += 2; 3296 address += 2; 3297 } 3298 3299 /* fprintf (stderr, "0x%x %d %ld\n", address, size, fixups[i].exp.X_add_number); */ 3300 fixP = fix_new_exp (frag_now, address, size, 3301 &fixups[i].exp, 3302 reloc_howto->pc_relative, 3303 reloc); 3304 3305 fixP->tc_fix_data = (void *) operand; 3306 3307 switch (reloc) 3308 { 3309 case BFD_RELOC_LO16: 3310 case BFD_RELOC_V850_LO16_S1: 3311 case BFD_RELOC_V850_LO16_SPLIT_OFFSET: 3312 case BFD_RELOC_HI16: 3313 case BFD_RELOC_HI16_S: 3314 fixP->fx_no_overflow = 1; 3315 break; 3316 default: 3317 break; 3318 } 3319 } 3320 else 3321 { 3322 gas_assert (f != NULL); 3323 fix_new_exp (frag_now, 3324 f - frag_now->fr_literal, 4, 3325 & fixups[i].exp, 3326 (operand->flags & V850_PCREL) != 0, 3327 (bfd_reloc_code_real_type) (fixups[i].opindex 3328 + (int) BFD_RELOC_UNUSED)); 3329 } 3330 } 3331 3332 input_line_pointer = saved_input_line_pointer; 3333 } 3334 3335 /* If while processing a fixup, a reloc really needs to be created 3336 then it is done here. */ 3337 3338 arelent * 3339 tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp) 3340 { 3341 arelent *reloc; 3342 3343 reloc = XNEW (arelent); 3344 reloc->sym_ptr_ptr = XNEW (asymbol *); 3345 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 3346 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 3347 3348 if ( fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY 3349 || fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT 3350 || fixp->fx_r_type == BFD_RELOC_V850_LONGCALL 3351 || fixp->fx_r_type == BFD_RELOC_V850_LONGJUMP 3352 || fixp->fx_r_type == BFD_RELOC_V850_ALIGN) 3353 reloc->addend = fixp->fx_offset; 3354 else 3355 { 3356 #if 0 3357 if (fixp->fx_r_type == BFD_RELOC_32 3358 && fixp->fx_pcrel) 3359 fixp->fx_r_type = BFD_RELOC_32_PCREL; 3360 #endif 3361 3362 reloc->addend = fixp->fx_addnumber; 3363 } 3364 3365 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); 3366 3367 if (reloc->howto == NULL) 3368 { 3369 as_bad_where (fixp->fx_file, fixp->fx_line, 3370 /* xgettext:c-format */ 3371 _("reloc %d not supported by object file format"), 3372 (int) fixp->fx_r_type); 3373 3374 xfree (reloc); 3375 3376 return NULL; 3377 } 3378 3379 return reloc; 3380 } 3381 3382 void 3383 v850_handle_align (fragS * frag) 3384 { 3385 if (v850_relax 3386 && frag->fr_type == rs_align 3387 && frag->fr_address + frag->fr_fix > 0 3388 && frag->fr_offset > 1 3389 && now_seg != bss_section 3390 && now_seg != v850_seg_table[SBSS_SECTION].s 3391 && now_seg != v850_seg_table[TBSS_SECTION].s 3392 && now_seg != v850_seg_table[ZBSS_SECTION].s) 3393 fix_new (frag, frag->fr_fix, 2, & abs_symbol, frag->fr_offset, 0, 3394 BFD_RELOC_V850_ALIGN); 3395 } 3396 3397 /* Return current size of variable part of frag. */ 3398 3399 int 3400 md_estimate_size_before_relax (fragS *fragp, asection *seg ATTRIBUTE_UNUSED) 3401 { 3402 if (fragp->fr_subtype >= sizeof (md_relax_table) / sizeof (md_relax_table[0])) 3403 abort (); 3404 3405 return md_relax_table[fragp->fr_subtype].rlx_length; 3406 } 3407 3408 long 3409 v850_pcrel_from_section (fixS *fixp, segT section) 3410 { 3411 /* If the symbol is undefined, or in a section other than our own, 3412 or it is weak (in which case it may well be in another section, 3413 then let the linker figure it out. */ 3414 if (fixp->fx_addsy != (symbolS *) NULL 3415 && (! S_IS_DEFINED (fixp->fx_addsy) 3416 || S_IS_WEAK (fixp->fx_addsy) 3417 || (S_GET_SEGMENT (fixp->fx_addsy) != section))) 3418 return 0; 3419 3420 return fixp->fx_frag->fr_address + fixp->fx_where; 3421 } 3422 3423 void 3424 md_apply_fix (fixS *fixP, valueT *valueP, segT seg ATTRIBUTE_UNUSED) 3425 { 3426 valueT value = * valueP; 3427 char *where; 3428 3429 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 3430 || fixP->fx_r_type == BFD_RELOC_V850_LONGCALL 3431 || fixP->fx_r_type == BFD_RELOC_V850_LONGJUMP 3432 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 3433 { 3434 fixP->fx_done = 0; 3435 return; 3436 } 3437 3438 if (fixP->fx_addsy == (symbolS *) NULL) 3439 fixP->fx_addnumber = value, 3440 fixP->fx_done = 1; 3441 3442 else if (fixP->fx_pcrel) 3443 fixP->fx_addnumber = fixP->fx_offset; 3444 3445 else 3446 { 3447 value = fixP->fx_offset; 3448 if (fixP->fx_subsy != (symbolS *) NULL) 3449 { 3450 if (S_GET_SEGMENT (fixP->fx_subsy) == absolute_section) 3451 value -= S_GET_VALUE (fixP->fx_subsy); 3452 else 3453 /* We don't actually support subtracting a symbol. */ 3454 as_bad_where (fixP->fx_file, fixP->fx_line, 3455 _("expression too complex")); 3456 } 3457 fixP->fx_addnumber = value; 3458 } 3459 3460 if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED) 3461 { 3462 int opindex; 3463 const struct v850_operand *operand; 3464 unsigned long insn; 3465 const char *errmsg = NULL; 3466 3467 opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED; 3468 operand = &v850_operands[opindex]; 3469 3470 /* Fetch the instruction, insert the fully resolved operand 3471 value, and stuff the instruction back again. 3472 3473 Note the instruction has been stored in little endian 3474 format! */ 3475 where = fixP->fx_frag->fr_literal + fixP->fx_where; 3476 3477 if (fixP->fx_size > 2) 3478 insn = bfd_getl32 ((unsigned char *) where); 3479 else 3480 insn = bfd_getl16 ((unsigned char *) where); 3481 3482 /* When inserting loop offets a backwards displacement 3483 is encoded as a positive value. */ 3484 if (operand->flags & V850_INVERSE_PCREL) 3485 value = - value; 3486 3487 insn = v850_insert_operand (insn, operand, (offsetT) value, 3488 &errmsg); 3489 if (errmsg) 3490 as_warn_where (fixP->fx_file, fixP->fx_line, "%s", errmsg); 3491 3492 if (fixP->fx_size > 2) 3493 bfd_putl32 ((bfd_vma) insn, (unsigned char *) where); 3494 else 3495 bfd_putl16 ((bfd_vma) insn, (unsigned char *) where); 3496 3497 if (fixP->fx_done) 3498 /* Nothing else to do here. */ 3499 return; 3500 3501 /* Determine a BFD reloc value based on the operand information. 3502 We are only prepared to turn a few of the operands into relocs. */ 3503 3504 if (operand->default_reloc == BFD_RELOC_NONE) 3505 { 3506 as_bad_where (fixP->fx_file, fixP->fx_line, 3507 _("unresolved expression that must be resolved")); 3508 fixP->fx_done = 1; 3509 return; 3510 } 3511 3512 { 3513 fixP->fx_r_type = operand->default_reloc; 3514 if (operand->default_reloc == BFD_RELOC_V850_16_PCREL) 3515 { 3516 fixP->fx_where += 2; 3517 fixP->fx_size = 2; 3518 fixP->fx_addnumber += 2; 3519 } 3520 } 3521 } 3522 else if (fixP->fx_done) 3523 { 3524 /* We still have to insert the value into memory! */ 3525 where = fixP->fx_frag->fr_literal + fixP->fx_where; 3526 3527 if (fixP->tc_fix_data != NULL 3528 && ((struct v850_operand *) fixP->tc_fix_data)->insert != NULL) 3529 { 3530 const char * message = NULL; 3531 struct v850_operand * operand = (struct v850_operand *) fixP->tc_fix_data; 3532 unsigned long insn; 3533 3534 /* The variable "where" currently points at the exact point inside 3535 the insn where we need to insert the value. But we need to 3536 extract the entire insn so we probably need to move "where" 3537 back a few bytes. */ 3538 3539 if (fixP->fx_size == 2) 3540 where -= 2; 3541 else if (fixP->fx_size == 1) 3542 where -= 3; 3543 3544 insn = bfd_getl32 ((unsigned char *) where); 3545 3546 /* Use the operand's insertion procedure, if present, in order to 3547 make sure that the value is correctly stored in the insn. */ 3548 insn = operand->insert (insn, (offsetT) value, & message); 3549 /* Ignore message even if it is set. */ 3550 3551 bfd_putl32 ((bfd_vma) insn, (unsigned char *) where); 3552 } 3553 else 3554 { 3555 switch (fixP->fx_r_type) 3556 { 3557 case BFD_RELOC_V850_32_ABS: 3558 case BFD_RELOC_V850_32_PCREL: 3559 bfd_putl32 (value & 0xfffffffe, (unsigned char *) where); 3560 break; 3561 3562 case BFD_RELOC_32: 3563 bfd_putl32 (value, (unsigned char *) where); 3564 break; 3565 3566 case BFD_RELOC_V850_23: 3567 bfd_putl32 (((value & 0x7f) << 4) | ((value & 0x7fff80) << (16-7)) 3568 | (bfd_getl32 (where) & ~((0x7f << 4) | (0xffff << 16))), 3569 (unsigned char *) where); 3570 break; 3571 3572 case BFD_RELOC_16: 3573 case BFD_RELOC_HI16: 3574 case BFD_RELOC_HI16_S: 3575 case BFD_RELOC_LO16: 3576 case BFD_RELOC_V850_ZDA_16_16_OFFSET: 3577 case BFD_RELOC_V850_SDA_16_16_OFFSET: 3578 case BFD_RELOC_V850_TDA_16_16_OFFSET: 3579 case BFD_RELOC_V850_CALLT_16_16_OFFSET: 3580 bfd_putl16 (value & 0xffff, (unsigned char *) where); 3581 break; 3582 3583 case BFD_RELOC_8: 3584 *where = value & 0xff; 3585 break; 3586 3587 case BFD_RELOC_V850_9_PCREL: 3588 bfd_putl16 (((value & 0x1f0) << 7) | ((value & 0x0e) << 3) 3589 | (bfd_getl16 (where) & ~((0x1f0 << 7) | (0x0e << 3))), where); 3590 break; 3591 3592 case BFD_RELOC_V850_17_PCREL: 3593 bfd_putl32 (((value & 0x10000) >> (16 - 4)) | ((value & 0xfffe) << 16) 3594 | (bfd_getl32 (where) & ~((0x10000 >> (16 - 4)) | (0xfffe << 16))), where); 3595 break; 3596 3597 case BFD_RELOC_V850_16_PCREL: 3598 bfd_putl16 ((-value & 0xfffe) | (bfd_getl16 (where + 2) & 0x0001), 3599 (unsigned char *) (where + 2)); 3600 break; 3601 3602 case BFD_RELOC_V850_22_PCREL: 3603 bfd_putl32 (((value & 0xfffe) << 16) | ((value & 0x3f0000) >> 16) 3604 | (bfd_getl32 (where) & ~((0xfffe << 16) | (0x3f0000 >> 16))), where); 3605 break; 3606 3607 case BFD_RELOC_V850_16_S1: 3608 case BFD_RELOC_V850_LO16_S1: 3609 case BFD_RELOC_V850_ZDA_15_16_OFFSET: 3610 case BFD_RELOC_V850_SDA_15_16_OFFSET: 3611 bfd_putl16 (value & 0xfffe, (unsigned char *) where); 3612 break; 3613 3614 case BFD_RELOC_V850_16_SPLIT_OFFSET: 3615 case BFD_RELOC_V850_LO16_SPLIT_OFFSET: 3616 case BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET: 3617 case BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET: 3618 bfd_putl32 (((value << 16) & 0xfffe0000) 3619 | ((value << 5) & 0x20) 3620 | (bfd_getl32 (where) & ~0xfffe0020), where); 3621 break; 3622 3623 case BFD_RELOC_V850_TDA_6_8_OFFSET: 3624 *where = (*where & ~0x7e) | ((value >> 1) & 0x7e); 3625 break; 3626 3627 case BFD_RELOC_V850_TDA_7_8_OFFSET: 3628 *where = (*where & ~0x7f) | ((value >> 1) & 0x7f); 3629 break; 3630 3631 case BFD_RELOC_V850_TDA_7_7_OFFSET: 3632 *where = (*where & ~0x7f) | (value & 0x7f); 3633 break; 3634 3635 case BFD_RELOC_V850_TDA_4_5_OFFSET: 3636 *where = (*where & ~0xf) | ((value >> 1) & 0xf); 3637 break; 3638 3639 case BFD_RELOC_V850_TDA_4_4_OFFSET: 3640 *where = (*where & ~0xf) | (value & 0xf); 3641 break; 3642 3643 case BFD_RELOC_V850_CALLT_6_7_OFFSET: 3644 *where = (*where & ~0x3f) | (value & 0x3f); 3645 break; 3646 3647 default: 3648 abort (); 3649 } 3650 } 3651 } 3652 } 3653 3654 /* Parse a cons expression. We have to handle hi(), lo(), etc 3655 on the v850. */ 3656 3657 bfd_reloc_code_real_type 3658 parse_cons_expression_v850 (expressionS *exp) 3659 { 3660 const char *errmsg; 3661 bfd_reloc_code_real_type r; 3662 3663 /* See if there's a reloc prefix like hi() we have to handle. */ 3664 r = v850_reloc_prefix (NULL, &errmsg); 3665 3666 /* Do normal expression parsing. */ 3667 expression (exp); 3668 return r; 3669 } 3670 3671 /* Create a fixup for a cons expression. If parse_cons_expression_v850 3672 found a reloc prefix, then we use that reloc, else we choose an 3673 appropriate one based on the size of the expression. */ 3674 3675 void 3676 cons_fix_new_v850 (fragS *frag, 3677 int where, 3678 int size, 3679 expressionS *exp, 3680 bfd_reloc_code_real_type r) 3681 { 3682 if (r == BFD_RELOC_NONE) 3683 { 3684 if (size == 4) 3685 r = BFD_RELOC_32; 3686 if (size == 2) 3687 r = BFD_RELOC_16; 3688 if (size == 1) 3689 r = BFD_RELOC_8; 3690 } 3691 3692 if (exp != NULL) 3693 fix_new_exp (frag, where, size, exp, 0, r); 3694 else 3695 fix_new (frag, where, size, NULL, 0, 0, r); 3696 } 3697 3698 bfd_boolean 3699 v850_fix_adjustable (fixS *fixP) 3700 { 3701 if (fixP->fx_addsy == NULL) 3702 return 1; 3703 3704 /* Don't adjust function names. */ 3705 if (S_IS_FUNCTION (fixP->fx_addsy)) 3706 return 0; 3707 3708 /* We need the symbol name for the VTABLE entries. */ 3709 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 3710 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 3711 return 0; 3712 3713 return 1; 3714 } 3715 3716 int 3717 v850_force_relocation (struct fix *fixP) 3718 { 3719 if (fixP->fx_r_type == BFD_RELOC_V850_LONGCALL 3720 || fixP->fx_r_type == BFD_RELOC_V850_LONGJUMP) 3721 return 1; 3722 3723 if (v850_relax 3724 && (fixP->fx_pcrel 3725 || fixP->fx_r_type == BFD_RELOC_V850_ALIGN 3726 || fixP->fx_r_type == BFD_RELOC_V850_9_PCREL 3727 || fixP->fx_r_type == BFD_RELOC_V850_16_PCREL 3728 || fixP->fx_r_type == BFD_RELOC_V850_17_PCREL 3729 || fixP->fx_r_type == BFD_RELOC_V850_22_PCREL 3730 || fixP->fx_r_type == BFD_RELOC_V850_32_PCREL 3731 || fixP->fx_r_type >= BFD_RELOC_UNUSED)) 3732 return 1; 3733 3734 return generic_force_reloc (fixP); 3735 } 3736 3737 /* Create a v850 note section. */ 3738 void 3739 v850_md_end (void) 3740 { 3741 segT note_sec; 3742 segT orig_seg = now_seg; 3743 subsegT orig_subseg = now_subseg; 3744 enum v850_notes id; 3745 3746 note_sec = subseg_new (V850_NOTE_SECNAME, 0); 3747 bfd_set_section_flags (stdoutput, note_sec, SEC_HAS_CONTENTS | SEC_READONLY | SEC_MERGE); 3748 bfd_set_section_alignment (stdoutput, note_sec, 2); 3749 3750 /* Provide default values for all of the notes. */ 3751 for (id = V850_NOTE_ALIGNMENT; id <= NUM_V850_NOTES; id++) 3752 { 3753 int val = 0; 3754 char * p; 3755 3756 /* Follow the standard note section layout: 3757 First write the length of the name string. */ 3758 p = frag_more (4); 3759 md_number_to_chars (p, 4, 4); 3760 3761 /* Next comes the length of the "descriptor", i.e., the actual data. */ 3762 p = frag_more (4); 3763 md_number_to_chars (p, 4, 4); 3764 3765 /* Write the note type. */ 3766 p = frag_more (4); 3767 md_number_to_chars (p, (valueT) id, 4); 3768 3769 /* Write the name field. */ 3770 p = frag_more (4); 3771 memcpy (p, V850_NOTE_NAME, 4); 3772 3773 /* Finally, write the descriptor. */ 3774 p = frag_more (4); 3775 switch (id) 3776 { 3777 case V850_NOTE_ALIGNMENT: 3778 val = v850_data_8 ? EF_RH850_DATA_ALIGN8 : EF_RH850_DATA_ALIGN4; 3779 break; 3780 3781 case V850_NOTE_DATA_SIZE: 3782 /* GCC does not currently support an option 3783 for 32-bit doubles with the V850 backend. */ 3784 val = EF_RH850_DOUBLE64; 3785 break; 3786 3787 case V850_NOTE_FPU_INFO: 3788 if (! soft_float) 3789 switch (machine) 3790 { 3791 case bfd_mach_v850e3v5: val = EF_RH850_FPU30; break; 3792 case bfd_mach_v850e2v3: val = EF_RH850_FPU20; break; 3793 default: break; 3794 } 3795 break; 3796 3797 default: 3798 break; 3799 } 3800 md_number_to_chars (p, val, 4); 3801 } 3802 3803 /* Paranoia - we probably do not need this. */ 3804 subseg_set (orig_seg, orig_subseg); 3805 } 3806
