1 /*++ 2 3 Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR> 4 5 This program and the accompanying materials are licensed and made available under 7 the terms and conditions of the BSD License that accompanies this distribution. 9 The full text of the license may be found at 11 http://opensource.org/licenses/bsd-license.php. 13 15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 17 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 19 21 23 24 Module Name: 25 26 PlatformCpuInfo.h 27 28 Abstract: 29 30 GUID used for Platform CPU Info Data entries in the HOB list. 31 32 --*/ 33 34 #ifndef _PLATFORM_CPU_INFO_GUID_H_ 35 #define _PLATFORM_CPU_INFO_GUID_H_ 36 37 #include "CpuType.h" 38 #include <Library/CpuIA32.h> 39 40 #define EFI_PLATFORM_CPU_INFO_GUID \ 41 {\ 42 0xbb9c7ab7, 0xb8d9, 0x4bf3, 0x9c, 0x29, 0x9b, 0xf3, 0x41, 0xe2, 0x17, 0xbc \ 43 } 44 45 extern EFI_GUID gEfiPlatformCpuInfoGuid; 46 extern CHAR16 EfiPlatformCpuInfoVariable[]; 47 48 // 49 // Tri-state for feature capabilities and enable/disable. 50 // [0] clear=feature isn't capable 51 // [0] set =feature is capable 52 // [1] clear=feature is disabled 53 // [1] set =feature is enabled 54 // 55 #define CPU_FEATURES_CAPABLE BIT0 56 #define CPU_FEATURES_ENABLE BIT1 57 58 #define MAX_CACHE_DESCRIPTORS 64 59 #define MAXIMUM_CPU_BRAND_STRING_LENGTH 48 60 61 #pragma pack(1) 62 63 typedef struct { 64 UINT32 FullCpuId; // [31:0] & 0x0FFF0FFF 65 UINT32 FullFamilyModelId; // [31:0] & 0x0FFF0FF0 66 UINT8 ExtendedFamilyId; // [27:20] 67 UINT8 ExtendedModelId; // [19:16] 68 UINT8 ProcessorType; // [13:11] 69 UINT8 FamilyId; // [11:8] 70 UINT8 Model; // [7:4] 71 UINT8 SteppingId; // [3:0] 72 } EFI_CPU_VERSION_INFO; // CPUID.1.EAX 73 74 typedef struct { 75 UINT32 L1InstructionCacheSize; 76 UINT32 L1DataCacheSize; 77 UINT32 L2CacheSize; 78 UINT32 L3CacheSize; 79 UINT32 TraceCacheSize; 80 UINT8 CacheDescriptor[MAX_CACHE_DESCRIPTORS]; 81 } EFI_CPU_CACHE_INFO; // CPUID.2.EAX 82 83 typedef struct { 84 UINT8 PhysicalPackages; 85 UINT8 LogicalProcessorsPerPhysicalPackage; 86 UINT8 CoresPerPhysicalPackage; 87 UINT8 ThreadsPerCore; 88 } EFI_CPU_PACKAGE_INFO; // CPUID.4.EAX 89 90 typedef struct { 91 UINT32 RegEdx; // CPUID.5.EAX 92 UINT8 MaxCState; 93 UINT8 C0SubCStatesMwait; // EDX [3:0] 94 UINT8 C1SubCStatesMwait; // EDX [7:4] 95 UINT8 C2SubCStatesMwait; // EDX [11:8] 96 UINT8 C3SubCStatesMwait; // EDX [15:12] 97 UINT8 C4SubCStatesMwait; // EDX [19:16] 98 UINT8 C5SubCStatesMwait; // EDX [23:20] 99 UINT8 C6SubCStatesMwait; // EDX [27:24] 100 UINT8 C7SubCStatesMwait; // EDX [31:28] 101 UINT8 MonitorMwaitSupport; // ECX [0] 102 UINT8 InterruptsBreakMwait; // ECX [1] 103 } EFI_CPU_CSTATE_INFO; // CPUID.5.EAX 104 105 typedef struct { 106 UINT8 Turbo; // EAX [1] 107 UINT8 PECI; // EAX [0] 108 UINT8 NumIntThresholds; // EBX [3:0] 109 UINT8 HwCoordinationFeedback; // ECX [0] 110 } EFI_CPU_POWER_MANAGEMENT; // CPUID.6.EAX 111 112 // 113 // IMPORTANT: Each CPU feature enabling entry is assumed a tri-state variable. 114 // - Keep the respective feature entry variable as default value (0x00) 115 // if the CPU is not capable for the feature. 116 // - Use the specially defined programming convention to update the variable 117 // to indicate capable, enable or disable. 118 // ie. F_CAPABLE for feature available 119 // F_ENABLE for feature enable 120 // F_DISABLE for feature disable 121 // 122 typedef struct { 123 EFI_CPUID_REGISTER Regs; // CPUID.1.EAX 124 UINT8 Xapic; // ECX [21] 125 UINT8 SSE4_2; // ECX [20] 126 UINT8 SSE4_1; // ECX [19] 127 UINT8 Dca; // ECX [18] 128 UINT8 SupSSE3; // ECX [9] 129 UINT8 Tm2; // ECX [8] 130 UINT8 Eist; // ECX [7] 131 UINT8 Lt; // ECX [6] 132 UINT8 Vt; // ECX [5] 133 UINT8 Mwait; // ECX [3] 134 UINT8 SSE3; // ECX [0] 135 UINT8 Tcc; // EDX [29] 136 UINT8 Mt; // EDX [28] 137 UINT8 SSE2; // EDX [26] 138 UINT8 SSE; // EDX [25] 139 UINT8 MMX; // EDX [23] 140 EFI_CPUID_REGISTER ExtRegs; // CPUID.80000001.EAX 141 UINT8 ExtLahfSahf64; // ECX [0] 142 UINT8 ExtIntel64; // EDX [29] 143 UINT8 ExtXd; // EDX [20] 144 UINT8 ExtSysCallRet64; // EDX [11] 145 UINT16 Ht; // CPUID.0B.EAX EBX [15:0] 146 } EFI_CPU_FEATURES; // CPUID.1.EAX, CPUID.0B.EAX, CPUID.80000001.EAX 147 148 typedef struct { 149 UINT8 PhysicalBits; 150 UINT8 VirtualBits; 151 } EFI_CPU_ADDRESS_BITS; // CPUID.80000008.EAX 152 153 typedef struct { 154 UINT8 PlatformID; // MSR 0x17 [52:50] 155 UINT32 MicrocodeRevision; // MSR 0x8B [63:32] 156 UINT8 MaxEfficiencyRatio; // MSR 0xCE [47:40] 157 UINT8 DdrRatioUnlockCap; // MSR 0xCE [30] 158 UINT8 TdcTdpLimitsTurbo; // MSR 0xCE [29] 159 UINT8 RatioLimitsTurbo; // MSR 0xCE [28] 160 UINT8 PreProduction; // MSR 0xCE [27] 161 UINT8 DcuModeSelect; // MSR 0xCE [26] 162 UINT8 MaxNonTurboRatio; // MSR 0xCE [15:8] 163 UINT8 Emrr; // MSR 0xFE [12] 164 UINT8 Smrr; // MSR 0xFE [11] 165 UINT8 VariableMtrrCount; // MSR 0xFE [7:0] 166 UINT16 PState; // MSR 0x198 [15:0] 167 UINT8 TccActivationTemperature; // MSR 0x1A2 [23:16] 168 UINT8 TemperatureControlOffset; // MSR 0x1A2 [15:8] 169 UINT32 PCIeBar; // MSR 0x300 [39:20] 170 UINT8 PCIeBarSizeMB; // MSR 0x300 [3:1] 171 } EFI_MSR_FEATURES; 172 173 typedef struct { 174 BOOLEAN IsIntelProcessor; 175 UINT8 BrandString[MAXIMUM_CPU_BRAND_STRING_LENGTH + 1]; 176 UINT32 CpuidMaxInputValue; 177 UINT32 CpuidMaxExtInputValue; 178 EFI_CPU_UARCH CpuUarch; 179 EFI_CPU_FAMILY CpuFamily; 180 EFI_CPU_PLATFORM CpuPlatform; 181 EFI_CPU_TYPE CpuType; 182 EFI_CPU_VERSION_INFO CpuVersion; 183 EFI_CPU_CACHE_INFO CpuCache; 184 EFI_CPU_FEATURES CpuFeatures; 185 EFI_CPU_CSTATE_INFO CpuCState; 186 EFI_CPU_PACKAGE_INFO CpuPackage; 187 EFI_CPU_POWER_MANAGEMENT CpuPowerManagement; 188 EFI_CPU_ADDRESS_BITS CpuAddress; 189 EFI_MSR_FEATURES Msr; 190 } EFI_PLATFORM_CPU_INFO; 191 192 #pragma pack() 193 194 #endif 195
