| /external/llvm/examples/OCaml-Kaleidoscope/Chapter2/ |
| token.ml | 9 | Def | Extern
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| /external/llvm/examples/OCaml-Kaleidoscope/Chapter3/ |
| token.ml | 9 | Def | Extern
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| /external/llvm/examples/OCaml-Kaleidoscope/Chapter4/ |
| token.ml | 9 | Def | Extern
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| /external/llvm/examples/OCaml-Kaleidoscope/Chapter5/ |
| token.ml | 9 | Def | Extern
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| /external/llvm/examples/OCaml-Kaleidoscope/Chapter6/ |
| token.ml | 9 | Def | Extern
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| /external/llvm/examples/OCaml-Kaleidoscope/Chapter7/ |
| token.ml | 9 | Def | Extern
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| /external/swiftshader/third_party/LLVM/examples/OCaml-Kaleidoscope/Chapter2/ |
| token.ml | 9 | Def | Extern
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| /external/swiftshader/third_party/LLVM/examples/OCaml-Kaleidoscope/Chapter3/ |
| token.ml | 9 | Def | Extern
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| /external/swiftshader/third_party/LLVM/examples/OCaml-Kaleidoscope/Chapter4/ |
| token.ml | 9 | Def | Extern
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| /external/swiftshader/third_party/LLVM/examples/OCaml-Kaleidoscope/Chapter5/ |
| token.ml | 9 | Def | Extern
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| /external/swiftshader/third_party/LLVM/examples/OCaml-Kaleidoscope/Chapter6/ |
| token.ml | 9 | Def | Extern
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| /external/swiftshader/third_party/LLVM/examples/OCaml-Kaleidoscope/Chapter7/ |
| token.ml | 9 | Def | Extern
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| /external/lzma/CPP/Common/ |
| MyTypes.h | 13 bool Def;
15 CBoolPair(): Val(false), Def(false) {}
20 Def = false;
26 Def = true;
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| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyLowerBrUnless.cpp | 75 MachineInstr *Def = MRI.getVRegDef(Cond);
76 switch (Def->getOpcode()) {
78 case EQ_I32: Def->setDesc(TII.get(NE_I32)); Inverted = true; break;
79 case NE_I32: Def->setDesc(TII.get(EQ_I32)); Inverted = true; break;
80 case GT_S_I32: Def->setDesc(TII.get(LE_S_I32)); Inverted = true; break;
81 case GE_S_I32: Def->setDesc(TII.get(LT_S_I32)); Inverted = true; break;
82 case LT_S_I32: Def->setDesc(TII.get(GE_S_I32)); Inverted = true; break;
83 case LE_S_I32: Def->setDesc(TII.get(GT_S_I32)); Inverted = true; break;
84 case GT_U_I32: Def->setDesc(TII.get(LE_U_I32)); Inverted = true; break;
85 case GE_U_I32: Def->setDesc(TII.get(LT_U_I32)); Inverted = true; break
[all...] |
| WebAssemblyRegisterInfo.cpp | 88 MachineInstr *Def = MF.getRegInfo().getUniqueVRegDef(OtherMOReg);
90 // the CONST_I32 happens to have exactly one def and one use. We
92 if (Def && Def->getOpcode() == WebAssembly::CONST_I32 &&
93 MRI.hasOneNonDBGUse(Def->getOperand(0).getReg())) {
94 MachineOperand &ImmMO = Def->getOperand(1);
|
| /external/llvm/lib/Analysis/ |
| MemDepPrinter.cpp | 29 Def,
67 return InstTypePair(dep.getInst(), Def);
91 = {"Clobber", "Def", "NonFuncLocal", "Unknown"};
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| /external/llvm/lib/CodeGen/ |
| LiveInterval.cpp | 62 VNInfo *createDeadDef(SlotIndex Def, VNInfo::Allocator &VNInfoAllocator) {
63 assert(!Def.isDead() && "Cannot define a value at the dead slot");
65 iterator I = impl().find(Def);
67 VNInfo *VNI = LR->getNextValue(Def, VNInfoAllocator);
68 impl().insertAtEnd(Segment(Def, Def.getDeadSlot(), VNI));
73 if (SlotIndex::isSameInstr(Def, S->start)) {
74 assert(S->valno->def == S->start && "Inconsistent existing value def");
81 Def = std::min(Def, S->start)
[all...] |
| MachineCopyPropagation.cpp | 65 bool eraseIfRedundant(MachineInstr &Copy, unsigned Src, unsigned Def);
69 /// Def -> available copies map.
71 /// Def -> copies map.
73 /// Src -> Def map
123 /// Return true if \p PreviousCopy did copy register \p Src to register \p Def.
125 /// all even though Src and Def are subregisters of the registers used in
130 unsigned Def, const TargetRegisterInfo *TRI) {
134 assert(Def == PreviousDef);
140 return SubIdx == TRI->getSubRegIndex(PreviousDef, Def);
144 /// register \p Src to the register \p Def; This may happen indirectly b
[all...] |
| RenameIndependentSubregs.cpp | 299 // There must be a def (or live-in) before every use. Splitting vregs may
311 SlotIndex Def = VNI.def;
312 MachineBasicBlock &MBB = *Indexes.getMBBFromIndex(Def);
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| /external/llvm/lib/Target/AMDGPU/ |
| SITypeRewriter.cpp | 118 InsertElementInst *Def = cast<InsertElementInst>(Arg);
119 Args.push_back(Def->getOperand(1));
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| /external/llvm/lib/Target/X86/ |
| X86WinAllocaExpander.cpp | 85 MachineInstr *Def = MRI->getUniqueVRegDef(AmountReg);
88 while (Def && Def->isCopy() && Def->getOperand(1).isReg())
89 Def = MRI->getUniqueVRegDef(Def->getOperand(1).getReg());
91 if (!Def ||
92 (Def->getOpcode() != X86::MOV32ri && Def->getOpcode() != X86::MOV64ri) ||
93 !Def->getOperand(1).isImm()
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Analysis/ |
| MemDepPrinter.cpp | 30 Def,
68 return InstTypePair(dep.getInst(), Def);
92 = {"Clobber", "Def", "NonFuncLocal", "Unknown"};
|
| /external/clang/lib/Lex/ |
| PPLexerChange.cpp | 763 MacroInfo *Def = nullptr;
765 Def = DefMD->getInfo();
772 if (Def || !Macro.getOverriddenMacros().empty())
773 addModuleMacro(LeavingMod, II, Def,
|
| PreprocessingRecord.cpp | 322 MacroDefinitionRecord *Def) {
323 MacroDefinitions[Macro] = Def;
379 else if (MacroDefinitionRecord *Def = findMacroDefinition(MI))
380 addPreprocessedEntity(new (*this) MacroExpansion(Def, Range));
423 MacroDefinitionRecord *Def =
425 addPreprocessedEntity(Def);
426 MacroDefinitions[MI] = Def;
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| /external/llvm/lib/Target/AArch64/ |
| AArch64AdvSIMDScalarPass.cpp | 217 MachineRegisterInfo::def_instr_iterator Def =
219 assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!");
220 MachineOperand *MOSrc0 = getSrcFromCopy(&*Def, MRI, SubReg0);
230 MachineRegisterInfo::def_instr_iterator Def =
232 assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!");
233 MachineOperand *MOSrc1 = getSrcFromCopy(&*Def, MRI, SubReg1);
310 MachineRegisterInfo::def_instr_iterator Def =
312 assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!")
[all...] |
