1 /******************************************************************************** 2 Copyright (C) 2016 Marvell International Ltd. 3 4 Marvell BSD License Option 5 6 If you received this File from Marvell, you may opt to use, redistribute and/or 7 modify this File under the following licensing terms. 8 Redistribution and use in source and binary forms, with or without modification, 9 are permitted provided that the following conditions are met: 10 11 * Redistributions of source code must retain the above copyright notice, 12 this list of conditions and the following disclaimer. 13 14 * Redistributions in binary form must reproduce the above copyright 15 notice, this list of conditions and the following disclaimer in the 16 documentation and/or other materials provided with the distribution. 17 18 * Neither the name of Marvell nor the names of its contributors may be 19 used to endorse or promote products derived from this software without 20 specific prior written permission. 21 22 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 23 ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 26 ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 29 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 33 *******************************************************************************/ 34 35 #ifndef __PP2_DXE_H__ 36 #define __PP2_DXE_H__ 37 38 #include <Protocol/Cpu.h> 39 #include <Protocol/DevicePath.h> 40 #include <Protocol/DriverBinding.h> 41 #include <Protocol/Ip4.h> 42 #include <Protocol/Ip6.h> 43 #include <Protocol/MvPhy.h> 44 #include <Protocol/SimpleNetwork.h> 45 46 #include <Library/BaseLib.h> 47 #include <Library/BaseMemoryLib.h> 48 #include <Library/DebugLib.h> 49 #include <Library/IoLib.h> 50 #include <Library/MemoryAllocationLib.h> 51 #include <Library/NetLib.h> 52 #include <Library/PcdLib.h> 53 #include <Library/UefiBootServicesTableLib.h> 54 #include <Library/UefiLib.h> 55 #include <Library/UncachedMemoryAllocationLib.h> 56 57 #include "Mvpp2LibHw.h" 58 59 #define PP2DXE_SIGNATURE SIGNATURE_32('P', 'P', '2', 'D') 60 #define INSTANCE_FROM_SNP(a) CR((a), PP2DXE_CONTEXT, Snp, PP2DXE_SIGNATURE) 61 62 /* OS API */ 63 #define Mvpp2Alloc(v) AllocateZeroPool(v) 64 #define Mvpp2Free(p) FreePool(p) 65 #define Mvpp2Memset(a, v, s) SetMem((a), (s), (v)) 66 #define Mvpp2Mdelay(t) gBS->Stall((t) * 1000) 67 #define Mvpp2Fls(v) 1 68 #define Mvpp2IsBroadcastEtherAddr(da) 1 69 #define Mvpp2IsMulticastEtherAddr(da) 1 70 #define Mvpp2Prefetch(v) do {} while(0); 71 #define Mvpp2Printf(...) do {} while(0); 72 #define Mvpp2SwapVariables(a,b) do { typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0) 73 #define Mvpp2SwapBytes16(x) SwapBytes16((x)) 74 #define Mvpp2Iphdr EFI_IP4_HEADER 75 #define Mvpp2Ipv6hdr EFI_IP6_HEADER 76 #define MVPP2_ALIGN(x, m) ALIGN_VALUE((x), (m)) 77 #define MVPP2_ENOMEM -1 78 #define MVPP2_EINVAL -2 79 #define MVPP2_ERANGE -3 80 #define MVPP2_USEC_PER_SEC 1000000L 81 82 #define DmaAddrT UINTN 83 #define PhysAddrT UINTN 84 85 #define Upper32Bits(n) ((UINT32)(((n) >> 16) >> 16)) 86 #define Lower32Bits(n) ((UINT32)(n)) 87 88 #define ARCH_DMA_MINALIGN 64 89 90 /* Port speeds */ 91 #define MV_PORT_SPEED_10 SPEED_10 92 #define MV_PORT_SPEED_100 SPEED_100 93 #define MV_PORT_SPEED_1000 SPEED_1000 94 #define MV_PORT_SPEED_2500 SPEED_2500 95 #define MV_PORT_SPEED_10000 SPEED_10000 96 97 /* L2 and L3 protocol macros */ 98 #define MV_IPPR_TCP 0 99 #define MV_IPPR_UDP 1 100 #define MV_IPPR_IPIP 2 101 #define MV_IPPR_ICMPV6 3 102 #define MV_IPPR_IGMP 4 103 #define MV_ETH_P_IP 5 104 #define MV_ETH_P_IPV6 6 105 #define MV_ETH_P_PPP_SES 7 106 #define MV_ETH_P_ARP 8 107 #define MV_ETH_P_8021Q 9 108 #define MV_ETH_P_8021AD 10 109 #define MV_ETH_P_EDSA 11 110 #define MV_PPP_IP 12 111 #define MV_PPP_IPV6 13 112 #define MV_ETH_ALEN NET_ETHER_ADDR_LEN 113 114 /* PHY modes */ 115 #define MV_MODE_SGMII PHY_CONNECTION_SGMII 116 #define MV_MODE_RGMII PHY_CONNECTION_RGMII 117 #define MV_MODE_XAUI PHY_CONNECTION_XAUI 118 #define MV_MODE_RXAUI PHY_CONNECTION_RXAUI 119 #define MV_MODE_QSGMII 100 120 #define PP2DXE_MAX_PHY 2 121 122 /* Gop */ 123 /* Sets the field located at the specified in data */ 124 #define U32_SET_FIELD(data, mask, val) ((data) = (((data) & ~(mask)) | (val))) 125 #define MV_RGMII_TX_FIFO_MIN_TH 0x41 126 #define MV_SGMII_TX_FIFO_MIN_TH 0x5 127 #define MV_SGMII2_5_TX_FIFO_MIN_TH 0xB 128 129 /* BM constants */ 130 #define MVPP2_BM_POOLS_NUM 8 131 #define MVPP2_BM_LONG_BUF_NUM 1024 132 #define MVPP2_BM_SHORT_BUF_NUM 2048 133 #define MVPP2_BM_POOL_SIZE_MAX (SIZE_16KB - MVPP2_BM_POOL_PTR_ALIGN/4) 134 #define MVPP2_BM_POOL_PTR_ALIGN 128 135 #define MVPP2_BM_SWF_LONG_POOL(Port) ((Port > 2) ? 2 : Port) 136 #define MVPP2_BM_SWF_SHORT_POOL 3 137 #define MVPP2_BM_POOL 0 138 #define MVPP2_BM_SIZE 32 139 140 /* 141 * BM short pool packet Size 142 * These value assure that for SWF the total number 143 * of bytes allocated for each buffer will be 512 144 */ 145 #define MVPP2_BM_SHORT_PKT_SIZE 512 146 147 /* 148 * Page table entries are set to 1MB, or multiples of 1MB 149 * (not < 1MB). driver uses less bd's so use 1MB bdspace. 150 */ 151 #define BD_SPACE (1 << 20) 152 153 /* Buffer has to be aligned to 1M */ 154 #define MVPP2_BUFFER_ALIGN_SIZE (1 << 20) 155 156 /* RX constants */ 157 #define RX_BUFFER_SIZE (ALIGN_VALUE(MTU + WRAP, ARCH_DMA_MINALIGN)) 158 #define MVPP2_RXQ_OFFSET 0 159 #define BUFF_HDR_OFFS 32 160 #define BM_ALIGN 32 161 #define ETH_HLEN 14 162 163 /* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */ 164 #define WRAP (2 + ETH_HLEN + 4 + 32) 165 #define MTU 1500 166 167 /* 168 * Maximum retries of checking, wheter HW really sent the packet 169 * after it was done is software. 170 */ 171 #define MVPP2_TX_SEND_MAX_POLLING_COUNT 10000 172 173 /* Structures */ 174 typedef struct { 175 /* Physical number of this Tx queue */ 176 UINT8 Id; 177 178 /* Logical number of this Tx queue */ 179 UINT8 LogId; 180 181 /* Number of Tx DMA descriptors in the descriptor ring */ 182 INT32 Size; 183 184 /* Number of currently used Tx DMA descriptor in the descriptor ring */ 185 INT32 count; 186 187 UINT32 DonePktsCoal; 188 189 /* Virtual address of thex Tx DMA descriptors array */ 190 MVPP2_TX_DESC *Descs; 191 192 /* DMA address of the Tx DMA descriptors array */ 193 DmaAddrT DescsPhys; 194 195 /* Index of the last Tx DMA descriptor */ 196 INT32 LastDesc; 197 198 /* Index of the next Tx DMA descriptor to process */ 199 INT32 NextDescToProc; 200 } MVPP2_TX_QUEUE; 201 202 typedef struct { 203 /* RX queue number, in the range 0-31 for physical RXQs */ 204 UINT8 Id; 205 206 /* Num of rx descriptors in the rx descriptor ring */ 207 INT32 Size; 208 209 UINT32 PktsCoal; 210 UINT32 TimeCoal; 211 212 /* Virtual address of the RX DMA descriptors array */ 213 MVPP2_RX_DESC *Descs; 214 215 /* DMA address of the RX DMA descriptors array */ 216 DmaAddrT DescsPhys; 217 218 /* Index of the last RX DMA descriptor */ 219 INT32 LastDesc; 220 221 /* Index of the next RX DMA descriptor to process */ 222 INT32 NextDescToProc; 223 224 /* ID of Port to which physical RXQ is mapped */ 225 INT32 Port; 226 227 /* Port's logic RXQ number to which physical RXQ is mapped */ 228 INT32 LogicRxq; 229 } MVPP2_RX_QUEUE; 230 231 enum Mvpp2BmType { 232 MVPP2_BM_FREE, 233 MVPP2_BM_SWF_LONG, 234 MVPP2_BM_SWF_SHORT 235 }; 236 237 typedef struct { 238 /* Pool number in the range 0-7 */ 239 INT32 Id; 240 enum Mvpp2BmType type; 241 242 /* Buffer Pointers Pool External (BPPE) Size */ 243 INT32 Size; 244 /* Number of buffers for this pool */ 245 INT32 BufNum; 246 /* Pool buffer Size */ 247 INT32 BufSize; 248 /* Packet Size */ 249 INT32 PktSize; 250 251 /* BPPE virtual base address */ 252 UINT32 *VirtAddr; 253 /* BPPE physical base address */ 254 DmaAddrT PhysAddr; 255 256 /* Ports using BM pool */ 257 UINT32 PortMap; 258 } MVPP2_BMS_POOL; 259 260 typedef struct Pp2DxePort PP2DXE_PORT; 261 262 /* Shared Packet Processor resources */ 263 typedef struct { 264 /* Shared registers' base addresses */ 265 UINT64 Base; 266 UINT64 Rfu1Base; 267 UINT64 SmiBase; 268 VOID *LmsBase; 269 270 /* List of pointers to Port structures */ 271 PP2DXE_PORT **PortList; 272 273 /* Aggregated TXQs */ 274 MVPP2_TX_QUEUE *AggrTxqs; 275 276 /* BM pools */ 277 MVPP2_BMS_POOL *BmPools; 278 279 /* PRS shadow table */ 280 MVPP2_PRS_SHADOW *PrsShadow; 281 /* PRS auxiliary table for double vlan entries control */ 282 BOOLEAN *PrsDoubleVlans; 283 284 /* Tclk value */ 285 UINT32 Tclk; 286 } MVPP2_SHARED; 287 288 /* Individual Port structure */ 289 struct Pp2DxePort { 290 UINT8 Id; 291 UINT8 GopIndex; 292 293 INT32 Irq; 294 295 MVPP2_SHARED *Priv; 296 297 /* Per-Port registers' base address */ 298 UINT64 GmacBase; 299 UINT64 XlgBase; 300 301 MVPP2_RX_QUEUE *Rxqs; 302 MVPP2_TX_QUEUE *Txqs; 303 304 INT32 PktSize; 305 306 UINT32 PendingCauseRx; 307 308 /* Flags */ 309 UINTN Flags; 310 311 UINT16 TxRingSize; 312 UINT16 RxRingSize; 313 314 INT32 PhyInterface; 315 BOOLEAN Link; 316 BOOLEAN Duplex; 317 BOOLEAN AlwaysUp; 318 PHY_SPEED Speed; 319 320 MVPP2_BMS_POOL *PoolLong; 321 MVPP2_BMS_POOL *PoolShort; 322 323 UINT8 TxpNum; 324 325 /* Index of first Port's physical RXQ */ 326 UINT8 FirstRxq; 327 }; 328 329 /* Structure for preallocation for buffer */ 330 typedef struct { 331 MVPP2_TX_DESC *TxDescs; 332 MVPP2_TX_DESC *AggrTxDescs; 333 MVPP2_RX_DESC *RxDescs; 334 DmaAddrT RxBuffers; 335 } BUFFER_LOCATION; 336 337 typedef struct { 338 MAC_ADDR_DEVICE_PATH Pp2Mac; 339 EFI_DEVICE_PATH_PROTOCOL End; 340 } PP2_DEVICE_PATH; 341 342 #define QUEUE_DEPTH 64 343 typedef struct { 344 UINT32 Signature; 345 INTN Instance; 346 EFI_HANDLE Controller; 347 EFI_LOCK Lock; 348 EFI_SIMPLE_NETWORK_PROTOCOL Snp; 349 MARVELL_PHY_PROTOCOL *Phy; 350 PHY_DEVICE *PhyDev; 351 PP2DXE_PORT Port; 352 BOOLEAN Initialized; 353 BOOLEAN LateInitialized; 354 VOID *CompletionQueue[QUEUE_DEPTH]; 355 UINTN CompletionQueueHead; 356 UINTN CompletionQueueTail; 357 EFI_EVENT EfiExitBootServicesEvent; 358 PP2_DEVICE_PATH *DevicePath; 359 } PP2DXE_CONTEXT; 360 361 /* Inline helpers */ 362 STATIC 363 inline 364 VOID 365 Mvpp2Write ( 366 IN MVPP2_SHARED *Priv, 367 IN UINT32 Offset, 368 IN UINT32 data 369 ) 370 { 371 ASSERT (Priv->Base != 0); 372 MmioWrite32 (Priv->Base + Offset, data); 373 } 374 375 STATIC 376 inline 377 UINT32 378 Mvpp2Read ( 379 IN MVPP2_SHARED *Priv, 380 IN UINT32 Offset 381 ) 382 { 383 ASSERT (Priv->Base != 0); 384 return MmioRead32 (Priv->Base + Offset); 385 } 386 387 STATIC 388 inline 389 UINT32 390 Mvpp2Rfu1Read ( 391 IN MVPP2_SHARED *Priv, 392 UINT32 Offset 393 ) 394 { 395 ASSERT (Priv->Rfu1Base != 0); 396 return MmioRead32 (Priv->Rfu1Base + Offset); 397 } 398 399 STATIC 400 inline 401 UINT32 402 Mvpp2Rfu1Write ( 403 IN MVPP2_SHARED *Priv, 404 IN UINT32 Offset, 405 IN UINT32 Data 406 ) 407 { 408 ASSERT (Priv->Rfu1Base != 0); 409 return MmioWrite32 (Priv->Rfu1Base + Offset, Data); 410 } 411 412 STATIC 413 inline 414 UINT32 415 Mvpp2SmiRead ( 416 IN MVPP2_SHARED *Priv, 417 IN UINT32 Offset 418 ) 419 { 420 ASSERT (Priv->SmiBase != 0); 421 return MmioRead32 (Priv->SmiBase + Offset); 422 } 423 424 STATIC 425 inline 426 UINT32 427 Mvpp2SmiWrite ( 428 IN MVPP2_SHARED *Priv, 429 IN UINT32 Offset, 430 IN UINT32 Data 431 ) 432 { 433 ASSERT (Priv->SmiBase != 0); 434 return MmioWrite32 (Priv->SmiBase + Offset, Data); 435 } 436 437 STATIC 438 inline 439 VOID 440 Mvpp2GmacWrite ( 441 IN PP2DXE_PORT *Port, 442 IN UINT32 Offset, 443 IN UINT32 Data 444 ) 445 { 446 ASSERT (Port->Priv->Base != 0); 447 MmioWrite32 (Port->Priv->Base + Offset, Data); 448 } 449 450 STATIC 451 inline 452 UINT32 453 Mvpp2GmacRead ( 454 IN PP2DXE_PORT *Port, 455 IN UINT32 Offset 456 ) 457 { 458 ASSERT (Port->Priv->Base != 0); 459 return MmioRead32 (Port->Priv->Base + Offset); 460 } 461 462 STATIC 463 inline 464 VOID 465 MvGop110GmacWrite ( 466 IN PP2DXE_PORT *Port, 467 IN UINT32 Offset, 468 IN UINT32 Data 469 ) 470 { 471 ASSERT (Port->GmacBase != 0); 472 MmioWrite32 (Port->GmacBase + Offset, Data); 473 } 474 475 STATIC 476 inline 477 UINT32 478 MvGop110GmacRead ( 479 IN PP2DXE_PORT *Port, 480 IN UINT32 Offset 481 ) 482 { 483 ASSERT (Port->GmacBase != 0); 484 return MmioRead32 (Port->GmacBase + Offset); 485 } 486 487 STATIC 488 inline 489 VOID 490 Mvpp2XlgWrite ( 491 IN PP2DXE_PORT *Port, 492 IN UINT32 Offset, 493 IN UINT32 Data 494 ) 495 { 496 ASSERT (Port->XlgBase != 0); 497 MmioWrite32 (Port->XlgBase + Offset, Data); 498 } 499 500 STATIC 501 inline 502 UINT32 503 Mvpp2XlgRead ( 504 IN PP2DXE_PORT *Port, 505 IN UINT32 Offset 506 ) 507 { 508 ASSERT (Port->XlgBase != 0); 509 return MmioRead32 (Port->XlgBase + Offset); 510 } 511 512 /* SNP callbacks */ 513 EFI_STATUS 514 EFIAPI 515 Pp2SnpStart ( 516 IN EFI_SIMPLE_NETWORK_PROTOCOL *This 517 ); 518 519 EFI_STATUS 520 EFIAPI 521 Pp2SnpStop ( 522 IN EFI_SIMPLE_NETWORK_PROTOCOL *This 523 ); 524 525 EFI_STATUS 526 EFIAPI 527 Pp2DxeSnpInitialize ( 528 IN EFI_SIMPLE_NETWORK_PROTOCOL *This, 529 IN UINTN ExtraRxBufferSize OPTIONAL, 530 IN UINTN ExtraTxBufferSize OPTIONAL 531 ); 532 533 EFI_STATUS 534 EFIAPI 535 Pp2SnpReset ( 536 IN EFI_SIMPLE_NETWORK_PROTOCOL *This, 537 IN BOOLEAN ExtendedVerification 538 ); 539 540 EFI_STATUS 541 EFIAPI 542 Pp2SnpShutdown ( 543 IN EFI_SIMPLE_NETWORK_PROTOCOL *This 544 ); 545 546 EFI_STATUS 547 EFIAPI 548 Pp2SnpReceiveFilters ( 549 IN EFI_SIMPLE_NETWORK_PROTOCOL *This, 550 IN UINT32 Enable, 551 IN UINT32 Disable, 552 IN BOOLEAN ResetMCastFilter, 553 IN UINTN MCastFilterCnt OPTIONAL, 554 IN EFI_MAC_ADDRESS *MCastFilter OPTIONAL 555 ); 556 557 EFI_STATUS 558 EFIAPI 559 Pp2SnpStationAddress ( 560 IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp, 561 IN BOOLEAN Reset, 562 IN EFI_MAC_ADDRESS *NewMac 563 ); 564 565 EFI_STATUS 566 EFIAPI 567 Pp2SnpNetStat ( 568 IN EFI_SIMPLE_NETWORK_PROTOCOL *This, 569 IN BOOLEAN Reset, 570 IN OUT UINTN *StatisticsSize OPTIONAL, 571 OUT EFI_NETWORK_STATISTICS *StatisticsTable OPTIONAL 572 ); 573 574 EFI_STATUS 575 EFIAPI 576 Pp2SnpIpToMac ( 577 IN EFI_SIMPLE_NETWORK_PROTOCOL *This, 578 IN BOOLEAN IPv6, 579 IN EFI_IP_ADDRESS *IP, 580 OUT EFI_MAC_ADDRESS *MAC 581 ); 582 583 EFI_STATUS 584 EFIAPI 585 Pp2SnpGetStatus ( 586 IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp, 587 OUT UINT32 *InterruptStatus OPTIONAL, 588 OUT VOID **TxBuf OPTIONAL 589 ); 590 591 EFI_STATUS 592 EFIAPI 593 Pp2SnpTransmit ( 594 IN EFI_SIMPLE_NETWORK_PROTOCOL *This, 595 IN UINTN HeaderSize, 596 IN UINTN BufferSize, 597 IN VOID *Buffer, 598 IN EFI_MAC_ADDRESS *SrcAddr OPTIONAL, 599 IN EFI_MAC_ADDRESS *DestAddr OPTIONAL, 600 IN UINT16 *EtherTypePtr OPTIONAL 601 ); 602 603 EFI_STATUS 604 EFIAPI 605 Pp2SnpReceive ( 606 IN EFI_SIMPLE_NETWORK_PROTOCOL *This, 607 OUT UINTN *HeaderSize OPTIONAL, 608 IN OUT UINTN *BufferSize, 609 OUT VOID *Buffer, 610 OUT EFI_MAC_ADDRESS *SrcAddr OPTIONAL, 611 OUT EFI_MAC_ADDRESS *DstAddr OPTIONAL, 612 OUT UINT16 *EtherType OPTIONAL 613 ); 614 #endif 615
