1 #ifndef ADRENO_COMMON_XML 2 #define ADRENO_COMMON_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2016-04-26 17:56:44) 12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) 13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32907 bytes, from 2016-11-26 23:01:08) 14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2016-11-26 23:01:08) 15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 23277 bytes, from 2016-12-24 05:01:47) 16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2016-11-26 23:01:08) 17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110757 bytes, from 2016-12-26 17:51:07) 18 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 100594 bytes, from 2017-01-20 23:03:30) 19 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00) 20 21 Copyright (C) 2013-2016 by the following authors: 22 - Rob Clark <robdclark (at) gmail.com> (robclark) 23 - Ilia Mirkin <imirkin (at) alum.mit.edu> (imirkin) 24 25 Permission is hereby granted, free of charge, to any person obtaining 26 a copy of this software and associated documentation files (the 27 "Software"), to deal in the Software without restriction, including 28 without limitation the rights to use, copy, modify, merge, publish, 29 distribute, sublicense, and/or sell copies of the Software, and to 30 permit persons to whom the Software is furnished to do so, subject to 31 the following conditions: 32 33 The above copyright notice and this permission notice (including the 34 next paragraph) shall be included in all copies or substantial 35 portions of the Software. 36 37 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 38 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 39 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 40 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 41 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 42 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 43 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 44 */ 45 46 47 enum adreno_pa_su_sc_draw { 48 PC_DRAW_POINTS = 0, 49 PC_DRAW_LINES = 1, 50 PC_DRAW_TRIANGLES = 2, 51 }; 52 53 enum adreno_compare_func { 54 FUNC_NEVER = 0, 55 FUNC_LESS = 1, 56 FUNC_EQUAL = 2, 57 FUNC_LEQUAL = 3, 58 FUNC_GREATER = 4, 59 FUNC_NOTEQUAL = 5, 60 FUNC_GEQUAL = 6, 61 FUNC_ALWAYS = 7, 62 }; 63 64 enum adreno_stencil_op { 65 STENCIL_KEEP = 0, 66 STENCIL_ZERO = 1, 67 STENCIL_REPLACE = 2, 68 STENCIL_INCR_CLAMP = 3, 69 STENCIL_DECR_CLAMP = 4, 70 STENCIL_INVERT = 5, 71 STENCIL_INCR_WRAP = 6, 72 STENCIL_DECR_WRAP = 7, 73 }; 74 75 enum adreno_rb_blend_factor { 76 FACTOR_ZERO = 0, 77 FACTOR_ONE = 1, 78 FACTOR_SRC_COLOR = 4, 79 FACTOR_ONE_MINUS_SRC_COLOR = 5, 80 FACTOR_SRC_ALPHA = 6, 81 FACTOR_ONE_MINUS_SRC_ALPHA = 7, 82 FACTOR_DST_COLOR = 8, 83 FACTOR_ONE_MINUS_DST_COLOR = 9, 84 FACTOR_DST_ALPHA = 10, 85 FACTOR_ONE_MINUS_DST_ALPHA = 11, 86 FACTOR_CONSTANT_COLOR = 12, 87 FACTOR_ONE_MINUS_CONSTANT_COLOR = 13, 88 FACTOR_CONSTANT_ALPHA = 14, 89 FACTOR_ONE_MINUS_CONSTANT_ALPHA = 15, 90 FACTOR_SRC_ALPHA_SATURATE = 16, 91 FACTOR_SRC1_COLOR = 20, 92 FACTOR_ONE_MINUS_SRC1_COLOR = 21, 93 FACTOR_SRC1_ALPHA = 22, 94 FACTOR_ONE_MINUS_SRC1_ALPHA = 23, 95 }; 96 97 enum adreno_rb_surface_endian { 98 ENDIAN_NONE = 0, 99 ENDIAN_8IN16 = 1, 100 ENDIAN_8IN32 = 2, 101 ENDIAN_16IN32 = 3, 102 ENDIAN_8IN64 = 4, 103 ENDIAN_8IN128 = 5, 104 }; 105 106 enum adreno_rb_dither_mode { 107 DITHER_DISABLE = 0, 108 DITHER_ALWAYS = 1, 109 DITHER_IF_ALPHA_OFF = 2, 110 }; 111 112 enum adreno_rb_depth_format { 113 DEPTHX_16 = 0, 114 DEPTHX_24_8 = 1, 115 DEPTHX_32 = 2, 116 }; 117 118 enum adreno_rb_copy_control_mode { 119 RB_COPY_RESOLVE = 1, 120 RB_COPY_CLEAR = 2, 121 RB_COPY_DEPTH_STENCIL = 5, 122 }; 123 124 enum a3xx_rop_code { 125 ROP_CLEAR = 0, 126 ROP_NOR = 1, 127 ROP_AND_INVERTED = 2, 128 ROP_COPY_INVERTED = 3, 129 ROP_AND_REVERSE = 4, 130 ROP_INVERT = 5, 131 ROP_XOR = 6, 132 ROP_NAND = 7, 133 ROP_AND = 8, 134 ROP_EQUIV = 9, 135 ROP_NOOP = 10, 136 ROP_OR_INVERTED = 11, 137 ROP_COPY = 12, 138 ROP_OR_REVERSE = 13, 139 ROP_OR = 14, 140 ROP_SET = 15, 141 }; 142 143 enum a3xx_render_mode { 144 RB_RENDERING_PASS = 0, 145 RB_TILING_PASS = 1, 146 RB_RESOLVE_PASS = 2, 147 RB_COMPUTE_PASS = 3, 148 }; 149 150 enum a3xx_msaa_samples { 151 MSAA_ONE = 0, 152 MSAA_TWO = 1, 153 MSAA_FOUR = 2, 154 }; 155 156 enum a3xx_threadmode { 157 MULTI = 0, 158 SINGLE = 1, 159 }; 160 161 enum a3xx_instrbuffermode { 162 CACHE = 0, 163 BUFFER = 1, 164 }; 165 166 enum a3xx_threadsize { 167 TWO_QUADS = 0, 168 FOUR_QUADS = 1, 169 }; 170 171 enum a3xx_color_swap { 172 WZYX = 0, 173 WXYZ = 1, 174 ZYXW = 2, 175 XYZW = 3, 176 }; 177 178 enum a3xx_rb_blend_opcode { 179 BLEND_DST_PLUS_SRC = 0, 180 BLEND_SRC_MINUS_DST = 1, 181 BLEND_DST_MINUS_SRC = 2, 182 BLEND_MIN_DST_SRC = 3, 183 BLEND_MAX_DST_SRC = 4, 184 }; 185 186 #define REG_AXXX_CP_RB_BASE 0x000001c0 187 188 #define REG_AXXX_CP_RB_CNTL 0x000001c1 189 #define AXXX_CP_RB_CNTL_BUFSZ__MASK 0x0000003f 190 #define AXXX_CP_RB_CNTL_BUFSZ__SHIFT 0 191 static inline uint32_t AXXX_CP_RB_CNTL_BUFSZ(uint32_t val) 192 { 193 return ((val) << AXXX_CP_RB_CNTL_BUFSZ__SHIFT) & AXXX_CP_RB_CNTL_BUFSZ__MASK; 194 } 195 #define AXXX_CP_RB_CNTL_BLKSZ__MASK 0x00003f00 196 #define AXXX_CP_RB_CNTL_BLKSZ__SHIFT 8 197 static inline uint32_t AXXX_CP_RB_CNTL_BLKSZ(uint32_t val) 198 { 199 return ((val) << AXXX_CP_RB_CNTL_BLKSZ__SHIFT) & AXXX_CP_RB_CNTL_BLKSZ__MASK; 200 } 201 #define AXXX_CP_RB_CNTL_BUF_SWAP__MASK 0x00030000 202 #define AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT 16 203 static inline uint32_t AXXX_CP_RB_CNTL_BUF_SWAP(uint32_t val) 204 { 205 return ((val) << AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT) & AXXX_CP_RB_CNTL_BUF_SWAP__MASK; 206 } 207 #define AXXX_CP_RB_CNTL_POLL_EN 0x00100000 208 #define AXXX_CP_RB_CNTL_NO_UPDATE 0x08000000 209 #define AXXX_CP_RB_CNTL_RPTR_WR_EN 0x80000000 210 211 #define REG_AXXX_CP_RB_RPTR_ADDR 0x000001c3 212 #define AXXX_CP_RB_RPTR_ADDR_SWAP__MASK 0x00000003 213 #define AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT 0 214 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_SWAP(uint32_t val) 215 { 216 return ((val) << AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT) & AXXX_CP_RB_RPTR_ADDR_SWAP__MASK; 217 } 218 #define AXXX_CP_RB_RPTR_ADDR_ADDR__MASK 0xfffffffc 219 #define AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT 2 220 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val) 221 { 222 assert(!(val & 0x3)); 223 return ((val >> 2) << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK; 224 } 225 226 #define REG_AXXX_CP_RB_RPTR 0x000001c4 227 228 #define REG_AXXX_CP_RB_WPTR 0x000001c5 229 230 #define REG_AXXX_CP_RB_WPTR_DELAY 0x000001c6 231 232 #define REG_AXXX_CP_RB_RPTR_WR 0x000001c7 233 234 #define REG_AXXX_CP_RB_WPTR_BASE 0x000001c8 235 236 #define REG_AXXX_CP_QUEUE_THRESHOLDS 0x000001d5 237 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK 0x0000000f 238 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT 0 239 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(uint32_t val) 240 { 241 return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK; 242 } 243 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK 0x00000f00 244 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT 8 245 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(uint32_t val) 246 { 247 return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK; 248 } 249 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK 0x000f0000 250 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT 16 251 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(uint32_t val) 252 { 253 return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK; 254 } 255 256 #define REG_AXXX_CP_MEQ_THRESHOLDS 0x000001d6 257 #define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK 0x001f0000 258 #define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT 16 259 static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_MEQ_END(uint32_t val) 260 { 261 return ((val) << AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK; 262 } 263 #define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK 0x1f000000 264 #define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT 24 265 static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_ROQ_END(uint32_t val) 266 { 267 return ((val) << AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK; 268 } 269 270 #define REG_AXXX_CP_CSQ_AVAIL 0x000001d7 271 #define AXXX_CP_CSQ_AVAIL_RING__MASK 0x0000007f 272 #define AXXX_CP_CSQ_AVAIL_RING__SHIFT 0 273 static inline uint32_t AXXX_CP_CSQ_AVAIL_RING(uint32_t val) 274 { 275 return ((val) << AXXX_CP_CSQ_AVAIL_RING__SHIFT) & AXXX_CP_CSQ_AVAIL_RING__MASK; 276 } 277 #define AXXX_CP_CSQ_AVAIL_IB1__MASK 0x00007f00 278 #define AXXX_CP_CSQ_AVAIL_IB1__SHIFT 8 279 static inline uint32_t AXXX_CP_CSQ_AVAIL_IB1(uint32_t val) 280 { 281 return ((val) << AXXX_CP_CSQ_AVAIL_IB1__SHIFT) & AXXX_CP_CSQ_AVAIL_IB1__MASK; 282 } 283 #define AXXX_CP_CSQ_AVAIL_IB2__MASK 0x007f0000 284 #define AXXX_CP_CSQ_AVAIL_IB2__SHIFT 16 285 static inline uint32_t AXXX_CP_CSQ_AVAIL_IB2(uint32_t val) 286 { 287 return ((val) << AXXX_CP_CSQ_AVAIL_IB2__SHIFT) & AXXX_CP_CSQ_AVAIL_IB2__MASK; 288 } 289 290 #define REG_AXXX_CP_STQ_AVAIL 0x000001d8 291 #define AXXX_CP_STQ_AVAIL_ST__MASK 0x0000007f 292 #define AXXX_CP_STQ_AVAIL_ST__SHIFT 0 293 static inline uint32_t AXXX_CP_STQ_AVAIL_ST(uint32_t val) 294 { 295 return ((val) << AXXX_CP_STQ_AVAIL_ST__SHIFT) & AXXX_CP_STQ_AVAIL_ST__MASK; 296 } 297 298 #define REG_AXXX_CP_MEQ_AVAIL 0x000001d9 299 #define AXXX_CP_MEQ_AVAIL_MEQ__MASK 0x0000001f 300 #define AXXX_CP_MEQ_AVAIL_MEQ__SHIFT 0 301 static inline uint32_t AXXX_CP_MEQ_AVAIL_MEQ(uint32_t val) 302 { 303 return ((val) << AXXX_CP_MEQ_AVAIL_MEQ__SHIFT) & AXXX_CP_MEQ_AVAIL_MEQ__MASK; 304 } 305 306 #define REG_AXXX_SCRATCH_UMSK 0x000001dc 307 #define AXXX_SCRATCH_UMSK_UMSK__MASK 0x000000ff 308 #define AXXX_SCRATCH_UMSK_UMSK__SHIFT 0 309 static inline uint32_t AXXX_SCRATCH_UMSK_UMSK(uint32_t val) 310 { 311 return ((val) << AXXX_SCRATCH_UMSK_UMSK__SHIFT) & AXXX_SCRATCH_UMSK_UMSK__MASK; 312 } 313 #define AXXX_SCRATCH_UMSK_SWAP__MASK 0x00030000 314 #define AXXX_SCRATCH_UMSK_SWAP__SHIFT 16 315 static inline uint32_t AXXX_SCRATCH_UMSK_SWAP(uint32_t val) 316 { 317 return ((val) << AXXX_SCRATCH_UMSK_SWAP__SHIFT) & AXXX_SCRATCH_UMSK_SWAP__MASK; 318 } 319 320 #define REG_AXXX_SCRATCH_ADDR 0x000001dd 321 322 #define REG_AXXX_CP_ME_RDADDR 0x000001ea 323 324 #define REG_AXXX_CP_STATE_DEBUG_INDEX 0x000001ec 325 326 #define REG_AXXX_CP_STATE_DEBUG_DATA 0x000001ed 327 328 #define REG_AXXX_CP_INT_CNTL 0x000001f2 329 330 #define REG_AXXX_CP_INT_STATUS 0x000001f3 331 332 #define REG_AXXX_CP_INT_ACK 0x000001f4 333 334 #define REG_AXXX_CP_ME_CNTL 0x000001f6 335 #define AXXX_CP_ME_CNTL_BUSY 0x20000000 336 #define AXXX_CP_ME_CNTL_HALT 0x10000000 337 338 #define REG_AXXX_CP_ME_STATUS 0x000001f7 339 340 #define REG_AXXX_CP_ME_RAM_WADDR 0x000001f8 341 342 #define REG_AXXX_CP_ME_RAM_RADDR 0x000001f9 343 344 #define REG_AXXX_CP_ME_RAM_DATA 0x000001fa 345 346 #define REG_AXXX_CP_DEBUG 0x000001fc 347 #define AXXX_CP_DEBUG_PREDICATE_DISABLE 0x00800000 348 #define AXXX_CP_DEBUG_PROG_END_PTR_ENABLE 0x01000000 349 #define AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE 0x02000000 350 #define AXXX_CP_DEBUG_PREFETCH_PASS_NOPS 0x04000000 351 #define AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE 0x08000000 352 #define AXXX_CP_DEBUG_PREFETCH_MATCH_DISABLE 0x10000000 353 #define AXXX_CP_DEBUG_SIMPLE_ME_FLOW_CONTROL 0x40000000 354 #define AXXX_CP_DEBUG_MIU_WRITE_PACK_DISABLE 0x80000000 355 356 #define REG_AXXX_CP_CSQ_RB_STAT 0x000001fd 357 #define AXXX_CP_CSQ_RB_STAT_RPTR__MASK 0x0000007f 358 #define AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT 0 359 static inline uint32_t AXXX_CP_CSQ_RB_STAT_RPTR(uint32_t val) 360 { 361 return ((val) << AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_RPTR__MASK; 362 } 363 #define AXXX_CP_CSQ_RB_STAT_WPTR__MASK 0x007f0000 364 #define AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT 16 365 static inline uint32_t AXXX_CP_CSQ_RB_STAT_WPTR(uint32_t val) 366 { 367 return ((val) << AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_WPTR__MASK; 368 } 369 370 #define REG_AXXX_CP_CSQ_IB1_STAT 0x000001fe 371 #define AXXX_CP_CSQ_IB1_STAT_RPTR__MASK 0x0000007f 372 #define AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT 0 373 static inline uint32_t AXXX_CP_CSQ_IB1_STAT_RPTR(uint32_t val) 374 { 375 return ((val) << AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_RPTR__MASK; 376 } 377 #define AXXX_CP_CSQ_IB1_STAT_WPTR__MASK 0x007f0000 378 #define AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT 16 379 static inline uint32_t AXXX_CP_CSQ_IB1_STAT_WPTR(uint32_t val) 380 { 381 return ((val) << AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_WPTR__MASK; 382 } 383 384 #define REG_AXXX_CP_CSQ_IB2_STAT 0x000001ff 385 #define AXXX_CP_CSQ_IB2_STAT_RPTR__MASK 0x0000007f 386 #define AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT 0 387 static inline uint32_t AXXX_CP_CSQ_IB2_STAT_RPTR(uint32_t val) 388 { 389 return ((val) << AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_RPTR__MASK; 390 } 391 #define AXXX_CP_CSQ_IB2_STAT_WPTR__MASK 0x007f0000 392 #define AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT 16 393 static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val) 394 { 395 return ((val) << AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_WPTR__MASK; 396 } 397 398 #define REG_AXXX_CP_NON_PREFETCH_CNTRS 0x00000440 399 400 #define REG_AXXX_CP_STQ_ST_STAT 0x00000443 401 402 #define REG_AXXX_CP_ST_BASE 0x0000044d 403 404 #define REG_AXXX_CP_ST_BUFSZ 0x0000044e 405 406 #define REG_AXXX_CP_MEQ_STAT 0x0000044f 407 408 #define REG_AXXX_CP_MIU_TAG_STAT 0x00000452 409 410 #define REG_AXXX_CP_BIN_MASK_LO 0x00000454 411 412 #define REG_AXXX_CP_BIN_MASK_HI 0x00000455 413 414 #define REG_AXXX_CP_BIN_SELECT_LO 0x00000456 415 416 #define REG_AXXX_CP_BIN_SELECT_HI 0x00000457 417 418 #define REG_AXXX_CP_IB1_BASE 0x00000458 419 420 #define REG_AXXX_CP_IB1_BUFSZ 0x00000459 421 422 #define REG_AXXX_CP_IB2_BASE 0x0000045a 423 424 #define REG_AXXX_CP_IB2_BUFSZ 0x0000045b 425 426 #define REG_AXXX_CP_STAT 0x0000047f 427 428 #define REG_AXXX_CP_SCRATCH_REG0 0x00000578 429 430 #define REG_AXXX_CP_SCRATCH_REG1 0x00000579 431 432 #define REG_AXXX_CP_SCRATCH_REG2 0x0000057a 433 434 #define REG_AXXX_CP_SCRATCH_REG3 0x0000057b 435 436 #define REG_AXXX_CP_SCRATCH_REG4 0x0000057c 437 438 #define REG_AXXX_CP_SCRATCH_REG5 0x0000057d 439 440 #define REG_AXXX_CP_SCRATCH_REG6 0x0000057e 441 442 #define REG_AXXX_CP_SCRATCH_REG7 0x0000057f 443 444 #define REG_AXXX_CP_ME_VS_EVENT_SRC 0x00000600 445 446 #define REG_AXXX_CP_ME_VS_EVENT_ADDR 0x00000601 447 448 #define REG_AXXX_CP_ME_VS_EVENT_DATA 0x00000602 449 450 #define REG_AXXX_CP_ME_VS_EVENT_ADDR_SWM 0x00000603 451 452 #define REG_AXXX_CP_ME_VS_EVENT_DATA_SWM 0x00000604 453 454 #define REG_AXXX_CP_ME_PS_EVENT_SRC 0x00000605 455 456 #define REG_AXXX_CP_ME_PS_EVENT_ADDR 0x00000606 457 458 #define REG_AXXX_CP_ME_PS_EVENT_DATA 0x00000607 459 460 #define REG_AXXX_CP_ME_PS_EVENT_ADDR_SWM 0x00000608 461 462 #define REG_AXXX_CP_ME_PS_EVENT_DATA_SWM 0x00000609 463 464 #define REG_AXXX_CP_ME_CF_EVENT_SRC 0x0000060a 465 466 #define REG_AXXX_CP_ME_CF_EVENT_ADDR 0x0000060b 467 468 #define REG_AXXX_CP_ME_CF_EVENT_DATA 0x0000060c 469 470 #define REG_AXXX_CP_ME_NRT_ADDR 0x0000060d 471 472 #define REG_AXXX_CP_ME_NRT_DATA 0x0000060e 473 474 #define REG_AXXX_CP_ME_VS_FETCH_DONE_SRC 0x00000612 475 476 #define REG_AXXX_CP_ME_VS_FETCH_DONE_ADDR 0x00000613 477 478 #define REG_AXXX_CP_ME_VS_FETCH_DONE_DATA 0x00000614 479 480 481 #endif /* ADRENO_COMMON_XML */ 482
