1 /* tic54x.h -- Header file for TI TMS320C54X opcode table 2 Copyright (C) 1999-2016 Free Software Foundation, Inc. 3 Written by Timothy Wall (twall (at) cygnus.com) 4 5 This file is part of GDB, GAS, and the GNU binutils. 6 7 GDB, GAS, and the GNU binutils are free software; you can redistribute 8 them and/or modify them under the terms of the GNU General Public 9 License as published by the Free Software Foundation; either version 3, 10 or (at your option) any later version. 11 12 GDB, GAS, and the GNU binutils are distributed in the hope that they 13 will be useful, but WITHOUT ANY WARRANTY; without even the implied 14 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 15 the GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this file; see the file COPYING3. If not, write to the Free 19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 20 02110-1301, USA. */ 21 22 #ifndef _opcode_tic54x_h_ 23 #define _opcode_tic54x_h_ 24 25 typedef struct _symbol 26 { 27 const char *name; 28 unsigned short value; 29 } tic54x_symbol; 30 31 enum optype { 32 OPT = 0x8000, 33 OP_None = 0x0, 34 35 OP_Xmem, /* AR3 or AR4, indirect */ 36 OP_Ymem, /* AR3 or AR4, indirect */ 37 OP_pmad, /* PROG mem, direct */ 38 OP_dmad, /* DATA mem, direct */ 39 OP_Smem, 40 OP_Lmem, /* 32-bit single-addressed (direct/indirect) */ 41 OP_MMR, 42 OP_PA, 43 OP_Sind, 44 OP_xpmad, 45 OP_xpmad_ms7, 46 OP_MMRX, 47 OP_MMRY, 48 49 OP_SRC1, /* src accumulator in bit 8 */ 50 OP_SRC, /* src accumulator in bit 9 */ 51 OP_RND, /* rounded result dst accumulator, opposite of bit 8 */ 52 OP_DST, /* dst accumulator in bit 8 */ 53 OP_ARX, /* arX in bits 0-3 */ 54 OP_SHIFT, /* -16 to 15 (SHIFT), bits 0-4 */ 55 OP_SHFT, /* 0 to 15 (SHIFT1 in summary), bits 0-3 */ 56 OP_B, /* ACC B only */ 57 OP_A, /* ACC A only */ 58 59 OP_lk, /* 16-bit immediate, '#' optional */ 60 OP_TS, 61 OP_k8, /* -128 <= k <= 128 */ 62 OP_16, /* literal "16" */ 63 OP_BITC, /* 0 to 16 */ 64 OP_CC, /* condition code */ 65 OP_CC2, /* 4-bit condition code */ 66 OP_CC3, /* 2-bit condition code */ 67 OP_123, /* 1, 2, or 3 */ 68 OP_031, /* 0-31, numeric */ 69 OP_k5, /* 0 to 31 */ 70 OP_k8u, /* 0 to 255 */ 71 OP_ASM, /* "ASM" */ 72 OP_T, /* "T" */ 73 OP_DP, /* "DP" */ 74 OP_ARP, /* "ARP" */ 75 OP_k3, /* 0-7 */ 76 OP_lku, /* 0 to 65535 */ 77 OP_N, /* 0/1 or ST0/ST1 */ 78 OP_SBIT, /* status bit or 0-15 */ 79 OP_12, /* one or two */ 80 OP_k9, /* 9 bits of data page (DP) address */ 81 OP_TRN, /* "TRN" */ 82 83 }; 84 85 typedef struct _template 86 { 87 /* The opcode mnemonic */ 88 const char *name; 89 unsigned int words; /* insn size in words */ 90 int minops, maxops; /* min/max operand count */ 91 /* The significant bits in the opcode. Other bits are zero. 92 Instructions with more than 16 bits of opcode store the rest in the upper 93 16 bits. 94 */ 95 unsigned short opcode; 96 #define INDIRECT(OP) ((OP)&0x80) 97 #define MOD(OP) (((OP)>>3)&0xF) 98 #define ARF(OP) ((OP)&0x7) 99 #define IS_LKADDR(OP) (INDIRECT(OP) && MOD(OP)>=12) 100 #define SRC(OP) ((OP)&0x200) 101 #define DST(OP) ((OP)&0x100) 102 #define SRC1(OP) ((OP)&0x100) 103 #define SHIFT(OP) (((OP)&0x10)?(((OP)&0x1F)-32):((OP)&0x1F)) 104 #define SHFT(OP) ((OP)&0xF) 105 #define ARX(OP) ((OP)&0x7) 106 #define XMEM(OP) (((OP)&0x00F0)>>4) 107 #define YMEM(OP) ((OP)&0x000F) 108 #define XMOD(C) (((C)&0xC)>>2) 109 #define XARX(C) (((C)&0x3)+2) 110 #define CC3(OP) (((OP)>>8)&0x3) 111 #define SBIT(OP) ((OP)&0xF) 112 #define MMR(OP) ((OP)&0x7F) 113 #define MMRX(OP) ((((OP)>>4)&0xF)+16) 114 #define MMRY(OP) (((OP)&0xF)+16) 115 116 #define OPTYPE(X) ((X)&~OPT) 117 118 /* Ones in this mask indicate which bits must match the opcode field. 119 Zeroes indicate don't care bits (operands and/or opcode options) */ 120 unsigned short mask; 121 122 /* An array of operand codes (at most 4 operands) */ 123 #define MAX_OPERANDS 4 124 enum optype operand_types[MAX_OPERANDS]; 125 126 /* Special purpose flags (e.g. branch type, parallel, delay, etc) 127 */ 128 unsigned short flags; 129 #define B_NEXT 0 /* normal execution, next insn is next address */ 130 #define B_BRANCH 1 /* next insn is in opcode */ 131 #define B_RET 2 /* next insn is on stack */ 132 #define B_BACC 3 /* next insn is in acc */ 133 #define B_REPEAT 4 /* next insn repeats */ 134 #define FL_BMASK 0x07 135 136 #define FL_DELAY 0x10 /* instruction uses delay slots */ 137 #define FL_EXT 0x20 /* instruction takes two words */ 138 #define FL_FAR 0x40 /* far mode addressing */ 139 #define FL_LP 0x80 /* LP-only instruction */ 140 #define FL_NR 0x100 /* no repeat allowed */ 141 #define FL_SMR 0x200 /* Smem read (for flagging write-only *+ARx */ 142 143 #define FL_PAR 0x400 /* Parallel instruction. */ 144 145 unsigned short opcode2, mask2; /* some insns have an extended opcode */ 146 147 const char* parname; 148 enum optype paroperand_types[MAX_OPERANDS]; 149 150 } insn_template; 151 152 extern const insn_template tic54x_unknown_opcode; 153 extern const insn_template tic54x_optab[]; 154 extern const insn_template tic54x_paroptab[]; 155 extern const tic54x_symbol mmregs[], regs[]; 156 extern const tic54x_symbol condition_codes[], cc2_codes[], status_bits[]; 157 extern const tic54x_symbol cc3_codes[]; 158 extern const char *misc_symbols[]; 159 struct disassemble_info; 160 extern const insn_template* tic54x_get_insn (struct disassemble_info *, 161 bfd_vma, unsigned short, int *); 162 163 #endif /* _opcode_tic54x_h_ */ 164
