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      1 #ifndef GEN_MI_XML
      2 #define GEN_MI_XML
      3 
      4 /* Autogenerated file, DO NOT EDIT manually!
      5 
      6 This file was generated by the rules-ng-ng headergen tool in this git repository:
      7 https://github.com/olvaffe/envytools/
      8 git clone https://github.com/olvaffe/envytools.git
      9 
     10 Copyright (C) 2014-2015 by the following authors:
     11 - Chia-I Wu <olvaffe (at) gmail.com> (olv)
     12 
     13 Permission is hereby granted, free of charge, to any person obtaining
     14 a copy of this software and associated documentation files (the
     15 "Software"), to deal in the Software without restriction, including
     16 without limitation the rights to use, copy, modify, merge, publish,
     17 distribute, sublicense, and/or sell copies of the Software, and to
     18 permit persons to whom the Software is furnished to do so, subject to
     19 the following conditions:
     20 
     21 The above copyright notice and this permission notice (including the
     22 next paragraph) shall be included in all copies or substantial
     23 portions of the Software.
     24 
     25 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
     26 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
     27 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
     28 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
     29 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
     30 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
     31 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
     32 */
     33 
     34 
     35 enum gen_mi_alu_opcode {
     36     GEN75_MI_ALU_NOOP					      = 0x0,
     37     GEN75_MI_ALU_LOAD					      = 0x80,
     38     GEN75_MI_ALU_LOADINV				      = 0x480,
     39     GEN75_MI_ALU_LOAD0					      = 0x81,
     40     GEN75_MI_ALU_LOAD1					      = 0x481,
     41     GEN75_MI_ALU_ADD					      = 0x100,
     42     GEN75_MI_ALU_SUB					      = 0x101,
     43     GEN75_MI_ALU_AND					      = 0x102,
     44     GEN75_MI_ALU_OR					      = 0x103,
     45     GEN75_MI_ALU_XOR					      = 0x104,
     46     GEN75_MI_ALU_STORE					      = 0x180,
     47     GEN75_MI_ALU_STOREINV				      = 0x580,
     48 };
     49 
     50 enum gen_mi_alu_operand {
     51     GEN75_MI_ALU_R0					      = 0x0,
     52     GEN75_MI_ALU_R1					      = 0x1,
     53     GEN75_MI_ALU_R2					      = 0x2,
     54     GEN75_MI_ALU_R3					      = 0x3,
     55     GEN75_MI_ALU_R4					      = 0x4,
     56     GEN75_MI_ALU_R5					      = 0x5,
     57     GEN75_MI_ALU_R6					      = 0x6,
     58     GEN75_MI_ALU_R7					      = 0x7,
     59     GEN75_MI_ALU_R8					      = 0x8,
     60     GEN75_MI_ALU_R9					      = 0x9,
     61     GEN75_MI_ALU_R10					      = 0xa,
     62     GEN75_MI_ALU_R11					      = 0xb,
     63     GEN75_MI_ALU_R12					      = 0xc,
     64     GEN75_MI_ALU_R13					      = 0xd,
     65     GEN75_MI_ALU_R14					      = 0xe,
     66     GEN75_MI_ALU_R15					      = 0xf,
     67     GEN75_MI_ALU_SRCA					      = 0x20,
     68     GEN75_MI_ALU_SRCB					      = 0x21,
     69     GEN75_MI_ALU_ACCU					      = 0x31,
     70     GEN75_MI_ALU_ZF					      = 0x32,
     71     GEN75_MI_ALU_CF					      = 0x33,
     72 };
     73 
     74 #define GEN6_MI_TYPE__MASK					0xe0000000
     75 #define GEN6_MI_TYPE__SHIFT					29
     76 #define GEN6_MI_TYPE_MI						(0x0 << 29)
     77 #define GEN6_MI_OPCODE__MASK					0x1f800000
     78 #define GEN6_MI_OPCODE__SHIFT					23
     79 #define GEN6_MI_OPCODE_MI_NOOP					(0x0 << 23)
     80 #define GEN75_MI_OPCODE_MI_SET_PREDICATE			(0x1 << 23)
     81 #define GEN75_MI_OPCODE_MI_RS_CONTROL				(0x6 << 23)
     82 #define GEN75_MI_OPCODE_MI_URB_ATOMIC_ALLOC			(0x9 << 23)
     83 #define GEN6_MI_OPCODE_MI_BATCH_BUFFER_END			(0xa << 23)
     84 #define GEN7_MI_OPCODE_MI_PREDICATE				(0xc << 23)
     85 #define GEN7_MI_OPCODE_MI_URB_CLEAR				(0x19 << 23)
     86 #define GEN75_MI_OPCODE_MI_MATH					(0x1a << 23)
     87 #define GEN8_MI_OPCODE_MI_SEMAPHORE_SIGNAL			(0x1b << 23)
     88 #define GEN8_MI_OPCODE_MI_SEMAPHORE_WAIT			(0x1c << 23)
     89 #define GEN6_MI_OPCODE_MI_STORE_DATA_IMM			(0x20 << 23)
     90 #define GEN6_MI_OPCODE_MI_LOAD_REGISTER_IMM			(0x22 << 23)
     91 #define GEN6_MI_OPCODE_MI_STORE_REGISTER_MEM			(0x24 << 23)
     92 #define GEN6_MI_OPCODE_MI_FLUSH_DW				(0x26 << 23)
     93 #define GEN6_MI_OPCODE_MI_REPORT_PERF_COUNT			(0x28 << 23)
     94 #define GEN7_MI_OPCODE_MI_LOAD_REGISTER_MEM			(0x29 << 23)
     95 #define GEN75_MI_OPCODE_MI_LOAD_REGISTER_REG			(0x2a << 23)
     96 #define GEN75_MI_OPCODE_MI_RS_STORE_DATA_IMM			(0x2b << 23)
     97 #define GEN75_MI_OPCODE_MI_LOAD_URB_MEM				(0x2c << 23)
     98 #define GEN75_MI_OPCODE_MI_STORE_URB_MEM			(0x2d << 23)
     99 #define GEN8_MI_OPCODE_MI_COPY_MEM_MEM				(0x2e << 23)
    100 #define GEN8_MI_OPCODE_MI_ATOMIC				(0x2f << 23)
    101 #define GEN6_MI_OPCODE_MI_BATCH_BUFFER_START			(0x31 << 23)
    102 #define GEN6_MI_LENGTH__MASK					0x0000003f
    103 #define GEN6_MI_LENGTH__SHIFT					0
    104 #define GEN6_MI_NOOP__SIZE					1
    105 #define GEN6_MI_NOOP_DW0_WRITE_NOPID				(0x1 << 22)
    106 #define GEN6_MI_NOOP_DW0_VALUE__MASK				0x003fffff
    107 #define GEN6_MI_NOOP_DW0_VALUE__SHIFT				0
    108 
    109 #define GEN75_MI_SET_PREDICATE__SIZE				1
    110 #define GEN75_MI_SET_PREDICATE_DW0_PREDICATE__MASK		0x00000003
    111 #define GEN75_MI_SET_PREDICATE_DW0_PREDICATE__SHIFT		0
    112 #define GEN75_MI_SET_PREDICATE_DW0_PREDICATE_ALWAYS		0x0
    113 #define GEN75_MI_SET_PREDICATE_DW0_PREDICATE_ON_CLEAR		0x1
    114 #define GEN75_MI_SET_PREDICATE_DW0_PREDICATE_ON_SET		0x2
    115 #define GEN75_MI_SET_PREDICATE_DW0_PREDICATE_DISABLE		0x3
    116 
    117 #define GEN75_MI_RS_CONTROL__SIZE				1
    118 #define GEN75_MI_RS_CONTROL_DW0_ENABLE				(0x1 << 0)
    119 
    120 #define GEN75_MI_URB_ATOMIC_ALLOC__SIZE				1
    121 #define GEN75_MI_URB_ATOMIC_ALLOC_DW0_OFFSET__MASK		0x000ff000
    122 #define GEN75_MI_URB_ATOMIC_ALLOC_DW0_OFFSET__SHIFT		12
    123 #define GEN75_MI_URB_ATOMIC_ALLOC_DW0_SIZE__MASK		0x000001ff
    124 #define GEN75_MI_URB_ATOMIC_ALLOC_DW0_SIZE__SHIFT		0
    125 
    126 #define GEN6_MI_BATCH_BUFFER_END__SIZE				1
    127 
    128 #define GEN7_MI_PREDICATE__SIZE					1
    129 #define GEN7_MI_PREDICATE_DW0_LOADOP__MASK			0x000000c0
    130 #define GEN7_MI_PREDICATE_DW0_LOADOP__SHIFT			6
    131 #define GEN7_MI_PREDICATE_DW0_LOADOP_KEEP			(0x0 << 6)
    132 #define GEN7_MI_PREDICATE_DW0_LOADOP_LOAD			(0x2 << 6)
    133 #define GEN7_MI_PREDICATE_DW0_LOADOP_LOADINV			(0x3 << 6)
    134 #define GEN7_MI_PREDICATE_DW0_COMBINEOP__MASK			0x00000018
    135 #define GEN7_MI_PREDICATE_DW0_COMBINEOP__SHIFT			3
    136 #define GEN7_MI_PREDICATE_DW0_COMBINEOP_SET			(0x0 << 3)
    137 #define GEN7_MI_PREDICATE_DW0_COMBINEOP_AND			(0x1 << 3)
    138 #define GEN7_MI_PREDICATE_DW0_COMBINEOP_OR			(0x2 << 3)
    139 #define GEN7_MI_PREDICATE_DW0_COMBINEOP_XOR			(0x3 << 3)
    140 #define GEN7_MI_PREDICATE_DW0_COMPAREOP__MASK			0x00000003
    141 #define GEN7_MI_PREDICATE_DW0_COMPAREOP__SHIFT			0
    142 #define GEN7_MI_PREDICATE_DW0_COMPAREOP_TRUE			0x0
    143 #define GEN7_MI_PREDICATE_DW0_COMPAREOP_FALSE			0x1
    144 #define GEN7_MI_PREDICATE_DW0_COMPAREOP_SRCS_EQUAL		0x2
    145 #define GEN7_MI_PREDICATE_DW0_COMPAREOP_DELTAS_EQUAL		0x3
    146 
    147 #define GEN7_MI_URB_CLEAR__SIZE					2
    148 
    149 #define GEN7_MI_URB_CLEAR_DW1_LENGTH__MASK			0x3fff0000
    150 #define GEN7_MI_URB_CLEAR_DW1_LENGTH__SHIFT			16
    151 #define GEN7_MI_URB_CLEAR_DW1_OFFSET__MASK			0x00007fff
    152 #define GEN7_MI_URB_CLEAR_DW1_OFFSET__SHIFT			0
    153 
    154 #define GEN75_MI_MATH__SIZE					65
    155 
    156 #define GEN75_MI_MATH_DW_OP__MASK				0xfff00000
    157 #define GEN75_MI_MATH_DW_OP__SHIFT				20
    158 #define GEN75_MI_MATH_DW_SRC1__MASK				0x000ffc00
    159 #define GEN75_MI_MATH_DW_SRC1__SHIFT				10
    160 #define GEN75_MI_MATH_DW_SRC2__MASK				0x000007ff
    161 #define GEN75_MI_MATH_DW_SRC2__SHIFT				0
    162 
    163 #define GEN8_MI_SEMAPHORE_SIGNAL__SIZE				2
    164 #define GEN8_MI_SEMAPHORE_SIGNAL_DW0_POST_SYNC_OP		(0x1 << 21)
    165 #define GEN8_MI_SEMAPHORE_SIGNAL_DW0_ENGINE__MASK		0x00038000
    166 #define GEN8_MI_SEMAPHORE_SIGNAL_DW0_ENGINE__SHIFT		15
    167 #define GEN8_MI_SEMAPHORE_SIGNAL_DW0_ENGINE_RCS			(0x0 << 15)
    168 #define GEN8_MI_SEMAPHORE_SIGNAL_DW0_ENGINE_VCS0		(0x1 << 15)
    169 #define GEN8_MI_SEMAPHORE_SIGNAL_DW0_ENGINE_BCS			(0x2 << 15)
    170 #define GEN8_MI_SEMAPHORE_SIGNAL_DW0_ENGINE_VECS		(0x3 << 15)
    171 #define GEN8_MI_SEMAPHORE_SIGNAL_DW0_ENGINE_VCS1		(0x4 << 15)
    172 
    173 
    174 #define GEN8_MI_SEMAPHORE_WAIT__SIZE				4
    175 #define GEN8_MI_SEMAPHORE_WAIT_DW0_USE_GGTT			(0x1 << 22)
    176 #define GEN8_MI_SEMAPHORE_WAIT_DW0_WAIT_MODE__MASK		0x00008000
    177 #define GEN8_MI_SEMAPHORE_WAIT_DW0_WAIT_MODE__SHIFT		15
    178 #define GEN8_MI_SEMAPHORE_WAIT_DW0_WAIT_MODE_SIGNAL		(0x0 << 15)
    179 #define GEN8_MI_SEMAPHORE_WAIT_DW0_WAIT_MODE_POLL		(0x1 << 15)
    180 #define GEN8_MI_SEMAPHORE_WAIT_DW0_OP__MASK			0x00007000
    181 #define GEN8_MI_SEMAPHORE_WAIT_DW0_OP__SHIFT			12
    182 #define GEN8_MI_SEMAPHORE_WAIT_DW0_OP_SAD_GREATER_THAN_SDD	(0x0 << 12)
    183 #define GEN8_MI_SEMAPHORE_WAIT_DW0_OP_SAD_GREATER_THAN_OR_EQUAL_SDD	(0x1 << 12)
    184 #define GEN8_MI_SEMAPHORE_WAIT_DW0_OP_SAD_LESS_THAN_SDD		(0x2 << 12)
    185 #define GEN8_MI_SEMAPHORE_WAIT_DW0_OP_SAD_LESS_THAN_OR_EQUAL_SDD	(0x3 << 12)
    186 #define GEN8_MI_SEMAPHORE_WAIT_DW0_OP_SAD_EQUAL_SDD		(0x4 << 12)
    187 #define GEN8_MI_SEMAPHORE_WAIT_DW0_OP_SAD_NO_EQUAL_SDD		(0x5 << 12)
    188 
    189 
    190 #define GEN8_MI_SEMAPHORE_WAIT_DW2_ADDR_ADDR__MASK		0xfffffffc
    191 #define GEN8_MI_SEMAPHORE_WAIT_DW2_ADDR_ADDR__SHIFT		2
    192 #define GEN8_MI_SEMAPHORE_WAIT_DW2_ADDR_ADDR__SHR		2
    193 
    194 
    195 #define GEN6_MI_STORE_DATA_IMM__SIZE				6
    196 #define GEN6_MI_STORE_DATA_IMM_DW0_USE_GGTT			(0x1 << 22)
    197 #define GEN8_MI_STORE_DATA_IMM_DW0_STORE_QWORD			(0x1 << 21)
    198 
    199 
    200 #define GEN6_MI_STORE_DATA_IMM_DW2_ADDR__MASK			0xfffffffc
    201 #define GEN6_MI_STORE_DATA_IMM_DW2_ADDR__SHIFT			2
    202 #define GEN6_MI_STORE_DATA_IMM_DW2_ADDR__SHR			2
    203 
    204 
    205 
    206 
    207 #define GEN6_MI_LOAD_REGISTER_IMM__SIZE				3
    208 #define GEN6_MI_LOAD_REGISTER_IMM_DW0_WRITE_DISABLES__MASK	0x00000f00
    209 #define GEN6_MI_LOAD_REGISTER_IMM_DW0_WRITE_DISABLES__SHIFT	8
    210 
    211 #define GEN6_MI_LOAD_REGISTER_IMM_DW1_REG__MASK			0x007ffffc
    212 #define GEN6_MI_LOAD_REGISTER_IMM_DW1_REG__SHIFT		2
    213 #define GEN6_MI_LOAD_REGISTER_IMM_DW1_REG__SHR			2
    214 
    215 
    216 #define GEN6_MI_STORE_REGISTER_MEM__SIZE			4
    217 #define GEN6_MI_STORE_REGISTER_MEM_DW0_USE_GGTT			(0x1 << 22)
    218 #define GEN75_MI_STORE_REGISTER_MEM_DW0_PREDICATE_ENABLE	(0x1 << 21)
    219 
    220 #define GEN6_MI_STORE_REGISTER_MEM_DW1_REG__MASK		0x007ffffc
    221 #define GEN6_MI_STORE_REGISTER_MEM_DW1_REG__SHIFT		2
    222 #define GEN6_MI_STORE_REGISTER_MEM_DW1_REG__SHR			2
    223 
    224 #define GEN6_MI_STORE_REGISTER_MEM_DW2_ADDR__MASK		0xfffffffc
    225 #define GEN6_MI_STORE_REGISTER_MEM_DW2_ADDR__SHIFT		2
    226 #define GEN6_MI_STORE_REGISTER_MEM_DW2_ADDR__SHR		2
    227 
    228 
    229 #define GEN6_MI_FLUSH_DW__SIZE					5
    230 #define GEN6_MI_FLUSH_DW_DW0_WRITE__MASK			0x0000c000
    231 #define GEN6_MI_FLUSH_DW_DW0_WRITE__SHIFT			14
    232 #define GEN6_MI_FLUSH_DW_DW0_WRITE_NONE				(0x0 << 14)
    233 #define GEN6_MI_FLUSH_DW_DW0_WRITE_IMM				(0x1 << 14)
    234 #define GEN6_MI_FLUSH_DW_DW0_WRITE_TIMESTAMP			(0x3 << 14)
    235 
    236 #define GEN6_MI_FLUSH_DW_DW1_USE_GGTT				(0x1 << 2)
    237 #define GEN6_MI_FLUSH_DW_DW1_ADDR__MASK				0xfffffff8
    238 #define GEN6_MI_FLUSH_DW_DW1_ADDR__SHIFT			3
    239 #define GEN6_MI_FLUSH_DW_DW1_ADDR__SHR				3
    240 
    241 
    242 
    243 
    244 #define GEN6_MI_REPORT_PERF_COUNT__SIZE				3
    245 
    246 #define GEN6_MI_REPORT_PERF_COUNT_DW1_CORE_MODE_ENABLE		(0x1 << 4)
    247 #define GEN6_MI_REPORT_PERF_COUNT_DW1_USE_GGTT			(0x1 << 0)
    248 #define GEN6_MI_REPORT_PERF_COUNT_DW1_ADDR__MASK		0xffffffc0
    249 #define GEN6_MI_REPORT_PERF_COUNT_DW1_ADDR__SHIFT		6
    250 #define GEN6_MI_REPORT_PERF_COUNT_DW1_ADDR__SHR			6
    251 
    252 
    253 #define GEN7_MI_LOAD_REGISTER_MEM__SIZE				4
    254 #define GEN7_MI_LOAD_REGISTER_MEM_DW0_USE_GGTT			(0x1 << 22)
    255 #define GEN7_MI_LOAD_REGISTER_MEM_DW0_ASYNC_MODE_ENABLE		(0x1 << 21)
    256 
    257 #define GEN7_MI_LOAD_REGISTER_MEM_DW1_REG__MASK			0x007ffffc
    258 #define GEN7_MI_LOAD_REGISTER_MEM_DW1_REG__SHIFT		2
    259 #define GEN7_MI_LOAD_REGISTER_MEM_DW1_REG__SHR			2
    260 
    261 #define GEN7_MI_LOAD_REGISTER_MEM_DW2_ADDR__MASK		0xfffffffc
    262 #define GEN7_MI_LOAD_REGISTER_MEM_DW2_ADDR__SHIFT		2
    263 #define GEN7_MI_LOAD_REGISTER_MEM_DW2_ADDR__SHR			2
    264 
    265 
    266 #define GEN75_MI_LOAD_REGISTER_REG__SIZE			3
    267 
    268 #define GEN75_MI_LOAD_REGISTER_REG_DW1_SRC_REG__MASK		0x007ffffc
    269 #define GEN75_MI_LOAD_REGISTER_REG_DW1_SRC_REG__SHIFT		2
    270 #define GEN75_MI_LOAD_REGISTER_REG_DW1_SRC_REG__SHR		2
    271 
    272 #define GEN75_MI_LOAD_REGISTER_REG_DW2_DST_REG__MASK		0x007ffffc
    273 #define GEN75_MI_LOAD_REGISTER_REG_DW2_DST_REG__SHIFT		2
    274 #define GEN75_MI_LOAD_REGISTER_REG_DW2_DST_REG__SHR		2
    275 
    276 #define GEN75_MI_RS_STORE_DATA_IMM__SIZE			6
    277 #define GEN75_MI_RS_STORE_DATA_IMM_DW0_USE_GGTT			(0x1 << 22)
    278 
    279 
    280 #define GEN75_MI_RS_STORE_DATA_IMM_DW2_ADDR__MASK		0xfffffffc
    281 #define GEN75_MI_RS_STORE_DATA_IMM_DW2_ADDR__SHIFT		2
    282 #define GEN75_MI_RS_STORE_DATA_IMM_DW2_ADDR__SHR		2
    283 
    284 
    285 
    286 
    287 #define GEN75_MI_LOAD_URB_MEM__SIZE				4
    288 
    289 #define GEN75_MI_LOAD_URB_MEM_DW1_ADDR__MASK			0x00007ffc
    290 #define GEN75_MI_LOAD_URB_MEM_DW1_ADDR__SHIFT			2
    291 #define GEN75_MI_LOAD_URB_MEM_DW1_ADDR__SHR			2
    292 
    293 #define GEN75_MI_LOAD_URB_MEM_DW2_ADDR__MASK			0xffffffc0
    294 #define GEN75_MI_LOAD_URB_MEM_DW2_ADDR__SHIFT			6
    295 #define GEN75_MI_LOAD_URB_MEM_DW2_ADDR__SHR			6
    296 
    297 
    298 #define GEN75_MI_STORE_URB_MEM__SIZE				4
    299 
    300 #define GEN75_MI_STORE_URB_MEM_DW1_ADDR__MASK			0x00007ffc
    301 #define GEN75_MI_STORE_URB_MEM_DW1_ADDR__SHIFT			2
    302 #define GEN75_MI_STORE_URB_MEM_DW1_ADDR__SHR			2
    303 
    304 #define GEN75_MI_STORE_URB_MEM_DW2_ADDR__MASK			0xffffffc0
    305 #define GEN75_MI_STORE_URB_MEM_DW2_ADDR__SHIFT			6
    306 #define GEN75_MI_STORE_URB_MEM_DW2_ADDR__SHR			6
    307 
    308 
    309 #define GEN8_MI_COPY_MEM_MEM__SIZE				5
    310 #define GEN8_MI_COPY_MEM_MEM_DW0_USE_GGTT_SRC			(0x1 << 22)
    311 #define GEN8_MI_COPY_MEM_MEM_DW0_USE_GGTT_DST			(0x1 << 21)
    312 
    313 #define GEN8_MI_COPY_MEM_MEM_DW1_DST_ADDR__MASK			0xfffffffc
    314 #define GEN8_MI_COPY_MEM_MEM_DW1_DST_ADDR__SHIFT		2
    315 #define GEN8_MI_COPY_MEM_MEM_DW1_DST_ADDR__SHR			2
    316 
    317 
    318 #define GEN8_MI_COPY_MEM_MEM_DW3_SRC_ADDR__MASK			0xfffffffc
    319 #define GEN8_MI_COPY_MEM_MEM_DW3_SRC_ADDR__SHIFT		2
    320 #define GEN8_MI_COPY_MEM_MEM_DW3_SRC_ADDR__SHR			2
    321 
    322 
    323 #define GEN8_MI_ATOMIC__SIZE					11
    324 #define GEN8_MI_ATOMIC_DW0_USE_GGTT				(0x1 << 22)
    325 #define GEN8_MI_ATOMIC_DW0_POST_SYNC_OP				(0x1 << 21)
    326 #define GEN8_MI_ATOMIC_DW0_SIZE__MASK				0x00180000
    327 #define GEN8_MI_ATOMIC_DW0_SIZE__SHIFT				19
    328 #define GEN8_MI_ATOMIC_DW0_SIZE_DWORD				(0x0 << 19)
    329 #define GEN8_MI_ATOMIC_DW0_SIZE_QWORD				(0x1 << 19)
    330 #define GEN8_MI_ATOMIC_DW0_SIZE_OWORD				(0x2 << 19)
    331 #define GEN8_MI_ATOMIC_DW0_INLINE_DATA				(0x1 << 18)
    332 #define GEN8_MI_ATOMIC_DW0_CS_STALL				(0x1 << 17)
    333 #define GEN8_MI_ATOMIC_DW0_RETURN_DATA_CONTROL			(0x1 << 16)
    334 #define GEN8_MI_ATOMIC_DW0_OP__MASK				0x0000ff00
    335 #define GEN8_MI_ATOMIC_DW0_OP__SHIFT				8
    336 
    337 #define GEN8_MI_ATOMIC_DW1_ADDR__MASK				0xfffffffc
    338 #define GEN8_MI_ATOMIC_DW1_ADDR__SHIFT				2
    339 #define GEN8_MI_ATOMIC_DW1_ADDR__SHR				2
    340 
    341 
    342 
    343 #define GEN6_MI_BATCH_BUFFER_START__SIZE			3
    344 #define GEN75_MI_BATCH_BUFFER_START_DW0_SECOND_LEVEL		(0x1 << 22)
    345 #define GEN75_MI_BATCH_BUFFER_START_DW0_ADD_OFFSET_ENABLE	(0x1 << 16)
    346 #define GEN75_MI_BATCH_BUFFER_START_DW0_PREDICATION_ENABLE	(0x1 << 15)
    347 #define GEN75_MI_BATCH_BUFFER_START_DW0_NON_PRIVILEGED		(0x1 << 13)
    348 #define GEN6_MI_BATCH_BUFFER_START_DW0_CLEAR_COMMAND_BUFFER	(0x1 << 11)
    349 #define GEN75_MI_BATCH_BUFFER_START_DW0_RS_ENABLE		(0x1 << 10)
    350 #define GEN6_MI_BATCH_BUFFER_START_DW0_USE_PPGTT		(0x1 << 8)
    351 
    352 #define GEN6_MI_BATCH_BUFFER_START_DW1_ADDR__MASK		0xfffffffc
    353 #define GEN6_MI_BATCH_BUFFER_START_DW1_ADDR__SHIFT		2
    354 #define GEN6_MI_BATCH_BUFFER_START_DW1_ADDR__SHR		2
    355 
    356 
    357 
    358 #endif /* GEN_MI_XML */
    359