1 #ifndef GEN_REGS_XML 2 #define GEN_REGS_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 https://github.com/olvaffe/envytools/ 8 git clone https://github.com/olvaffe/envytools.git 9 10 Copyright (C) 2014-2015 by the following authors: 11 - Chia-I Wu <olvaffe (at) gmail.com> (olv) 12 13 Permission is hereby granted, free of charge, to any person obtaining 14 a copy of this software and associated documentation files (the 15 "Software"), to deal in the Software without restriction, including 16 without limitation the rights to use, copy, modify, merge, publish, 17 distribute, sublicense, and/or sell copies of the Software, and to 18 permit persons to whom the Software is furnished to do so, subject to 19 the following conditions: 20 21 The above copyright notice and this permission notice (including the 22 next paragraph) shall be included in all copies or substantial 23 portions of the Software. 24 25 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 28 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 29 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 30 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 31 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 32 */ 33 34 35 #define GEN6_REG_MASK__MASK 0xffff0000 36 #define GEN6_REG_MASK__SHIFT 16 37 #define GEN6_REG__SIZE 0x400000 38 #define GEN6_REG_NOPID 0x2094 39 40 41 #define GEN6_REG_SO_PRIM_STORAGE_NEEDED 0x2280 42 43 #define GEN6_REG_SO_NUM_PRIMS_WRITTEN 0x2288 44 45 46 #define GEN7_REG_TS_GPGPU_THREADS_DISPATCHED 0x2290 47 48 #define GEN7_REG_HS_INVOCATION_COUNT 0x2300 49 50 #define GEN7_REG_DS_INVOCATION_COUNT 0x2308 51 52 #define GEN6_REG_IA_VERTICES_COUNT 0x2310 53 54 #define GEN6_REG_IA_PRIMITIVES_COUNT 0x2318 55 56 #define GEN6_REG_VS_INVOCATION_COUNT 0x2320 57 58 #define GEN6_REG_GS_INVOCATION_COUNT 0x2328 59 60 #define GEN6_REG_GS_PRIMITIVES_COUNT 0x2330 61 62 #define GEN6_REG_CL_INVOCATION_COUNT 0x2338 63 64 #define GEN6_REG_CL_PRIMITIVES_COUNT 0x2340 65 66 #define GEN6_REG_PS_INVOCATION_COUNT 0x2348 67 68 #define GEN6_REG_PS_DEPTH_COUNT 0x2350 69 70 #define GEN6_REG_TIMESTAMP 0x2358 71 72 #define GEN6_REG_OACONTROL 0x2360 73 #define GEN6_REG_OACONTROL_COUNTER_SELECT__MASK 0x0000001c 74 #define GEN6_REG_OACONTROL_COUNTER_SELECT__SHIFT 2 75 #define GEN6_REG_OACONTROL_PERFORMANCE_COUNTER_ENABLE (0x1 << 0) 76 77 78 #define GEN7_REG_MI_PREDICATE_SRC0 0x2400 79 80 #define GEN7_REG_MI_PREDICATE_SRC1 0x2408 81 82 #define GEN7_REG_MI_PREDICATE_DATA 0x2410 83 84 #define GEN7_REG_MI_PREDICATE_RESULT 0x2418 85 86 #define GEN75_REG_MI_PREDICATE_RESULT_1 0x241c 87 88 #define GEN75_REG_MI_PREDICATE_RESULT_2 0x2214 89 90 #define GEN7_REG_3DPRIM_END_OFFSET 0x2420 91 92 #define GEN7_REG_3DPRIM_START_VERTEX 0x2430 93 94 #define GEN7_REG_3DPRIM_VERTEX_COUNT 0x2434 95 96 #define GEN7_REG_3DPRIM_INSTANCE_COUNT 0x2438 97 98 #define GEN7_REG_3DPRIM_START_INSTANCE 0x243c 99 100 #define GEN7_REG_3DPRIM_BASE_VERTEX 0x2440 101 102 #define GEN75_REG_CS_GPR(i0) (0x2600 + 0x8*(i0)) 103 #define GEN75_REG_CS_GPR__ESIZE 0x8 104 #define GEN75_REG_CS_GPR__LEN 0x10 105 106 #define GEN7_REG_GPGPU_DISPATCHDIMX 0x2500 107 108 #define GEN7_REG_GPGPU_DISPATCHDIMY 0x2504 109 110 #define GEN7_REG_GPGPU_DISPATCHDIMZ 0x2508 111 112 113 #define GEN7_REG_SO_NUM_PRIMS_WRITTEN(i0) (0x5200 + 0x8*(i0)) 114 #define GEN7_REG_SO_NUM_PRIMS_WRITTEN__ESIZE 0x8 115 #define GEN7_REG_SO_NUM_PRIMS_WRITTEN__LEN 0x4 116 117 #define GEN7_REG_SO_PRIM_STORAGE_NEEDED(i0) (0x5240 + 0x8*(i0)) 118 #define GEN7_REG_SO_PRIM_STORAGE_NEEDED__ESIZE 0x8 119 #define GEN7_REG_SO_PRIM_STORAGE_NEEDED__LEN 0x4 120 121 #define GEN7_REG_SO_WRITE_OFFSET(i0) (0x5280 + 0x8*(i0)) 122 #define GEN7_REG_SO_WRITE_OFFSET__ESIZE 0x8 123 #define GEN7_REG_SO_WRITE_OFFSET__LEN 0x4 124 125 126 #define GEN7_REG_CACHE_MODE_0 0x7000 127 #define GEN7_REG_CACHE_MODE_0_HIZ_RAW_STALL_OPT_DISABLE (0x1 << 2) 128 129 #define GEN7_REG_CACHE_MODE_1 0x7004 130 #define GEN8_REG_CACHE_MODE_1_NP_EARLY_Z_FAILS_DISABLE (0x1 << 13) 131 #define GEN8_REG_CACHE_MODE_1_NP_PMA_FIX_ENABLE (0x1 << 11) 132 133 134 #define GEN8_REG_L3CNTLREG 0x7034 135 136 137 #define GEN7_REG_L3SQCREG1 0xb010 138 #define GEN7_REG_L3SQCREG1_CON4DCUNC (0x1 << 24) 139 #define GEN7_REG_L3SQCREG1_SQGHPCI__MASK 0x00ff0000 140 #define GEN7_REG_L3SQCREG1_SQGHPCI__SHIFT 16 141 #define GEN7_REG_L3SQCREG1_SQGHPCI_18_6 (0x73 << 16) 142 #define GEN75_REG_L3SQCREG1_SQGPCI__MASK 0x00f80000 143 #define GEN75_REG_L3SQCREG1_SQGPCI__SHIFT 19 144 #define GEN75_REG_L3SQCREG1_SQGPCI_24 (0xc << 19) 145 #define GEN75_REG_L3SQCREG1_SQHPCI__MASK 0x0007c000 146 #define GEN75_REG_L3SQCREG1_SQHPCI__SHIFT 14 147 #define GEN75_REG_L3SQCREG1_SQHPCI_8 (0x4 << 14) 148 149 #define GEN7_REG_L3SQCREG2 0xb014 150 151 #define GEN7_REG_L3SQCREG3 0xb018 152 153 #define GEN7_REG_L3CNTLREG1 0xb01c 154 155 #define GEN7_REG_L3CNTLREG2 0xb020 156 #define GEN7_REG_L3CNTLREG2_DCWASLMB (0x1 << 27) 157 #define GEN7_REG_L3CNTLREG2_DCWASS__MASK 0x07e00000 158 #define GEN7_REG_L3CNTLREG2_DCWASS__SHIFT 21 159 #define GEN7_REG_L3CNTLREG2_ROCPSLMB (0x1 << 20) 160 #define GEN7_REG_L3CNTLREG2_RDOCPL__MASK 0x000fc000 161 #define GEN7_REG_L3CNTLREG2_RDOCPL__SHIFT 14 162 #define GEN7_REG_L3CNTLREG2_URBSLMB (0x1 << 7) 163 #define GEN7_REG_L3CNTLREG2_URBALL__MASK 0x0000007e 164 #define GEN7_REG_L3CNTLREG2_URBALL__SHIFT 1 165 #define GEN7_REG_L3CNTLREG2_SLMMENB (0x1 << 0) 166 167 #define GEN7_REG_L3CNTLREG3 0xb024 168 #define GEN7_REG_L3CNTLREG3_TWALSLMB (0x1 << 21) 169 #define GEN7_REG_L3CNTLREG3_TXWYALL__MASK 0x001f8000 170 #define GEN7_REG_L3CNTLREG3_TXWYALL__SHIFT 15 171 #define GEN7_REG_L3CNTLREG3_CWASLMB (0x1 << 14) 172 #define GEN7_REG_L3CNTLREG3_CTWYALL__MASK 0x00003f00 173 #define GEN7_REG_L3CNTLREG3_CTWYALL__SHIFT 8 174 #define GEN7_REG_L3CNTLREG3_ISWYSLMB (0x1 << 7) 175 #define GEN7_REG_L3CNTLREG3_ISWYALL__MASK 0x0000007e 176 #define GEN7_REG_L3CNTLREG3_ISWYALL__SHIFT 1 177 178 #define GEN6_REG_BCS_SWCTRL 0x22200 179 #define GEN6_REG_BCS_SWCTRL_DST_TILING_Y (0x1 << 1) 180 #define GEN6_REG_BCS_SWCTRL_SRC_TILING_Y (0x1 << 0) 181 182 183 #endif /* GEN_REGS_XML */ 184
