1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __GIC_COMMON_H__ 8 #define __GIC_COMMON_H__ 9 10 /******************************************************************************* 11 * GIC Distributor interface general definitions 12 ******************************************************************************/ 13 /* Constants to categorise interrupts */ 14 #define MIN_SGI_ID 0 15 #define MIN_SEC_SGI_ID 8 16 #define MIN_PPI_ID 16 17 #define MIN_SPI_ID 32 18 #define MAX_SPI_ID 1019 19 20 #define TOTAL_SPI_INTR_NUM (MAX_SPI_ID - MIN_SPI_ID + 1) 21 #define TOTAL_PCPU_INTR_NUM (MIN_SPI_ID - MIN_SGI_ID) 22 23 /* Mask for the priority field common to all GIC interfaces */ 24 #define GIC_PRI_MASK 0xff 25 26 /* Mask for the configuration field common to all GIC interfaces */ 27 #define GIC_CFG_MASK 0x3 28 29 /* Constant to indicate a spurious interrupt in all GIC versions */ 30 #define GIC_SPURIOUS_INTERRUPT 1023 31 32 /* Interrupt configurations */ 33 #define GIC_INTR_CFG_LEVEL 0 34 #define GIC_INTR_CFG_EDGE 1 35 36 /* Constants to categorise priorities */ 37 #define GIC_HIGHEST_SEC_PRIORITY 0 38 #define GIC_LOWEST_SEC_PRIORITY 127 39 #define GIC_HIGHEST_NS_PRIORITY 128 40 #define GIC_LOWEST_NS_PRIORITY 254 /* 255 would disable an interrupt */ 41 42 /******************************************************************************* 43 * GIC Distributor interface register offsets that are common to GICv3 & GICv2 44 ******************************************************************************/ 45 #define GICD_CTLR 0x0 46 #define GICD_TYPER 0x4 47 #define GICD_IIDR 0x8 48 #define GICD_IGROUPR 0x80 49 #define GICD_ISENABLER 0x100 50 #define GICD_ICENABLER 0x180 51 #define GICD_ISPENDR 0x200 52 #define GICD_ICPENDR 0x280 53 #define GICD_ISACTIVER 0x300 54 #define GICD_ICACTIVER 0x380 55 #define GICD_IPRIORITYR 0x400 56 #define GICD_ICFGR 0xc00 57 #define GICD_NSACR 0xe00 58 59 /* GICD_CTLR bit definitions */ 60 #define CTLR_ENABLE_G0_SHIFT 0 61 #define CTLR_ENABLE_G0_MASK 0x1 62 #define CTLR_ENABLE_G0_BIT (1 << CTLR_ENABLE_G0_SHIFT) 63 64 65 /******************************************************************************* 66 * GIC Distributor interface register constants that are common to GICv3 & GICv2 67 ******************************************************************************/ 68 #define PIDR2_ARCH_REV_SHIFT 4 69 #define PIDR2_ARCH_REV_MASK 0xf 70 71 /* GICv3 revision as reported by the PIDR2 register */ 72 #define ARCH_REV_GICV3 0x3 73 /* GICv2 revision as reported by the PIDR2 register */ 74 #define ARCH_REV_GICV2 0x2 75 76 #define IGROUPR_SHIFT 5 77 #define ISENABLER_SHIFT 5 78 #define ICENABLER_SHIFT ISENABLER_SHIFT 79 #define ISPENDR_SHIFT 5 80 #define ICPENDR_SHIFT ISPENDR_SHIFT 81 #define ISACTIVER_SHIFT 5 82 #define ICACTIVER_SHIFT ISACTIVER_SHIFT 83 #define IPRIORITYR_SHIFT 2 84 #define ITARGETSR_SHIFT 2 85 #define ICFGR_SHIFT 4 86 #define NSACR_SHIFT 4 87 88 /* GICD_TYPER shifts and masks */ 89 #define TYPER_IT_LINES_NO_SHIFT 0 90 #define TYPER_IT_LINES_NO_MASK 0x1f 91 92 /* Value used to initialize Normal world interrupt priorities four at a time */ 93 #define GICD_IPRIORITYR_DEF_VAL \ 94 (GIC_HIGHEST_NS_PRIORITY | \ 95 (GIC_HIGHEST_NS_PRIORITY << 8) | \ 96 (GIC_HIGHEST_NS_PRIORITY << 16) | \ 97 (GIC_HIGHEST_NS_PRIORITY << 24)) 98 99 #endif /* __GIC_COMMON_H__ */ 100
