1 /* 2 * Permission is hereby granted, free of charge, to any person obtaining a copy 3 * of this software and associated documentation files (the "Software"), to 4 * deal in the Software without restriction, including without limitation the 5 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 6 * sell copies of the Software, and to permit persons to whom the Software is 7 * furnished to do so, subject to the following conditions: 8 * 9 * The above copyright notice and this permission notice shall be included in 10 * all copies or substantial portions of the Software. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 15 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 16 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 17 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 18 * DEALINGS IN THE SOFTWARE. 19 */ 20 21 #ifndef __XEN_PUBLIC_HVM_PARAMS_H__ 22 #define __XEN_PUBLIC_HVM_PARAMS_H__ 23 24 #include "hvm_op.h" 25 26 /* 27 * Parameter space for HVMOP_{set,get}_param. 28 */ 29 30 /* 31 * How should CPU0 event-channel notifications be delivered? 32 * val[63:56] == 0: val[55:0] is a delivery GSI (Global System Interrupt). 33 * val[63:56] == 1: val[55:0] is a delivery PCI INTx line, as follows: 34 * Domain = val[47:32], Bus = val[31:16], 35 * DevFn = val[15: 8], IntX = val[ 1: 0] 36 * val[63:56] == 2: val[7:0] is a vector number, check for 37 * XENFEAT_hvm_callback_vector to know if this delivery 38 * method is available. 39 * If val == 0 then CPU0 event-channel notifications are not delivered. 40 */ 41 #define HVM_PARAM_CALLBACK_IRQ 0 42 43 /* 44 * These are not used by Xen. They are here for convenience of HVM-guest 45 * xenbus implementations. 46 */ 47 #define HVM_PARAM_STORE_PFN 1 48 #define HVM_PARAM_STORE_EVTCHN 2 49 50 #define HVM_PARAM_PAE_ENABLED 4 51 52 #define HVM_PARAM_IOREQ_PFN 5 53 54 #define HVM_PARAM_BUFIOREQ_PFN 6 55 #define HVM_PARAM_BUFIOREQ_EVTCHN 26 56 57 #if defined(MDE_CPU_IA32) || defined(MDE_CPU_X64) 58 59 /* Expose Viridian interfaces to this HVM guest? */ 60 #define HVM_PARAM_VIRIDIAN 9 61 62 #endif 63 64 /* 65 * Set mode for virtual timers (currently x86 only): 66 * delay_for_missed_ticks (default): 67 * Do not advance a vcpu's time beyond the correct delivery time for 68 * interrupts that have been missed due to preemption. Deliver missed 69 * interrupts when the vcpu is rescheduled and advance the vcpu's virtual 70 * time stepwise for each one. 71 * no_delay_for_missed_ticks: 72 * As above, missed interrupts are delivered, but guest time always tracks 73 * wallclock (i.e., real) time while doing so. 74 * no_missed_ticks_pending: 75 * No missed interrupts are held pending. Instead, to ensure ticks are 76 * delivered at some non-zero rate, if we detect missed ticks then the 77 * internal tick alarm is not disabled if the VCPU is preempted during the 78 * next tick period. 79 * one_missed_tick_pending: 80 * Missed interrupts are collapsed together and delivered as one 'late tick'. 81 * Guest time always tracks wallclock (i.e., real) time. 82 */ 83 #define HVM_PARAM_TIMER_MODE 10 84 #define HVMPTM_delay_for_missed_ticks 0 85 #define HVMPTM_no_delay_for_missed_ticks 1 86 #define HVMPTM_no_missed_ticks_pending 2 87 #define HVMPTM_one_missed_tick_pending 3 88 89 /* Boolean: Enable virtual HPET (high-precision event timer)? (x86-only) */ 90 #define HVM_PARAM_HPET_ENABLED 11 91 92 /* Identity-map page directory used by Intel EPT when CR0.PG=0. */ 93 #define HVM_PARAM_IDENT_PT 12 94 95 /* Device Model domain, defaults to 0. */ 96 #define HVM_PARAM_DM_DOMAIN 13 97 98 /* ACPI S state: currently support S0 and S3 on x86. */ 99 #define HVM_PARAM_ACPI_S_STATE 14 100 101 /* TSS used on Intel when CR0.PE=0. */ 102 #define HVM_PARAM_VM86_TSS 15 103 104 /* Boolean: Enable aligning all periodic vpts to reduce interrupts */ 105 #define HVM_PARAM_VPT_ALIGN 16 106 107 /* Console debug shared memory ring and event channel */ 108 #define HVM_PARAM_CONSOLE_PFN 17 109 #define HVM_PARAM_CONSOLE_EVTCHN 18 110 111 /* 112 * Select location of ACPI PM1a and TMR control blocks. Currently two locations 113 * are supported, specified by version 0 or 1 in this parameter: 114 * - 0: default, use the old addresses 115 * PM1A_EVT == 0x1f40; PM1A_CNT == 0x1f44; PM_TMR == 0x1f48 116 * - 1: use the new default qemu addresses 117 * PM1A_EVT == 0xb000; PM1A_CNT == 0xb004; PM_TMR == 0xb008 118 * You can find these address definitions in <hvm/ioreq.h> 119 */ 120 #define HVM_PARAM_ACPI_IOPORTS_LOCATION 19 121 122 /* Enable blocking memory events, async or sync (pause vcpu until response) 123 * onchangeonly indicates messages only on a change of value */ 124 #define HVM_PARAM_MEMORY_EVENT_CR0 20 125 #define HVM_PARAM_MEMORY_EVENT_CR3 21 126 #define HVM_PARAM_MEMORY_EVENT_CR4 22 127 #define HVM_PARAM_MEMORY_EVENT_INT3 23 128 #define HVM_PARAM_MEMORY_EVENT_SINGLE_STEP 25 129 #define HVM_PARAM_MEMORY_EVENT_MSR 30 130 131 #define HVMPME_MODE_MASK (3 << 0) 132 #define HVMPME_mode_disabled 0 133 #define HVMPME_mode_async 1 134 #define HVMPME_mode_sync 2 135 #define HVMPME_onchangeonly (1 << 2) 136 137 /* Boolean: Enable nestedhvm (hvm only) */ 138 #define HVM_PARAM_NESTEDHVM 24 139 140 /* Params for the mem event rings */ 141 #define HVM_PARAM_PAGING_RING_PFN 27 142 #define HVM_PARAM_ACCESS_RING_PFN 28 143 #define HVM_PARAM_SHARING_RING_PFN 29 144 145 /* SHUTDOWN_* action in case of a triple fault */ 146 #define HVM_PARAM_TRIPLE_FAULT_REASON 31 147 148 #define HVM_NR_PARAMS 32 149 150 #endif /* __XEN_PUBLIC_HVM_PARAMS_H__ */ 151
