1 /** @file 2 Various register numbers and value bits based on the following publications: 3 - Intel(R) datasheet 316966-002 4 - Intel(R) datasheet 316972-004 5 6 Copyright (C) 2015, Red Hat, Inc. 7 Copyright (c) 2014, Gabriel L. Somlo <somlo (at) cmu.edu> 8 9 This program and the accompanying materials are licensed and made available 10 under the terms and conditions of the BSD License which accompanies this 11 distribution. The full text of the license may be found at 12 http://opensource.org/licenses/bsd-license.php 13 14 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT 15 WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 16 **/ 17 18 #ifndef __Q35_MCH_ICH9_H__ 19 #define __Q35_MCH_ICH9_H__ 20 21 #include <Library/PciLib.h> 22 23 // 24 // Host Bridge Device ID (DID) value for Q35/MCH 25 // 26 #define INTEL_Q35_MCH_DEVICE_ID 0x29C0 27 28 // 29 // B/D/F/Type: 0/0/0/PCI 30 // 31 #define DRAMC_REGISTER_Q35(Offset) PCI_LIB_ADDRESS (0, 0, 0, (Offset)) 32 33 #define MCH_GGC 0x52 34 #define MCH_GGC_IVD BIT1 35 36 #define MCH_PCIEXBAR_LOW 0x60 37 #define MCH_PCIEXBAR_LOWMASK 0x0FFFFFFF 38 #define MCH_PCIEXBAR_BUS_FF 0 39 #define MCH_PCIEXBAR_EN BIT0 40 41 #define MCH_PCIEXBAR_HIGH 0x64 42 #define MCH_PCIEXBAR_HIGHMASK 0xFFFFFFF0 43 44 #define MCH_SMRAM 0x9D 45 #define MCH_SMRAM_D_LCK BIT4 46 #define MCH_SMRAM_G_SMRAME BIT3 47 48 #define MCH_ESMRAMC 0x9E 49 #define MCH_ESMRAMC_H_SMRAME BIT7 50 #define MCH_ESMRAMC_E_SMERR BIT6 51 #define MCH_ESMRAMC_SM_CACHE BIT5 52 #define MCH_ESMRAMC_SM_L1 BIT4 53 #define MCH_ESMRAMC_SM_L2 BIT3 54 #define MCH_ESMRAMC_TSEG_8MB BIT2 55 #define MCH_ESMRAMC_TSEG_2MB BIT1 56 #define MCH_ESMRAMC_TSEG_1MB 0 57 #define MCH_ESMRAMC_TSEG_MASK (BIT2 | BIT1) 58 #define MCH_ESMRAMC_T_EN BIT0 59 60 #define MCH_GBSM 0xA4 61 #define MCH_GBSM_MB_SHIFT 20 62 63 #define MCH_BGSM 0xA8 64 #define MCH_BGSM_MB_SHIFT 20 65 66 #define MCH_TSEGMB 0xAC 67 #define MCH_TSEGMB_MB_SHIFT 20 68 69 #define MCH_TOLUD 0xB0 70 #define MCH_TOLUD_MB_SHIFT 4 71 72 // 73 // B/D/F/Type: 0/0x1f/0/PCI 74 // 75 #define POWER_MGMT_REGISTER_Q35(Offset) \ 76 PCI_LIB_ADDRESS (0, 0x1f, 0, (Offset)) 77 78 #define ICH9_PMBASE 0x40 79 #define ICH9_PMBASE_MASK (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | \ 80 BIT10 | BIT9 | BIT8 | BIT7) 81 82 #define ICH9_ACPI_CNTL 0x44 83 #define ICH9_ACPI_CNTL_ACPI_EN BIT7 84 85 #define ICH9_GEN_PMCON_1 0xA0 86 #define ICH9_GEN_PMCON_1_SMI_LOCK BIT4 87 88 #define ICH9_RCBA 0xF0 89 #define ICH9_RCBA_EN BIT0 90 91 // 92 // IO ports 93 // 94 #define ICH9_APM_CNT 0xB2 95 #define ICH9_APM_STS 0xB3 96 97 // 98 // IO ports relative to PMBASE 99 // 100 #define ICH9_PMBASE_OFS_SMI_EN 0x30 101 #define ICH9_SMI_EN_APMC_EN BIT5 102 #define ICH9_SMI_EN_GBL_SMI_EN BIT0 103 104 #define ICH9_ROOT_COMPLEX_BASE 0xFED1C000 105 106 #endif 107
